[PATCH 0/2] Enable the GICv2m extension support for IPQ8074/IPQ6018

[PATCH 0/2] Enable the GICv2m extension support for IPQ8074/IPQ6018

[Kathiravan T]

GIC used in the IPQ8074 and IPQ6018 family of SoCs has one instance of
GICv2m extension, which supports upto 32 MSI interrupts. This series
enables the support for the same.

Kathiravan T (2):
  arm64: dts: qcom: ipq8074: enable the GICv2m support
  arm64: dts: qcom: ipq6018: enable the GICv2m support

 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++++++++
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
 2 files changed, 18 insertions(+)

-- 
2.7.4

[PATCH 1/2] arm64: dts: qcom: ipq8074: enable the GICv2m support

[Kathiravan T]

GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension,
which supports upto 32 MSI interrupts. Lets add support for the same.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 26ba7ce9222c..7b0258407d10 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -620,9 +620,18 @@
 
 		intc: interrupt-controller@b000000 {
 			compatible = "qcom,msm-qgic2";
+			#address-cells = <1>;
+			#size-cells = <1>;
 			interrupt-controller;
 			#interrupt-cells = <0x3>;
 			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
+			ranges = <0 0xb00a000 0xffd>;
+
+			v2m@0 {
+				compatible = "arm,gic-v2m-frame";
+				msi-controller;
+				reg = <0x0 0xffd>;
+			};
 		};
 
 		timer {
-- 
2.7.4

[PATCH 2/2] arm64: dts: qcom: ipq6018: enable the GICv2m support

[Kathiravan T]

GIC used in the IPQ6018 SoCs has one instance of the GICv2m extension,
which supports upto 32 MSI interrupts. Lets add support for the same.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 66ec5615651d..b8171548f0e1 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -373,6 +373,8 @@
 
 		intc: interrupt-controller@b000000 {
 			compatible = "qcom,msm-qgic2";
+			#address-cells = <2>;
+			#size-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <0x3>;
 			reg =   <0x0 0x0b000000 0x0 0x1000>,  /*GICD*/
@@ -380,6 +382,13 @@
 				<0x0 0x0b001000 0x0 0x1000>,  /*GICH*/
 				<0x0 0x0b004000 0x0 0x1000>;  /*GICV*/
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			ranges = <0 0 0 0xb00a000 0 0xffd>;
+
+			v2m@0 {
+				compatible = "arm,gic-v2m-frame";
+				msi-controller;
+				reg = <0x0 0x0 0x0 0xffd>;
+			};
 		};
 
 		pcie_phy: phy@84000 {
-- 
2.7.4

Re: [PATCH 0/2] Enable the GICv2m extension support for IPQ8074/IPQ6018

[patchwork-bot+linux-arm-msm]

Hello:

This series was applied to qcom/linux.git (for-next)
by Bjorn Andersson <bjorn.andersson@linaro.org>:

On Tue, 8 Feb 2022 21:05:23 +0530 you wrote:
> GIC used in the IPQ8074 and IPQ6018 family of SoCs has one instance of
> GICv2m extension, which supports upto 32 MSI interrupts. This series
> enables the support for the same.
> 
> Kathiravan T (2):
>   arm64: dts: qcom: ipq8074: enable the GICv2m support
>   arm64: dts: qcom: ipq6018: enable the GICv2m support
> 
> [...]

Here is the summary with links:
  - [1/2] arm64: dts: qcom: ipq8074: enable the GICv2m support
    https://git.kernel.org/qcom/c/59892de947f0
  - [2/2] arm64: dts: qcom: ipq6018: enable the GICv2m support
    https://git.kernel.org/qcom/c/3d44861d006b

You are awesome, thank you!
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