From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>,
agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
sboyd@kernel.org, linus.walleij@linaro.org,
catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org,
arnd@arndb.de, dmitry.baryshkov@linaro.org,
marcel.ziswiler@toradex.com, nfraprado@collabora.com,
robimarko@gmail.com, quic_gurus@quicinc.com,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V2 8/9] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support
Date: Mon, 30 Jan 2023 13:25:50 +0100 [thread overview]
Message-ID: <1d8777f7-ec11-b68c-629e-b17d5772396b@linaro.org> (raw)
In-Reply-To: <20230130114702.20606-9-quic_kathirav@quicinc.com>
On 30.01.2023 12:47, Kathiravan Thirumoorthy wrote:
> From: Kathiravan T <quic_kathirav@quicinc.com>
>
> Add initial device tree support for the Qualcomm IPQ5332 SoC and
> MI01.2 board.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
[...]
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + tz_mem: tz@4a600000 {
> + no-map;
> + reg = <0x0 0x4a600000 0x0 0x200000>;
reg should come before no-map
> + };
> + };
> +
> + soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> +
> + tlmm: pinctrl@1000000 {
> + compatible = "qcom,ipq5332-tlmm";
> + reg = <0x01000000 0x300000>;
> + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 53>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + serial_0_pins: serial0-state {
> + pins = "gpio18", "gpio19";
> + function = "blsp0_uart0";
> + drive-strength = <8>;
> + bias-pull-up;
> + };
> + };
> +
> + gcc: clock-controller@1800000 {
> + compatible = "qcom,ipq5332-gcc";
> + reg = <0x01800000 0x80000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + clock-names = "xo",
> + "sleep_clk",
> + "pcie_2lane_phy_pipe_clk",
> + "pcie_2lane_phy_pipe_clk_x1",
> + "usb_pcie_wrapper_pipe_clk";
> + clocks = <&xo_board>,
> + <&sleep_clk>,
> + <0>,
> + <0>,
> + <0>;
> + };
> +
> + sdhc: mmc@7804000 {
> + compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
> +
> + interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&xo_board>;
> + clock-names = "iface", "core", "xo";
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + max-frequency = <192000000>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + blsp1_uart0: serial@78af000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x078af000 0x200>;
> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> + intc: interrupt-controller@b000000 {
> + compatible = "qcom,msm-qgic2";
> + reg = <0x0b000000 0x1000>, /* GICD */
> + <0x0b002000 0x1000>, /* GICC */
> + <0x0b001000 0x1000>, /* GICH */
> + <0x0b004000 0x1000>; /* GICV */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0b00c000 0x3000>;
> +
> + v2m0: v2m@0 {
> + compatible = "arm,gic-v2m-frame";
> + reg = <0x00000000 0xffd>;
> + msi-controller;
> + };
> +
> + v2m1: v2m@1 {
> + compatible = "arm,gic-v2m-frame";
> + reg = <0x00001000 0xffd>;
The unit address does not match the address part of the reg
property, dtbs_check will not succeed..
The rest lgtm
Konrad
> + msi-controller;
> + };
> +
> + v2m2: v2m@2 {
> + compatible = "arm,gic-v2m-frame";
> + reg = <0x00002000 0xffd>;
> + msi-controller;
> + };
> + };
> +
> + timer@b120000 {
> + compatible = "arm,armv7-timer-mem";
> + reg = <0x0b120000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + frame@b120000 {
> + reg = <0x0b121000 0x1000>,
> + <0x0b122000 0x1000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <0>;
> + };
> +
> + frame@b123000 {
> + reg = <0x0b123000 0x1000>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <1>;
> + status = "disabled";
> + };
> +
> + frame@b124000 {
> + reg = <0x0b124000 0x1000>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <2>;
> + status = "disabled";
> + };
> +
> + frame@b125000 {
> + reg = <0x0b125000 0x1000>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <3>;
> + status = "disabled";
> + };
> +
> + frame@b126000 {
> + reg = <0x0b126000 0x1000>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <4>;
> + status = "disabled";
> + };
> +
> + frame@b127000 {
> + reg = <0x0b127000 0x1000>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <5>;
> + status = "disabled";
> + };
> +
> + frame@b128000 {
> + reg = <0x0b128000 0x1000>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + frame-number = <6>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +};
next prev parent reply other threads:[~2023-01-30 12:25 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-30 11:46 [PATCH V2 0/9] Add minimal boot support for IPQ5332 Kathiravan Thirumoorthy
2023-01-30 11:46 ` [PATCH V2 1/9] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl Kathiravan Thirumoorthy
2023-01-31 19:31 ` Krzysztof Kozlowski
2023-01-30 11:46 ` [PATCH V2 2/9] pinctrl: qcom: Introduce IPQ5332 TLMM driver Kathiravan Thirumoorthy
2023-01-30 11:46 ` [PATCH V2 3/9] clk: qcom: Add STROMER PLUS PLL type for IPQ5332 Kathiravan Thirumoorthy
2023-01-30 11:46 ` [PATCH V2 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC Kathiravan Thirumoorthy
2023-01-31 19:28 ` Krzysztof Kozlowski
2023-01-31 21:06 ` Stephen Boyd
2023-01-30 11:46 ` [PATCH V2 6/9] dt-bindings: qcom: add ipq5332 boards Kathiravan Thirumoorthy
2023-01-31 19:29 ` Krzysztof Kozlowski
2023-01-30 11:47 ` [PATCH V2 7/9] dt-bindings: firmware: qcom,scm: document IPQ5332 SCM Kathiravan Thirumoorthy
2023-01-30 11:47 ` [PATCH V2 8/9] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support Kathiravan Thirumoorthy
2023-01-30 12:25 ` Konrad Dybcio [this message]
2023-02-01 5:37 ` Kathiravan T
2023-01-31 19:26 ` Krzysztof Kozlowski
2023-02-01 5:40 ` Kathiravan T
2023-01-30 11:47 ` [PATCH V2 9/9] arm64: defconfig: Enable IPQ5332 SoC base configs Kathiravan Thirumoorthy
2023-01-31 19:27 ` [PATCH V2 0/9] Add minimal boot support for IPQ5332 Krzysztof Kozlowski
2023-02-01 5:43 ` Kathiravan T
[not found] ` <20230130114702.20606-6-quic_kathirav@quicinc.com>
2023-01-31 21:09 ` [PATCH V2 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC Stephen Boyd
2023-02-01 5:45 ` Kathiravan T
2023-02-01 5:46 ` Kathiravan T
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