* [PATCH v4 01/18] dt-bindings: phy: remove qcom-dwc3-usb-phy
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
@ 2020-02-07 1:58 ` Bryan O'Donoghue
2020-02-07 1:58 ` [PATCH v4 02/18] dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding Bryan O'Donoghue
` (16 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:58 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Jorge Ramirez-Ortiz, Jorge Ramirez-Ortiz,
Bryan O'Donoghue
From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
This binding is not used by any driver.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../bindings/phy/qcom-dwc3-usb-phy.txt | 37 -------------------
1 file changed, 37 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
deleted file mode 100644
index a1697c27aecd..000000000000
--- a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-Qualcomm DWC3 HS AND SS PHY CONTROLLER
---------------------------------------
-
-DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
-controllers. Each DWC3 PHY controller should have its own node.
-
-Required properties:
-- compatible: should contain one of the following:
- - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
- - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
-- reg: offset and length of the DWC3 PHY controller register set
-- #phy-cells: must be zero
-- clocks: a list of phandles and clock-specifier pairs, one for each entry in
- clock-names.
-- clock-names: Should contain "ref" for the PHY reference clock
-
-Optional clocks:
- "xo" External reference clock
-
-Example:
- phy@100f8800 {
- compatible = "qcom,dwc3-hs-usb-phy";
- reg = <0x100f8800 0x30>;
- clocks = <&gcc USB30_0_UTMI_CLK>;
- clock-names = "ref";
- #phy-cells = <0>;
-
- };
-
- phy@100f8830 {
- compatible = "qcom,dwc3-ss-usb-phy";
- reg = <0x100f8830 0x30>;
- clocks = <&gcc USB30_0_MASTER_CLK>;
- clock-names = "ref";
- #phy-cells = <0>;
-
- };
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 02/18] dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
2020-02-07 1:58 ` [PATCH v4 01/18] dt-bindings: phy: remove qcom-dwc3-usb-phy Bryan O'Donoghue
@ 2020-02-07 1:58 ` Bryan O'Donoghue
2020-02-07 1:58 ` [PATCH v4 03/18] phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver Bryan O'Donoghue
` (15 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:58 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Sriharsha Allenki, Anu Ramanathan, Shawn Guo,
Andy Gross, Kishon Vijay Abraham I, Rob Herring, Mark Rutland,
Jorge Ramirez-Ortiz, devicetree, Bryan O'Donoghue
From: Sriharsha Allenki <sallenki@codeaurora.org>
Adds bindings for Qualcomm's 28 nm USB PHY supporting Low-Speed, Full-Speed
and Hi-Speed USB connectivity on Qualcomm chipsets.
[bod: Converted to YAML. Changed name dropping snps, 28nm components]
Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../bindings/phy/qcom,usb-hs-28nm.yaml | 90 +++++++++++++++++++
1 file changed, 90 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml
new file mode 100644
index 000000000000..ca6a0836b53c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
+
+maintainers:
+ - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+
+description: |
+ Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
+
+properties:
+ compatible:
+ enum:
+ - qcom,usb-hs-28nm-femtophy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: rpmcc ref clock
+ - description: PHY AHB clock
+ - description: Rentention clock
+
+ clock-names:
+ items:
+ - const: ref
+ - const: ahb
+ - const: sleep
+
+ resets:
+ items:
+ - description: PHY core reset
+ - description: POR reset
+
+ reset-names:
+ items:
+ - const: phy
+ - const: por
+
+ vdd-supply:
+ description: phandle to the regulator VDD supply node.
+
+ vdda1p8-supply:
+ description: phandle to the regulator 1.8V supply node.
+
+ vdda3p3-supply:
+ description: phandle to the regulator 3.3V supply node.
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdd-supply
+ - vdda1p8-supply
+ - vdda3p3-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-qcs404.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ usb2_phy_prim: phy@7a000 {
+ compatible = "qcom,usb-hs-28nm-femtophy";
+ reg = <0x0007a000 0x200>;
+ #phy-cells = <0>;
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "ahb", "sleep";
+ resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
+ <&gcc GCC_USB2A_PHY_BCR>;
+ reset-names = "phy", "por";
+ vdd-supply = <&vreg_l4_1p2>;
+ vdda1p8-supply = <&vreg_l5_1p8>;
+ vdda3p3-supply = <&vreg_l12_3p3>;
+ };
+...
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 03/18] phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
2020-02-07 1:58 ` [PATCH v4 01/18] dt-bindings: phy: remove qcom-dwc3-usb-phy Bryan O'Donoghue
2020-02-07 1:58 ` [PATCH v4 02/18] dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding Bryan O'Donoghue
@ 2020-02-07 1:58 ` Bryan O'Donoghue
2020-02-07 1:58 ` [PATCH v4 04/18] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings Bryan O'Donoghue
` (14 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:58 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Shawn Guo, Andy Gross, Kishon Vijay Abraham I,
Philipp Zabel, Jorge Ramirez-Ortiz, Bryan O'Donoghue
From: Shawn Guo <shawn.guo@linaro.org>
Adds Qualcomm 28nm Hi-Speed USB PHY driver support. This PHY is usually
paired with Synopsys DWC3 USB controllers on Qualcomm SoCs.
The PHY can come in two flavours femtoPHY or picoPHY. This commit adds
support for the femtoPHY with the possibility of extending to the picoPHY
with additional future commits. Both PHYs are on a 28 nanometer process
node.
[bod: Updated qcom_snps_hsphy_set_mode to match new method signature
Added disjunct on mode > 0
Removed regulator_set_voltage() in favour of setting floor in dts
Removed 'snps' and from driver name
Extended commit log to mention femtoPHY and picoPHY for future
reference.]
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
drivers/phy/qualcomm/Kconfig | 11 +
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c | 415 ++++++++++++++++++++
3 files changed, 427 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index e46824da29f6..9c56a7216f72 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -91,3 +91,14 @@ config PHY_QCOM_USB_HSIC
select GENERIC_PHY
help
Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
+
+config PHY_QCOM_USB_HS_28NM
+ tristate "Qualcomm 28nm High-Speed PHY"
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
+ select GENERIC_PHY
+ help
+ Enable this to support the Qualcomm Synopsys DesignWare Core 28nm
+ High-Speed PHY driver. This driver supports the Hi-Speed PHY which
+ is usually paired with either the ChipIdea or Synopsys DWC3 USB
+ IPs on MSM SOCs.
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index 283251d6a5d9..a4dab5329de0 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o
obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o
obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
+obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c b/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
new file mode 100644
index 000000000000..d998e65c89c8
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2009-2018, Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2020, Linaro Limited
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_graph.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+/* PHY register and bit definitions */
+#define PHY_CTRL_COMMON0 0x078
+#define SIDDQ BIT(2)
+#define PHY_IRQ_CMD 0x0d0
+#define PHY_INTR_MASK0 0x0d4
+#define PHY_INTR_CLEAR0 0x0dc
+#define DPDM_MASK 0x1e
+#define DP_1_0 BIT(4)
+#define DP_0_1 BIT(3)
+#define DM_1_0 BIT(2)
+#define DM_0_1 BIT(1)
+
+enum hsphy_voltage {
+ VOL_NONE,
+ VOL_MIN,
+ VOL_MAX,
+ VOL_NUM,
+};
+
+enum hsphy_vreg {
+ VDD,
+ VDDA_1P8,
+ VDDA_3P3,
+ VREG_NUM,
+};
+
+struct hsphy_init_seq {
+ int offset;
+ int val;
+ int delay;
+};
+
+struct hsphy_data {
+ const struct hsphy_init_seq *init_seq;
+ unsigned int init_seq_num;
+};
+
+struct hsphy_priv {
+ void __iomem *base;
+ struct clk_bulk_data *clks;
+ int num_clks;
+ struct reset_control *phy_reset;
+ struct reset_control *por_reset;
+ struct regulator_bulk_data vregs[VREG_NUM];
+ const struct hsphy_data *data;
+ enum phy_mode mode;
+};
+
+static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ struct hsphy_priv *priv = phy_get_drvdata(phy);
+
+ priv->mode = PHY_MODE_INVALID;
+
+ if (mode > 0)
+ priv->mode = mode;
+
+ return 0;
+}
+
+static void qcom_snps_hsphy_enable_hv_interrupts(struct hsphy_priv *priv)
+{
+ u32 val;
+
+ /* Clear any existing interrupts before enabling the interrupts */
+ val = readb(priv->base + PHY_INTR_CLEAR0);
+ val |= DPDM_MASK;
+ writeb(val, priv->base + PHY_INTR_CLEAR0);
+
+ writeb(0x0, priv->base + PHY_IRQ_CMD);
+ usleep_range(200, 220);
+ writeb(0x1, priv->base + PHY_IRQ_CMD);
+
+ /* Make sure the interrupts are cleared */
+ usleep_range(200, 220);
+
+ val = readb(priv->base + PHY_INTR_MASK0);
+ switch (priv->mode) {
+ case PHY_MODE_USB_HOST_HS:
+ case PHY_MODE_USB_HOST_FS:
+ case PHY_MODE_USB_DEVICE_HS:
+ case PHY_MODE_USB_DEVICE_FS:
+ val |= DP_1_0 | DM_0_1;
+ break;
+ case PHY_MODE_USB_HOST_LS:
+ case PHY_MODE_USB_DEVICE_LS:
+ val |= DP_0_1 | DM_1_0;
+ break;
+ default:
+ /* No device connected */
+ val |= DP_0_1 | DM_0_1;
+ break;
+ }
+ writeb(val, priv->base + PHY_INTR_MASK0);
+}
+
+static void qcom_snps_hsphy_disable_hv_interrupts(struct hsphy_priv *priv)
+{
+ u32 val;
+
+ val = readb(priv->base + PHY_INTR_MASK0);
+ val &= ~DPDM_MASK;
+ writeb(val, priv->base + PHY_INTR_MASK0);
+
+ /* Clear any pending interrupts */
+ val = readb(priv->base + PHY_INTR_CLEAR0);
+ val |= DPDM_MASK;
+ writeb(val, priv->base + PHY_INTR_CLEAR0);
+
+ writeb(0x0, priv->base + PHY_IRQ_CMD);
+ usleep_range(200, 220);
+
+ writeb(0x1, priv->base + PHY_IRQ_CMD);
+ usleep_range(200, 220);
+}
+
+static void qcom_snps_hsphy_enter_retention(struct hsphy_priv *priv)
+{
+ u32 val;
+
+ val = readb(priv->base + PHY_CTRL_COMMON0);
+ val |= SIDDQ;
+ writeb(val, priv->base + PHY_CTRL_COMMON0);
+}
+
+static void qcom_snps_hsphy_exit_retention(struct hsphy_priv *priv)
+{
+ u32 val;
+
+ val = readb(priv->base + PHY_CTRL_COMMON0);
+ val &= ~SIDDQ;
+ writeb(val, priv->base + PHY_CTRL_COMMON0);
+}
+
+static int qcom_snps_hsphy_power_on(struct phy *phy)
+{
+ struct hsphy_priv *priv = phy_get_drvdata(phy);
+ int ret;
+
+ ret = regulator_bulk_enable(VREG_NUM, priv->vregs);
+ if (ret)
+ return ret;
+ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
+ if (ret)
+ goto err_disable_regulator;
+ qcom_snps_hsphy_disable_hv_interrupts(priv);
+ qcom_snps_hsphy_exit_retention(priv);
+
+ return 0;
+
+err_disable_regulator:
+ regulator_bulk_disable(VREG_NUM, priv->vregs);
+
+ return ret;
+}
+
+static int qcom_snps_hsphy_power_off(struct phy *phy)
+{
+ struct hsphy_priv *priv = phy_get_drvdata(phy);
+
+ qcom_snps_hsphy_enter_retention(priv);
+ qcom_snps_hsphy_enable_hv_interrupts(priv);
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
+ regulator_bulk_disable(VREG_NUM, priv->vregs);
+
+ return 0;
+}
+
+static int qcom_snps_hsphy_reset(struct hsphy_priv *priv)
+{
+ int ret;
+
+ ret = reset_control_assert(priv->phy_reset);
+ if (ret)
+ return ret;
+
+ usleep_range(10, 15);
+
+ ret = reset_control_deassert(priv->phy_reset);
+ if (ret)
+ return ret;
+
+ usleep_range(80, 100);
+
+ return 0;
+}
+
+static void qcom_snps_hsphy_init_sequence(struct hsphy_priv *priv)
+{
+ const struct hsphy_data *data = priv->data;
+ const struct hsphy_init_seq *seq;
+ int i;
+
+ /* Device match data is optional. */
+ if (!data)
+ return;
+
+ seq = data->init_seq;
+
+ for (i = 0; i < data->init_seq_num; i++, seq++) {
+ writeb(seq->val, priv->base + seq->offset);
+ if (seq->delay)
+ usleep_range(seq->delay, seq->delay + 10);
+ }
+}
+
+static int qcom_snps_hsphy_por_reset(struct hsphy_priv *priv)
+{
+ int ret;
+
+ ret = reset_control_assert(priv->por_reset);
+ if (ret)
+ return ret;
+
+ /*
+ * The Femto PHY is POR reset in the following scenarios.
+ *
+ * 1. After overriding the parameter registers.
+ * 2. Low power mode exit from PHY retention.
+ *
+ * Ensure that SIDDQ is cleared before bringing the PHY
+ * out of reset.
+ */
+ qcom_snps_hsphy_exit_retention(priv);
+
+ /*
+ * As per databook, 10 usec delay is required between
+ * PHY POR assert and de-assert.
+ */
+ usleep_range(10, 20);
+ ret = reset_control_deassert(priv->por_reset);
+ if (ret)
+ return ret;
+
+ /*
+ * As per databook, it takes 75 usec for PHY to stabilize
+ * after the reset.
+ */
+ usleep_range(80, 100);
+
+ return 0;
+}
+
+static int qcom_snps_hsphy_init(struct phy *phy)
+{
+ struct hsphy_priv *priv = phy_get_drvdata(phy);
+ int ret;
+
+ ret = qcom_snps_hsphy_reset(priv);
+ if (ret)
+ return ret;
+
+ qcom_snps_hsphy_init_sequence(priv);
+
+ ret = qcom_snps_hsphy_por_reset(priv);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct phy_ops qcom_snps_hsphy_ops = {
+ .init = qcom_snps_hsphy_init,
+ .power_on = qcom_snps_hsphy_power_on,
+ .power_off = qcom_snps_hsphy_power_off,
+ .set_mode = qcom_snps_hsphy_set_mode,
+ .owner = THIS_MODULE,
+};
+
+static const char * const qcom_snps_hsphy_clks[] = {
+ "ref",
+ "ahb",
+ "sleep",
+};
+
+static int qcom_snps_hsphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *provider;
+ struct hsphy_priv *priv;
+ struct phy *phy;
+ int ret;
+ int i;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->num_clks = ARRAY_SIZE(qcom_snps_hsphy_clks);
+ priv->clks = devm_kcalloc(dev, priv->num_clks, sizeof(*priv->clks),
+ GFP_KERNEL);
+ if (!priv->clks)
+ return -ENOMEM;
+
+ for (i = 0; i < priv->num_clks; i++)
+ priv->clks[i].id = qcom_snps_hsphy_clks[i];
+
+ ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
+ if (ret)
+ return ret;
+
+ priv->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
+ if (IS_ERR(priv->phy_reset))
+ return PTR_ERR(priv->phy_reset);
+
+ priv->por_reset = devm_reset_control_get_exclusive(dev, "por");
+ if (IS_ERR(priv->por_reset))
+ return PTR_ERR(priv->por_reset);
+
+ priv->vregs[VDD].supply = "vdd";
+ priv->vregs[VDDA_1P8].supply = "vdda1p8";
+ priv->vregs[VDDA_3P3].supply = "vdda3p3";
+
+ ret = devm_regulator_bulk_get(dev, VREG_NUM, priv->vregs);
+ if (ret)
+ return ret;
+
+ /* Get device match data */
+ priv->data = device_get_match_data(dev);
+
+ phy = devm_phy_create(dev, dev->of_node, &qcom_snps_hsphy_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ phy_set_drvdata(phy, priv);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(provider))
+ return PTR_ERR(provider);
+
+ ret = regulator_set_load(priv->vregs[VDDA_1P8].consumer, 19000);
+ if (ret < 0)
+ return ret;
+
+ ret = regulator_set_load(priv->vregs[VDDA_3P3].consumer, 16000);
+ if (ret < 0)
+ goto unset_1p8_load;
+
+ return 0;
+
+unset_1p8_load:
+ regulator_set_load(priv->vregs[VDDA_1P8].consumer, 0);
+
+ return ret;
+}
+
+/*
+ * The macro is used to define an initialization sequence. Each tuple
+ * is meant to program 'value' into phy register at 'offset' with 'delay'
+ * in us followed.
+ */
+#define HSPHY_INIT_CFG(o, v, d) { .offset = o, .val = v, .delay = d, }
+
+static const struct hsphy_init_seq init_seq_femtophy[] = {
+ HSPHY_INIT_CFG(0xc0, 0x01, 0),
+ HSPHY_INIT_CFG(0xe8, 0x0d, 0),
+ HSPHY_INIT_CFG(0x74, 0x12, 0),
+ HSPHY_INIT_CFG(0x98, 0x63, 0),
+ HSPHY_INIT_CFG(0x9c, 0x03, 0),
+ HSPHY_INIT_CFG(0xa0, 0x1d, 0),
+ HSPHY_INIT_CFG(0xa4, 0x03, 0),
+ HSPHY_INIT_CFG(0x8c, 0x23, 0),
+ HSPHY_INIT_CFG(0x78, 0x08, 0),
+ HSPHY_INIT_CFG(0x7c, 0xdc, 0),
+ HSPHY_INIT_CFG(0x90, 0xe0, 20),
+ HSPHY_INIT_CFG(0x74, 0x10, 0),
+ HSPHY_INIT_CFG(0x90, 0x60, 0),
+};
+
+static const struct hsphy_data hsphy_data_femtophy = {
+ .init_seq = init_seq_femtophy,
+ .init_seq_num = ARRAY_SIZE(init_seq_femtophy),
+};
+
+static const struct of_device_id qcom_snps_hsphy_match[] = {
+ { .compatible = "qcom,usb-hs-28nm-femtophy", .data = &hsphy_data_femtophy, },
+ { },
+};
+MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_match);
+
+static struct platform_driver qcom_snps_hsphy_driver = {
+ .probe = qcom_snps_hsphy_probe,
+ .driver = {
+ .name = "qcom,usb-hs-28nm-phy",
+ .of_match_table = qcom_snps_hsphy_match,
+ },
+};
+module_platform_driver(qcom_snps_hsphy_driver);
+
+MODULE_DESCRIPTION("Qualcomm 28nm Hi-Speed USB PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 04/18] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (2 preceding siblings ...)
2020-02-07 1:58 ` [PATCH v4 03/18] phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver Bryan O'Donoghue
@ 2020-02-07 1:58 ` Bryan O'Donoghue
2020-02-07 1:58 ` [PATCH v4 05/18] phy: qualcomm: usb: Add SuperSpeed PHY driver Bryan O'Donoghue
` (13 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:58 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Jorge Ramirez-Ortiz, Jorge Ramirez-Ortiz,
Rob Herring, Mark Rutland, devicetree, Bryan O'Donoghue
From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed PHY. This PHY
appears in a number of SoCs on various flavors of 20nm and 28nm nodes.
Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
definitions.
[bod: converted to yaml format]
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../devicetree/bindings/phy/qcom,usb-ss.yaml | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml
new file mode 100644
index 000000000000..377b9e1e39d3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
+
+maintainers:
+ - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+
+description: |
+ Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
+
+properties:
+ compatible:
+ enum:
+ - qcom,usb-ssphy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: rpmcc clock
+ - description: PHY AHB clock
+ - description: SuperSpeed pipe clock
+
+ clock-names:
+ items:
+ - const: ref
+ - const: ahb
+ - const: pipe
+
+ vdd-supply:
+ description: phandle to the regulator VDD supply node.
+
+ vdda1p8-supply:
+ description: phandle to the regulator 1.8V supply node.
+
+ resets:
+ items:
+ - description: COM reset
+ - description: PHY reset line
+
+ reset-names:
+ items:
+ - const: com
+ - const: phy
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - vdd-supply
+ - vdda1p8-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-qcs404.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ usb3_phy: usb3-phy@78000 {
+ compatible = "qcom,usb-ssphy";
+ reg = <0x78000 0x400>;
+ #phy-cells = <0>;
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "ref", "ahb", "pipe";
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "com", "phy";
+ vdd-supply = <&vreg_l3_1p05>;
+ vdda1p8-supply = <&vreg_l5_1p8>;
+ };
+...
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 05/18] phy: qualcomm: usb: Add SuperSpeed PHY driver
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (3 preceding siblings ...)
2020-02-07 1:58 ` [PATCH v4 04/18] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings Bryan O'Donoghue
@ 2020-02-07 1:58 ` Bryan O'Donoghue
2020-02-07 1:58 ` [PATCH v4 06/18] usb: dwc3: Registering a role switch in the DRD code Bryan O'Donoghue
` (12 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:58 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Jorge Ramirez-Ortiz, Jorge Ramirez-Ortiz,
Sriharsha Allenki's, Andy Gross, Kishon Vijay Abraham I,
Philipp Zabel, Bryan O'Donoghue
From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the
20nm and 28nm process nodes.
Based on Sriharsha Allenki's <sallenki@codeaurora.org> original code.
[bod: Removed dependency on extcon.
Switched to gpio-usb-conn to handle VBUS On/Off
Switched to usb-role-switch to bind gpio-usb-conn to DWC3]
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
Cc: Sriharsha Allenki's <sallenki@codeaurora.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
drivers/phy/qualcomm/Kconfig | 9 +
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-usb-ss.c | 246 +++++++++++++++++++++++++
3 files changed, 256 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-ss.c
diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 9c56a7216f72..98674ed094d9 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -102,3 +102,12 @@ config PHY_QCOM_USB_HS_28NM
High-Speed PHY driver. This driver supports the Hi-Speed PHY which
is usually paired with either the ChipIdea or Synopsys DWC3 USB
IPs on MSM SOCs.
+
+config PHY_QCOM_USB_SS
+ tristate "Qualcomm USB Super-Speed PHY driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
+ select GENERIC_PHY
+ help
+ Enable this to support the Super-Speed USB transceiver on various
+ Qualcomm chipsets.
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index a4dab5329de0..1f14aeacbd70 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o
obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
+obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c b/drivers/phy/qualcomm/phy-qcom-usb-ss.c
new file mode 100644
index 000000000000..d7c6eb5e733c
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-usb-ss.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2012-2014,2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2020, Linaro Limited
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#define PHY_CTRL0 0x6C
+#define PHY_CTRL1 0x70
+#define PHY_CTRL2 0x74
+#define PHY_CTRL4 0x7C
+
+/* PHY_CTRL bits */
+#define REF_PHY_EN BIT(0)
+#define LANE0_PWR_ON BIT(2)
+#define SWI_PCS_CLK_SEL BIT(4)
+#define TST_PWR_DOWN BIT(4)
+#define PHY_RESET BIT(7)
+
+#define NUM_BULK_CLKS 3
+#define NUM_BULK_REGS 2
+
+struct ssphy_priv {
+ void __iomem *base;
+ struct device *dev;
+ struct reset_control *reset_com;
+ struct reset_control *reset_phy;
+ struct regulator_bulk_data regs[NUM_BULK_REGS];
+ struct clk_bulk_data clks[NUM_BULK_CLKS];
+ enum phy_mode mode;
+};
+
+static inline void qcom_ssphy_updatel(void __iomem *addr, u32 mask, u32 val)
+{
+ writel((readl(addr) & ~mask) | val, addr);
+}
+
+static int qcom_ssphy_do_reset(struct ssphy_priv *priv)
+{
+ int ret;
+
+ if (!priv->reset_com) {
+ qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET,
+ PHY_RESET);
+ usleep_range(10, 20);
+ qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0);
+ } else {
+ ret = reset_control_assert(priv->reset_com);
+ if (ret) {
+ dev_err(priv->dev, "Failed to assert reset com\n");
+ return ret;
+ }
+
+ ret = reset_control_assert(priv->reset_phy);
+ if (ret) {
+ dev_err(priv->dev, "Failed to assert reset phy\n");
+ return ret;
+ }
+
+ usleep_range(10, 20);
+
+ ret = reset_control_deassert(priv->reset_com);
+ if (ret) {
+ dev_err(priv->dev, "Failed to deassert reset com\n");
+ return ret;
+ }
+
+ ret = reset_control_deassert(priv->reset_phy);
+ if (ret) {
+ dev_err(priv->dev, "Failed to deassert reset phy\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int qcom_ssphy_power_on(struct phy *phy)
+{
+ struct ssphy_priv *priv = phy_get_drvdata(phy);
+ int ret;
+
+ ret = regulator_bulk_enable(NUM_BULK_REGS, priv->regs);
+ if (ret)
+ return ret;
+
+ ret = clk_bulk_prepare_enable(NUM_BULK_CLKS, priv->clks);
+ if (ret)
+ goto err_disable_regulator;
+
+ ret = qcom_ssphy_do_reset(priv);
+ if (ret)
+ goto err_disable_clock;
+
+ writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0);
+ qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON);
+ qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN);
+ qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0);
+
+ return 0;
+err_disable_clock:
+ clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks);
+err_disable_regulator:
+ regulator_bulk_disable(NUM_BULK_REGS, priv->regs);
+
+ return ret;
+}
+
+static int qcom_ssphy_power_off(struct phy *phy)
+{
+ struct ssphy_priv *priv = phy_get_drvdata(phy);
+
+ qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0);
+ qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0);
+ qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN);
+
+ clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks);
+ regulator_bulk_disable(NUM_BULK_REGS, priv->regs);
+
+ return 0;
+}
+
+static int qcom_ssphy_init_clock(struct ssphy_priv *priv)
+{
+ priv->clks[0].id = "ref";
+ priv->clks[1].id = "ahb";
+ priv->clks[2].id = "pipe";
+
+ return devm_clk_bulk_get(priv->dev, NUM_BULK_CLKS, priv->clks);
+}
+
+static int qcom_ssphy_init_regulator(struct ssphy_priv *priv)
+{
+ int ret;
+
+ priv->regs[0].supply = "vdd";
+ priv->regs[1].supply = "vdda1p8";
+ ret = devm_regulator_bulk_get(priv->dev, NUM_BULK_REGS, priv->regs);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(priv->dev, "Failed to get regulators\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+static int qcom_ssphy_init_reset(struct ssphy_priv *priv)
+{
+ priv->reset_com = devm_reset_control_get_optional_exclusive(priv->dev, "com");
+ if (IS_ERR(priv->reset_com)) {
+ dev_err(priv->dev, "Failed to get reset control com\n");
+ return PTR_ERR(priv->reset_com);
+ }
+
+ if (priv->reset_com) {
+ /* if reset_com is present, reset_phy is no longer optional */
+ priv->reset_phy = devm_reset_control_get_exclusive(priv->dev, "phy");
+ if (IS_ERR(priv->reset_phy)) {
+ dev_err(priv->dev, "Failed to get reset control phy\n");
+ return PTR_ERR(priv->reset_phy);
+ }
+ }
+
+ return 0;
+}
+
+static const struct phy_ops qcom_ssphy_ops = {
+ .power_off = qcom_ssphy_power_off,
+ .power_on = qcom_ssphy_power_on,
+ .owner = THIS_MODULE,
+};
+
+static int qcom_ssphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *provider;
+ struct ssphy_priv *priv;
+ struct phy *phy;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(struct ssphy_priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ priv->mode = PHY_MODE_INVALID;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ ret = qcom_ssphy_init_clock(priv);
+ if (ret)
+ return ret;
+
+ ret = qcom_ssphy_init_reset(priv);
+ if (ret)
+ return ret;
+
+ ret = qcom_ssphy_init_regulator(priv);
+ if (ret)
+ return ret;
+
+ phy = devm_phy_create(dev, dev->of_node, &qcom_ssphy_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "Failed to create the SS phy\n");
+ return PTR_ERR(phy);
+ }
+
+ phy_set_drvdata(phy, priv);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static const struct of_device_id qcom_ssphy_match[] = {
+ { .compatible = "qcom,usb-ssphy", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, qcom_ssphy_match);
+
+static struct platform_driver qcom_ssphy_driver = {
+ .probe = qcom_ssphy_probe,
+ .driver = {
+ .name = "qcom-usb-ssphy",
+ .of_match_table = qcom_ssphy_match,
+ },
+};
+module_platform_driver(qcom_ssphy_driver);
+
+MODULE_DESCRIPTION("Qualcomm SuperSpeed USB PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 06/18] usb: dwc3: Registering a role switch in the DRD code.
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (4 preceding siblings ...)
2020-02-07 1:58 ` [PATCH v4 05/18] phy: qualcomm: usb: Add SuperSpeed PHY driver Bryan O'Donoghue
@ 2020-02-07 1:58 ` Bryan O'Donoghue
2020-02-07 1:58 ` [PATCH v4 07/18] dt-bindings: usb: dwc3: Add a gpio-usb-connector example Bryan O'Donoghue
` (11 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:58 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Yu Chen, Rob Herring, Mark Rutland, ShuFan Lee,
Heikki Krogerus, Suzuki K Poulose, Chunfeng Yun, Hans de Goede,
Andy Shevchenko, Jun Li, Valentin Schneider, devicetree,
John Stultz, Bryan O'Donoghue
From: Yu Chen <chenyu56@huawei.com>
The Type-C drivers use USB role switch API to inform the
system about the negotiated data role, so registering a role
switch in the DRD code in order to support platforms with
USB Type-C connectors.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
CC: ShuFan Lee <shufan_lee@richtek.com>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Chunfeng Yun <chunfeng.yun@mediatek.com>
Cc: Yu Chen <chenyu56@huawei.com>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Jun Li <lijun.kernel@gmail.com>
Cc: Valentin Schneider <valentin.schneider@arm.com>
Cc: Jack Pham <jackp@codeaurora.org>
Cc: linux-usb@vger.kernel.org
Cc: devicetree@vger.kernel.org
Suggested-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Yu Chen <chenyu56@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
drivers/usb/dwc3/core.h | 3 ++
drivers/usb/dwc3/drd.c | 75 ++++++++++++++++++++++++++++++++++++++++-
2 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 77c4a9abe365..a99e57636172 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -25,6 +25,7 @@
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg.h>
+#include <linux/usb/role.h>
#include <linux/ulpi/interface.h>
#include <linux/phy/phy.h>
@@ -953,6 +954,7 @@ struct dwc3_scratchpad_array {
* @hsphy_mode: UTMI phy mode, one of following:
* - USBPHY_INTERFACE_MODE_UTMI
* - USBPHY_INTERFACE_MODE_UTMIW
+ * @role_sw: usb_role_switch handle
* @usb2_phy: pointer to USB2 PHY
* @usb3_phy: pointer to USB3 PHY
* @usb2_generic_phy: pointer to USB2 PHY
@@ -1086,6 +1088,7 @@ struct dwc3 {
struct extcon_dev *edev;
struct notifier_block edev_nb;
enum usb_phy_interface hsphy_mode;
+ struct usb_role_switch *role_sw;
u32 fladj;
u32 irq_gadget;
diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
index c946d64142ad..c355166793d0 100644
--- a/drivers/usb/dwc3/drd.c
+++ b/drivers/usb/dwc3/drd.c
@@ -476,6 +476,71 @@ static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
return edev;
}
+#if IS_ENABLED(CONFIG_USB_ROLE_SWITCH)
+static int dwc3_usb_role_switch_set(struct device *dev, enum usb_role role)
+{
+ struct dwc3 *dwc = dev_get_drvdata(dev);
+ u32 mode;
+
+ switch (role) {
+ case USB_ROLE_HOST:
+ mode = DWC3_GCTL_PRTCAP_HOST;
+ break;
+ case USB_ROLE_DEVICE:
+ mode = DWC3_GCTL_PRTCAP_DEVICE;
+ break;
+ default:
+ mode = DWC3_GCTL_PRTCAP_DEVICE;
+ break;
+ }
+
+ dwc3_set_mode(dwc, mode);
+ return 0;
+}
+
+static enum usb_role dwc3_usb_role_switch_get(struct device *dev)
+{
+ struct dwc3 *dwc = dev_get_drvdata(dev);
+ unsigned long flags;
+ enum usb_role role;
+
+ spin_lock_irqsave(&dwc->lock, flags);
+ switch (dwc->current_dr_role) {
+ case DWC3_GCTL_PRTCAP_HOST:
+ role = USB_ROLE_HOST;
+ break;
+ case DWC3_GCTL_PRTCAP_DEVICE:
+ role = USB_ROLE_DEVICE;
+ break;
+ case DWC3_GCTL_PRTCAP_OTG:
+ role = dwc->current_otg_role;
+ break;
+ default:
+ role = USB_ROLE_DEVICE;
+ break;
+ }
+ spin_unlock_irqrestore(&dwc->lock, flags);
+ return role;
+}
+
+static int dwc3_setup_role_switch(struct dwc3 *dwc)
+{
+ struct usb_role_switch_desc dwc3_role_switch = {NULL};
+
+ dwc3_role_switch.fwnode = dev_fwnode(dwc->dev);
+ dwc3_role_switch.set = dwc3_usb_role_switch_set;
+ dwc3_role_switch.get = dwc3_usb_role_switch_get;
+ dwc->role_sw = usb_role_switch_register(dwc->dev, &dwc3_role_switch);
+ if (IS_ERR(dwc->role_sw))
+ return PTR_ERR(dwc->role_sw);
+
+ dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
+ return 0;
+}
+#else
+#define dwc3_setup_role_switch(x) 0
+#endif
+
int dwc3_drd_init(struct dwc3 *dwc)
{
int ret, irq;
@@ -484,7 +549,12 @@ int dwc3_drd_init(struct dwc3 *dwc)
if (IS_ERR(dwc->edev))
return PTR_ERR(dwc->edev);
- if (dwc->edev) {
+ if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
+ device_property_read_bool(dwc->dev, "usb-role-switch")) {
+ ret = dwc3_setup_role_switch(dwc);
+ if (ret < 0)
+ return ret;
+ } else if (dwc->edev) {
dwc->edev_nb.notifier_call = dwc3_drd_notifier;
ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST,
&dwc->edev_nb);
@@ -531,6 +601,9 @@ void dwc3_drd_exit(struct dwc3 *dwc)
{
unsigned long flags;
+ if (dwc->role_sw)
+ usb_role_switch_unregister(dwc->role_sw);
+
if (dwc->edev)
extcon_unregister_notifier(dwc->edev, EXTCON_USB_HOST,
&dwc->edev_nb);
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 07/18] dt-bindings: usb: dwc3: Add a gpio-usb-connector example
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (5 preceding siblings ...)
2020-02-07 1:58 ` [PATCH v4 06/18] usb: dwc3: Registering a role switch in the DRD code Bryan O'Donoghue
@ 2020-02-07 1:58 ` Bryan O'Donoghue
2020-02-07 1:58 ` [PATCH v4 08/18] dt-bindings: usb: dwc3: Add a usb-role-switch to the example Bryan O'Donoghue
` (10 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:58 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Bryan O'Donoghue, Rob Herring, Mark Rutland,
devicetree
A USB connector should be a child node of the USB controller
connector/usb-connector.txt. This patch adds an example of how to do this
to the dwc3 binding descriptions.
It is necessary to declare a connector as a child-node of a USB controller
for role-switching to work, so this example should be helpful to others
implementing that.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-usb@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Felipe Balbi <balbi@kernel.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
Documentation/devicetree/bindings/usb/dwc3.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 66780a47ad85..4e1e4afccee6 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -121,4 +121,12 @@ dwc3@4a030000 {
interrupts = <0 92 4>
usb-phy = <&usb2_phy>, <&usb3,phy>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+
+ usb_con: connector {
+ compatible = "gpio-usb-b-connector";
+ id-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
+ vbus-supply = <&usb3_vbus_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_id_pin>, <&usb3_vbus_pin>;
+ };
};
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 08/18] dt-bindings: usb: dwc3: Add a usb-role-switch to the example
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (6 preceding siblings ...)
2020-02-07 1:58 ` [PATCH v4 07/18] dt-bindings: usb: dwc3: Add a gpio-usb-connector example Bryan O'Donoghue
@ 2020-02-07 1:58 ` Bryan O'Donoghue
2020-02-07 1:58 ` [PATCH v4 09/18] usb: dwc3: qcom: Override VBUS when using gpio_usb_connector Bryan O'Donoghue
` (9 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:58 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Bryan O'Donoghue
This patch adds usb-role-switch to the example dwc3 given in the file.
Documentation/devicetree/bindings/usb/generic.txt makes this a valid
declaration for dwc3 this patch gives an example of how to use it.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
Documentation/devicetree/bindings/usb/dwc3.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 4e1e4afccee6..8c6c7b355356 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -121,6 +121,7 @@ dwc3@4a030000 {
interrupts = <0 92 4>
usb-phy = <&usb2_phy>, <&usb3,phy>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ usb-role-switch;
usb_con: connector {
compatible = "gpio-usb-b-connector";
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 09/18] usb: dwc3: qcom: Override VBUS when using gpio_usb_connector
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (7 preceding siblings ...)
2020-02-07 1:58 ` [PATCH v4 08/18] dt-bindings: usb: dwc3: Add a usb-role-switch to the example Bryan O'Donoghue
@ 2020-02-07 1:58 ` Bryan O'Donoghue
2020-02-07 8:07 ` Jack Pham
2020-02-07 1:58 ` [PATCH v4 10/18] usb: dwc3: Add support for usb-conn-gpio connectors Bryan O'Donoghue
` (8 subsequent siblings)
17 siblings, 1 reply; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:58 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Lee Jones, Philipp Zabel
Using the gpio_usb_connector driver also means that we are not supplying
VBUS via the SoC but by an external PMIC directly.
This patch searches for a gpio_usb_connector as a child node of the core
DWC3 block and if found switches on the VBUS over-ride, leaving it up to
the role-switching code in gpio-usb-connector to switch off and on VBUS.
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Felipe Balbi <balbi@kernel.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
drivers/usb/dwc3/dwc3-qcom.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 261af9e38ddd..b2d20b474029 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -550,6 +550,21 @@ static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
.ss_phy_irq_index = 2
};
+static bool dwc3_qcom_find_gpio_usb_connector(struct platform_device *pdev)
+{
+ struct device_node *np;
+ bool retval = false;
+
+ np = of_get_child_by_name(pdev->dev.of_node, "connector");
+ if (np) {
+ if (of_device_is_compatible(np, "gpio-usb-b-connector"))
+ retval = true;
+ }
+ of_node_put(np);
+
+ return retval;
+}
+
static int dwc3_qcom_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -557,7 +572,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
struct dwc3_qcom *qcom;
struct resource *res, *parent_res = NULL;
int ret, i;
- bool ignore_pipe_clk;
+ bool ignore_pipe_clk, gpio_usb_conn;
qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
if (!qcom)
@@ -649,9 +664,10 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
}
qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
+ gpio_usb_conn = dwc3_qcom_find_gpio_usb_connector(qcom->dwc3);
- /* enable vbus override for device mode */
- if (qcom->mode == USB_DR_MODE_PERIPHERAL)
+ /* enable vbus override for device mode or GPIO USB connector mode */
+ if (qcom->mode == USB_DR_MODE_PERIPHERAL || gpio_usb_conn)
dwc3_qcom_vbus_overrride_enable(qcom, true);
/* register extcon to override sw_vbus on Vbus change later */
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v4 09/18] usb: dwc3: qcom: Override VBUS when using gpio_usb_connector
2020-02-07 1:58 ` [PATCH v4 09/18] usb: dwc3: qcom: Override VBUS when using gpio_usb_connector Bryan O'Donoghue
@ 2020-02-07 8:07 ` Jack Pham
2020-02-07 10:36 ` Bryan O'Donoghue
0 siblings, 1 reply; 23+ messages in thread
From: Jack Pham @ 2020-02-07 8:07 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: linux-arm-msm, linux-usb, gregkh, balbi, bjorn.andersson,
linux-kernel, Andy Gross, Lee Jones, Philipp Zabel, Manu Gautam
Hi Bryan,
On Fri, Feb 07, 2020 at 01:58:58AM +0000, Bryan O'Donoghue wrote:
> Using the gpio_usb_connector driver also means that we are not supplying
> VBUS via the SoC but by an external PMIC directly.
>
> This patch searches for a gpio_usb_connector as a child node of the core
> DWC3 block and if found switches on the VBUS over-ride, leaving it up to
> the role-switching code in gpio-usb-connector to switch off and on VBUS.
<snip>
> static int dwc3_qcom_probe(struct platform_device *pdev)
> {
> struct device_node *np = pdev->dev.of_node;
> @@ -557,7 +572,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> struct dwc3_qcom *qcom;
> struct resource *res, *parent_res = NULL;
> int ret, i;
> - bool ignore_pipe_clk;
> + bool ignore_pipe_clk, gpio_usb_conn;
>
> qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
> if (!qcom)
> @@ -649,9 +664,10 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> }
>
> qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
> + gpio_usb_conn = dwc3_qcom_find_gpio_usb_connector(qcom->dwc3);
>
> - /* enable vbus override for device mode */
> - if (qcom->mode == USB_DR_MODE_PERIPHERAL)
> + /* enable vbus override for device mode or GPIO USB connector mode */
> + if (qcom->mode == USB_DR_MODE_PERIPHERAL || gpio_usb_conn)
> dwc3_qcom_vbus_overrride_enable(qcom, true);
This doesn't seem right. It looks like you are doing the vbus_override
only once on probe() and keeping it that way regardless of the dynamic
state of the connector, i.e. even after VBUS is physically removed
and/or ID pin is low.
> /* register extcon to override sw_vbus on Vbus change later */
As suggested by this comment, if you look at the extcon handling, it
intercepts the VBUS state toggling in dwc3_qcom_vbus_notifier() and
calls vbus_override() accordingly. That way it should only be true when
the role==USB_ROLE_DEVICE and disabled otherwise (USB_ROLE_HOST/NONE).
To me the gpio-b connector + usb-role-switch is attempting to be an
alternative to extcon. But to correctly mimic the vbus_override()
behavior I think we need a way to intercept when the connector child
driver calls usb_role_switch_set_role() to the dwc3 device, but somehow
be able to do it from up here in the parent/glue layer. Unfortunately I
don't have a good idea of how to do that, short of shoehorning an
"upcall" notification from drd.c to the glue, something I don't think
Felipe would be a fan of.
Could the usb_role_switch class somehow be enhanced to support chaining
multiple "consumers" to support this case? Such that when the gpio-b
driver calls set_role() it could get handled both by drd.c and
dwc3-qcom.c?
Jack
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v4 09/18] usb: dwc3: qcom: Override VBUS when using gpio_usb_connector
2020-02-07 8:07 ` Jack Pham
@ 2020-02-07 10:36 ` Bryan O'Donoghue
2020-02-07 10:50 ` Bryan O'Donoghue
0 siblings, 1 reply; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 10:36 UTC (permalink / raw)
To: Jack Pham
Cc: linux-arm-msm, linux-usb, gregkh, balbi, bjorn.andersson,
linux-kernel, Andy Gross, Lee Jones, Philipp Zabel, Manu Gautam
On 07/02/2020 08:07, Jack Pham wrote:
> Hi Bryan,
>
> On Fri, Feb 07, 2020 at 01:58:58AM +0000, Bryan O'Donoghue wrote:
>> Using the gpio_usb_connector driver also means that we are not supplying
>> VBUS via the SoC but by an external PMIC directly.
>>
>> This patch searches for a gpio_usb_connector as a child node of the core
>> DWC3 block and if found switches on the VBUS over-ride, leaving it up to
>> the role-switching code in gpio-usb-connector to switch off and on VBUS.
>
> <snip>
>
>> static int dwc3_qcom_probe(struct platform_device *pdev)
>> {
>> struct device_node *np = pdev->dev.of_node;
>> @@ -557,7 +572,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
>> struct dwc3_qcom *qcom;
>> struct resource *res, *parent_res = NULL;
>> int ret, i;
>> - bool ignore_pipe_clk;
>> + bool ignore_pipe_clk, gpio_usb_conn;
>>
>> qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
>> if (!qcom)
>> @@ -649,9 +664,10 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
>> }
>>
>> qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
>> + gpio_usb_conn = dwc3_qcom_find_gpio_usb_connector(qcom->dwc3);
>>
>> - /* enable vbus override for device mode */
>> - if (qcom->mode == USB_DR_MODE_PERIPHERAL)
>> + /* enable vbus override for device mode or GPIO USB connector mode */
>> + if (qcom->mode == USB_DR_MODE_PERIPHERAL || gpio_usb_conn)
>> dwc3_qcom_vbus_overrride_enable(qcom, true);
>
> This doesn't seem right. It looks like you are doing the vbus_override
> only once on probe() and keeping it that way regardless of the dynamic
> state of the connector, i.e. even after VBUS is physically removed
> and/or ID pin is low.
>
Hmm, I don't see anything much in the documentation that flags why we
want or need to toggle this.
>> /* register extcon to override sw_vbus on Vbus change later */
>
> As suggested by this comment, if you look at the extcon handling, it
> intercepts the VBUS state toggling in dwc3_qcom_vbus_notifier() and
> calls vbus_override() accordingly. That way it should only be true when
> the role==USB_ROLE_DEVICE and disabled otherwise (USB_ROLE_HOST/NONE).
>
> To me the gpio-b connector + usb-role-switch is attempting to be an
> alternative to extcon. But to correctly mimic the vbus_override()
> behavior I think we need a way to intercept when the connector child
> driver calls usb_role_switch_set_role() to the dwc3 device, but somehow
> be able to do it from up here in the parent/glue layer. Unfortunately I
> don't have a good idea of how to do that, short of shoehorning an
> "upcall" notification from drd.c to the glue, something I don't think
> Felipe would be a fan of.
>
> Could the usb_role_switch class somehow be enhanced to support chaining
> multiple "consumers" to support this case? Such that when the gpio-b
> driver calls set_role() it could get handled both by drd.c and
> dwc3-qcom.c?
It is probably necessary eventually, but, per my reading of the
documents and working with the hardware, I couldn't justify the
additional work.
However if you think this patchset needs the toggle, I can look into
getting the indicator to toggle here too.
We'd need to add some sort of linked list of notifiers to the role
switching logic and toggle them in order.
Similar to what is done in extcon now for the various notifer hooks.
---
bod
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v4 09/18] usb: dwc3: qcom: Override VBUS when using gpio_usb_connector
2020-02-07 10:36 ` Bryan O'Donoghue
@ 2020-02-07 10:50 ` Bryan O'Donoghue
2020-02-07 15:04 ` Bryan O'Donoghue
0 siblings, 1 reply; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 10:50 UTC (permalink / raw)
To: Jack Pham
Cc: linux-arm-msm, linux-usb, gregkh, balbi, bjorn.andersson,
linux-kernel, Andy Gross, Lee Jones, Philipp Zabel, Manu Gautam
On 07/02/2020 10:36, Bryan O'Donoghue wrote:
> On 07/02/2020 08:07, Jack Pham wrote:
>> Could the usb_role_switch class somehow be enhanced to support chaining
>> multiple "consumers" to support this case? Such that when the gpio-b
>> driver calls set_role() it could get handled both by drd.c and
>> dwc3-qcom.c?
>
> It is probably necessary eventually, but, per my reading of the
> documents and working with the hardware, I couldn't justify the
> additional work.
>
> However if you think this patchset needs the toggle, I can look into
> getting the indicator to toggle here too.
>
> We'd need to add some sort of linked list of notifiers to the role
> switching logic and toggle them in order.
>
> Similar to what is done in extcon now for the various notifer hooks.
Maybe I'm wrong...
Looking a bit closer at the role-switch code it might be possible to
register multiple devices _as-is_ so long as you have a pointer to the
relevant parent...
---
bod
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v4 09/18] usb: dwc3: qcom: Override VBUS when using gpio_usb_connector
2020-02-07 10:50 ` Bryan O'Donoghue
@ 2020-02-07 15:04 ` Bryan O'Donoghue
0 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 15:04 UTC (permalink / raw)
To: Jack Pham
Cc: linux-arm-msm, linux-usb, gregkh, balbi, bjorn.andersson,
linux-kernel, Andy Gross, Lee Jones, Philipp Zabel, Manu Gautam
On 07/02/2020 10:50, Bryan O'Donoghue wrote:
>
> Maybe I'm wrong...
>
> Looking a bit closer at the role-switch code it might be possible to
> register multiple devices _as-is_ so long as you have a pointer to the
> relevant parent...
Soo... its possible to create a new role-switch device relatively easily
@usb_role_switch_register() but, the drivers calling the role-switch
callback have a 1:1 mapping between role-switch call and receiver.
Doing something inside DWC3 <=> DWC3::QCOM looks like less of a rewrite.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v4 10/18] usb: dwc3: Add support for usb-conn-gpio connectors
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (8 preceding siblings ...)
2020-02-07 1:58 ` [PATCH v4 09/18] usb: dwc3: qcom: Override VBUS when using gpio_usb_connector Bryan O'Donoghue
@ 2020-02-07 1:58 ` Bryan O'Donoghue
2020-02-07 1:59 ` [PATCH v4 11/18] arm64: dts: qcom: qcs404: Add USB devices and PHYs Bryan O'Donoghue
` (7 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:58 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Bryan O'Donoghue, John Stultz, Lee Jones,
Rob Herring, Mark Rutland, ShuFan Lee, Heikki Krogerus,
Suzuki K Poulose, Chunfeng Yun, Yu Chen, Hans de Goede,
Andy Shevchenko, Jun Li, Valentin Schneider, devicetree
This patch adds the ability to probe and enumerate a connector based on
usb-conn-gpio. A device node label gpio_usb_connector is used to identify
a usb-conn-gpio as a child of the USB interface.
You would use usb-conn-gpio when a regulator in your system provides VBUS
directly to the connector instead of supplying via the USB PHY.
The parent device must have the "usb-role-switch" property, so that when
the usb-conn-gpio driver calls usb_role_switch_set_role() the notification
in dwc3 will run and the block registers will be updated to match the state
detected at the connector.
Cc: John Stultz <john.stultz@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
CC: ShuFan Lee <shufan_lee@richtek.com>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Chunfeng Yun <chunfeng.yun@mediatek.com>
Cc: Yu Chen <chenyu56@huawei.com>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Jun Li <lijun.kernel@gmail.com>
Cc: Valentin Schneider <valentin.schneider@arm.com>
Cc: Jack Pham <jackp@codeaurora.org>
Cc: linux-usb@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
drivers/usb/dwc3/drd.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
index c355166793d0..c1825fd655f6 100644
--- a/drivers/usb/dwc3/drd.c
+++ b/drivers/usb/dwc3/drd.c
@@ -11,6 +11,7 @@
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/property.h>
+#include <linux/of_platform.h>
#include "debug.h"
#include "core.h"
@@ -537,8 +538,29 @@ static int dwc3_setup_role_switch(struct dwc3 *dwc)
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
return 0;
}
+
+static int dwc3_register_gpio_usb_connector(struct dwc3 *dwc)
+{
+ struct device *dev = dwc->dev;
+ struct device_node *np = dev->of_node, *conn_np;
+ int ret = 0;
+
+ conn_np = of_get_child_by_name(np, "connector");
+ if (!conn_np) {
+ dev_dbg(dev, "no connector child node specified\n");
+ goto done;
+ }
+
+ if (of_device_is_compatible(conn_np, "gpio-usb-b-connector"))
+ ret = of_platform_populate(np, NULL, NULL, dev);
+done:
+ of_node_put(conn_np);
+ return ret;
+}
+
#else
#define dwc3_setup_role_switch(x) 0
+#define dwc3_register_gpio_usb_connector(x) 0
#endif
int dwc3_drd_init(struct dwc3 *dwc)
@@ -554,6 +576,9 @@ int dwc3_drd_init(struct dwc3 *dwc)
ret = dwc3_setup_role_switch(dwc);
if (ret < 0)
return ret;
+ ret = dwc3_register_gpio_usb_connector(dwc);
+ if (ret < 0)
+ return ret;
} else if (dwc->edev) {
dwc->edev_nb.notifier_call = dwc3_drd_notifier;
ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST,
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 11/18] arm64: dts: qcom: qcs404: Add USB devices and PHYs
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (9 preceding siblings ...)
2020-02-07 1:58 ` [PATCH v4 10/18] usb: dwc3: Add support for usb-conn-gpio connectors Bryan O'Donoghue
@ 2020-02-07 1:59 ` Bryan O'Donoghue
2020-02-07 1:59 ` [PATCH v4 12/18] arm64: dts: qcom: qcs404-evb: Define VBUS detect pin Bryan O'Donoghue
` (6 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:59 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Vinod Koul, Shawn Guo, Andy Gross, Rob Herring,
Mark Rutland, devicetree, Bryan O'Donoghue
From: Bjorn Andersson <bjorn.andersson@linaro.org>
QCS404 sports HS and SS USB controllers based on dwc3 block with two HS
PHYs and one SS PHY. Add nodes for these devices and enable them for
EVB board.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 100 +++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index f5f0c4c9cb16..cdd153de35c4 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -272,6 +272,48 @@ rpm_msg_ram: memory@60000 {
reg = <0x00060000 0x6000>;
};
+ usb3_phy: phy@78000 {
+ compatible = "qcom,usb-ssphy";
+ reg = <0x00078000 0x400>;
+ #phy-cells = <0>;
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "ref", "ahb", "pipe";
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "com", "phy";
+ status = "disabled";
+ };
+
+ usb2_phy_prim: phy@7a000 {
+ compatible = "qcom,usb-hs-28nm-femtophy";
+ reg = <0x0007a000 0x200>;
+ #phy-cells = <0>;
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "ahb", "sleep";
+ resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
+ <&gcc GCC_USB2A_PHY_BCR>;
+ reset-names = "phy", "por";
+ status = "disabled";
+ };
+
+ usb2_phy_sec: phy@7c000 {
+ compatible = "qcom,usb-hs-28nm-femtophy";
+ reg = <0x0007c000 0x200>;
+ #phy-cells = <0>;
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "ahb", "sleep";
+ resets = <&gcc GCC_QUSB2_PHY_BCR>,
+ <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
+ reset-names = "phy", "por";
+ status = "disabled";
+ };
+
qfprom: qfprom@a4000 {
compatible = "qcom,qfprom";
reg = <0x000a4000 0x1000>;
@@ -379,6 +421,64 @@ glink-edge {
};
};
+ usb3: usb@7678800 {
+ compatible = "qcom,dwc3";
+ reg = <0x07678800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&gcc GCC_USB30_MASTER_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_CLK>,
+ <&gcc GCC_USB30_SLEEP_CLK>,
+ <&gcc GCC_USB30_MOCK_UTMI_CLK>;
+ clock-names = "core", "iface", "sleep", "mock_utmi";
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+ status = "disabled";
+
+ dwc3@7580000 {
+ compatible = "snps,dwc3";
+ reg = <0x07580000 0xcd00>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy_sec>, <&usb3_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3_lpm_capable;
+ dr_mode = "otg";
+ };
+ };
+
+ usb2: usb@79b8800 {
+ compatible = "qcom,dwc3";
+ reg = <0x079b8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
+ <&gcc GCC_PCNOC_USB2_CLK>,
+ <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
+ <&gcc GCC_USB20_MOCK_UTMI_CLK>;
+ clock-names = "core", "iface", "sleep", "mock_utmi";
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB_HS_SYSTEM_CLK>;
+ assigned-clock-rates = <19200000>, <133333333>;
+ status = "disabled";
+
+ dwc3@78c0000 {
+ compatible = "snps,dwc3";
+ reg = <0x078c0000 0xcc00>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy_prim>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3_lpm_capable;
+ dr_mode = "peripheral";
+ };
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,qcs404-pinctrl";
reg = <0x01000000 0x200000>,
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 12/18] arm64: dts: qcom: qcs404-evb: Define VBUS detect pin
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (10 preceding siblings ...)
2020-02-07 1:59 ` [PATCH v4 11/18] arm64: dts: qcom: qcs404: Add USB devices and PHYs Bryan O'Donoghue
@ 2020-02-07 1:59 ` Bryan O'Donoghue
2020-02-07 1:59 ` [PATCH v4 13/18] arm64: dts: qcom: qcs404-evb: Define VBUS boost pin Bryan O'Donoghue
` (5 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:59 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Rob Herring,
Mark Rutland, devicetree
VBUS present/absent is presented to the SoC via a GPIO on the EVB. Define
the pin mapping for later use by gpio-usb-conn.
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 501a7330dbc8..6d53dc342f97 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -4,6 +4,8 @@
#include <dt-bindings/gpio/gpio.h>
#include "qcs404.dtsi"
#include "pms405.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
aliases {
@@ -270,6 +272,18 @@ rclk {
};
};
+&pms405_gpios {
+ usb3_vbus_pin: usb3-vbus-pin {
+ pinconf {
+ pins = "gpio12";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ input-enable;
+ bias-pull-down;
+ power-source = <1>;
+ };
+ };
+};
+
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 13/18] arm64: dts: qcom: qcs404-evb: Define VBUS boost pin
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (11 preceding siblings ...)
2020-02-07 1:59 ` [PATCH v4 12/18] arm64: dts: qcom: qcs404-evb: Define VBUS detect pin Bryan O'Donoghue
@ 2020-02-07 1:59 ` Bryan O'Donoghue
2020-02-07 1:59 ` [PATCH v4 14/18] arm64: dts: qcom: qcs404-evb: Define USB ID pin Bryan O'Donoghue
` (4 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:59 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Rob Herring,
Mark Rutland, devicetree
An external regulator is used to trigger VBUS on/off via GPIO. This patch
defines the relevant GPIO in the EVB dts.
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 6d53dc342f97..b6147b5ab5cb 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -273,6 +273,14 @@ rclk {
};
&pms405_gpios {
+ usb_vbus_boost_pin: usb-vbus-boost-pin {
+ pinconf {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ output-low;
+ power-source = <1>;
+ };
+ };
usb3_vbus_pin: usb3-vbus-pin {
pinconf {
pins = "gpio12";
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 14/18] arm64: dts: qcom: qcs404-evb: Define USB ID pin
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (12 preceding siblings ...)
2020-02-07 1:59 ` [PATCH v4 13/18] arm64: dts: qcom: qcs404-evb: Define VBUS boost pin Bryan O'Donoghue
@ 2020-02-07 1:59 ` Bryan O'Donoghue
2020-02-07 1:59 ` [PATCH v4 15/18] arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator Bryan O'Donoghue
` (3 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:59 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Rob Herring,
Mark Rutland, devicetree
The USB ID pin is used to tell if a system is a Host or a Device. For our
purposes we will bind this pin into gpio-usb-conn later.
For now define the pin with its pinmux.
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index b6147b5ab5cb..abfb2a9a37e9 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -270,6 +270,20 @@ rclk {
bias-pull-down;
};
};
+
+ usb3_id_pin: usb3-id-pin {
+ pinmux {
+ pins = "gpio116";
+ function = "gpio";
+ };
+
+ pinconf {
+ pins = "gpio116";
+ drive-strength = <2>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
};
&pms405_gpios {
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 15/18] arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (13 preceding siblings ...)
2020-02-07 1:59 ` [PATCH v4 14/18] arm64: dts: qcom: qcs404-evb: Define USB ID pin Bryan O'Donoghue
@ 2020-02-07 1:59 ` Bryan O'Donoghue
2020-02-07 1:59 ` [PATCH v4 16/18] arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage Bryan O'Donoghue
` (2 subsequent siblings)
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:59 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Rob Herring,
Mark Rutland, devicetree
VBUS is supplied by an external regulator controlled by a GPIO pin. This
patch models the regulator as regulator-usb3-vbus.
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index abfb2a9a37e9..01ef59e8e5b7 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -33,6 +33,18 @@ vdd_esmps3_3p3: vdd-esmps3-3p3-regulator {
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
+
+ usb3_vbus_reg: regulator-usb3-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "VBUS_BOOST_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_vbus_boost_pin>;
+ vin-supply = <&vph_pwr>;
+ enable-active-high;
+ };
};
&blsp1_uart3 {
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 16/18] arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (14 preceding siblings ...)
2020-02-07 1:59 ` [PATCH v4 15/18] arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator Bryan O'Donoghue
@ 2020-02-07 1:59 ` Bryan O'Donoghue
2020-02-07 1:59 ` [PATCH v4 17/18] arm64: dts: qcom: qcs404-evb: Enable secondary USB controller Bryan O'Donoghue
2020-02-07 1:59 ` [PATCH v4 18/18] arm64: dts: qcom: qcs404-evb: Enable primary " Bryan O'Donoghue
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:59 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Rob Herring,
Mark Rutland, devicetree
Rather than set the minimum microvolt for this regulator in the USB SS PHY
driver, set it in the DTS.
Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 01ef59e8e5b7..0fff50f755ef 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -199,7 +199,7 @@ vreg_l11_sdc2: l11 {
};
vreg_l12_3p3: l12 {
- regulator-min-microvolt = <2968000>;
+ regulator-min-microvolt = <3050000>;
regulator-max-microvolt = <3300000>;
};
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 17/18] arm64: dts: qcom: qcs404-evb: Enable secondary USB controller
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (15 preceding siblings ...)
2020-02-07 1:59 ` [PATCH v4 16/18] arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage Bryan O'Donoghue
@ 2020-02-07 1:59 ` Bryan O'Donoghue
2020-02-07 1:59 ` [PATCH v4 18/18] arm64: dts: qcom: qcs404-evb: Enable primary " Bryan O'Donoghue
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:59 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Rob Herring,
Mark Rutland, devicetree
This patch enables the second DWC3 controller which has one USB Hi-Speed
PHY attached to it.
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 0fff50f755ef..07d6d793a922 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -318,6 +318,17 @@ pinconf {
};
};
+&usb2 {
+ status = "okay";
+};
+
+&usb2_phy_sec {
+ vdd-supply = <&vreg_l4_1p2>;
+ vdda1p8-supply = <&vreg_l5_1p8>;
+ vdda3p3-supply = <&vreg_l12_3p3>;
+ status = "okay";
+};
+
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v4 18/18] arm64: dts: qcom: qcs404-evb: Enable primary USB controller
2020-02-07 1:58 [PATCH v4 00/18] Enable Qualcomm QCS 404 HS/SS USB Bryan O'Donoghue
` (16 preceding siblings ...)
2020-02-07 1:59 ` [PATCH v4 17/18] arm64: dts: qcom: qcs404-evb: Enable secondary USB controller Bryan O'Donoghue
@ 2020-02-07 1:59 ` Bryan O'Donoghue
17 siblings, 0 replies; 23+ messages in thread
From: Bryan O'Donoghue @ 2020-02-07 1:59 UTC (permalink / raw)
To: linux-arm-msm, linux-usb, gregkh, jackp, balbi, bjorn.andersson
Cc: linux-kernel, Bryan O'Donoghue, Andy Gross, Rob Herring,
Mark Rutland, devicetree
This patch enables the primary USB controller which has
- One USB3 SS PHY using gpio-usb-conn
- One USB2 HS PHY in device mode only and no connector driver
associated.
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 29 ++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 07d6d793a922..4045d3000da6 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -329,6 +329,35 @@ &usb2_phy_sec {
status = "okay";
};
+&usb3 {
+ status = "okay";
+ dwc3@7580000 {
+ usb-role-switch;
+ usb_con: connector {
+ compatible = "gpio-usb-b-connector";
+ label = "USB-C";
+ id-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
+ vbus-supply = <&usb3_vbus_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_id_pin>, <&usb3_vbus_pin>;
+ status = "okay";
+ };
+ };
+};
+
+&usb2_phy_prim {
+ vdd-supply = <&vreg_l4_1p2>;
+ vdda1p8-supply = <&vreg_l5_1p8>;
+ vdda3p3-supply = <&vreg_l12_3p3>;
+ status = "okay";
+};
+
+&usb3_phy {
+ vdd-supply = <&vreg_l3_1p05>;
+ vdda1p8-supply = <&vreg_l5_1p8>;
+ status = "okay";
+};
+
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
--
2.25.0
^ permalink raw reply related [flat|nested] 23+ messages in thread