* [PATCH v3 1/5] clk: qcom: clk-alpha-pll: Use common names for defines
2020-02-16 10:27 [PATCH v3 0/5] Add clock drivers for SM8250 SoC Vinod Koul
@ 2020-02-16 10:27 ` Vinod Koul
2020-02-16 10:27 ` [PATCH v3 2/5] clk: qcom: clk-alpha-pll: Refactor trion PLL Vinod Koul
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Vinod Koul @ 2020-02-16 10:27 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-arm-msm, Bjorn Andersson, Taniya Das, Rob Herring,
Mark Rutland, devicetree, Andy Gross, Michael Turquette,
linux-clk, linux-kernel, psodagud, tsoni, jshriram, vnkgutta,
Vinod Koul
From: Taniya Das <tdas@codeaurora.org>
The PLL run and standby modes are similar across the PLLs, thus rename
them to common names and update the use of these.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/clk/qcom/clk-alpha-pll.c | 40 ++++++++++++++------------------
1 file changed, 17 insertions(+), 23 deletions(-)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 6d946770a80f..0bdf6e45fac9 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -134,15 +134,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
#define PLL_HUAYRA_N_MASK 0xff
#define PLL_HUAYRA_ALPHA_WIDTH 16
-#define FABIA_OPMODE_STANDBY 0x0
-#define FABIA_OPMODE_RUN 0x1
-
-#define FABIA_PLL_OUT_MASK 0x7
-#define FABIA_PLL_RATE_MARGIN 500
-
-#define TRION_PLL_STANDBY 0x0
-#define TRION_PLL_RUN 0x1
-#define TRION_PLL_OUT_MASK 0x7
+#define PLL_STANDBY 0x0
+#define PLL_RUN 0x1
+#define PLL_OUT_MASK 0x7
+#define PLL_RATE_MARGIN 500
#define pll_alpha_width(p) \
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
@@ -766,7 +761,7 @@ static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
if (ret)
return 0;
- return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
+ return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL));
}
static int clk_trion_pll_is_enabled(struct clk_hw *hw)
@@ -796,7 +791,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
}
/* Set operation mode to RUN */
- regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
+ regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
ret = wait_for_pll_enable_lock(pll);
if (ret)
@@ -804,7 +799,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
/* Enable the PLL outputs */
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
- TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
+ PLL_OUT_MASK, PLL_OUT_MASK);
if (ret)
return ret;
@@ -837,12 +832,12 @@ static void clk_trion_pll_disable(struct clk_hw *hw)
/* Disable the PLL outputs */
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
- TRION_PLL_OUT_MASK, 0);
+ PLL_OUT_MASK, 0);
if (ret)
return;
/* Place the PLL mode in STANDBY */
- regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
+ regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
@@ -1089,14 +1084,14 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
return ret;
/* Skip If PLL is already running */
- if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
+ if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
return 0;
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
if (ret)
return ret;
- ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
+ ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
if (ret)
return ret;
@@ -1105,7 +1100,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
if (ret)
return ret;
- ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
+ ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
if (ret)
return ret;
@@ -1114,7 +1109,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
return ret;
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
- FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
+ PLL_OUT_MASK, PLL_OUT_MASK);
if (ret)
return ret;
@@ -1144,13 +1139,12 @@ static void alpha_pll_fabia_disable(struct clk_hw *hw)
return;
/* Disable main outputs */
- ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
- 0);
+ ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
if (ret)
return;
/* Place the PLL in STANDBY */
- regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
+ regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
}
static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
@@ -1171,7 +1165,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l, alpha_width = pll_alpha_width(pll);
u64 a;
- unsigned long rrate, max = rate + FABIA_PLL_RATE_MARGIN;
+ unsigned long rrate, max = rate + PLL_RATE_MARGIN;
rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
@@ -1230,7 +1224,7 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw)
* Due to a limited number of bits for fractional rate programming, the
* rounded up rate could be marginally higher than the requested rate.
*/
- if (rrate > (cal_freq + FABIA_PLL_RATE_MARGIN) || rrate < cal_freq)
+ if (rrate > (cal_freq + PLL_RATE_MARGIN) || rrate < cal_freq)
return -EINVAL;
/* Setup PLL for calibration frequency */
--
2.24.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 2/5] clk: qcom: clk-alpha-pll: Refactor trion PLL
2020-02-16 10:27 [PATCH v3 0/5] Add clock drivers for SM8250 SoC Vinod Koul
2020-02-16 10:27 ` [PATCH v3 1/5] clk: qcom: clk-alpha-pll: Use common names for defines Vinod Koul
@ 2020-02-16 10:27 ` Vinod Koul
2020-02-16 10:27 ` [PATCH v3 3/5] clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs Vinod Koul
2020-02-16 10:27 ` [PATCH v3 4/5] dt-bindings: clock: Add SM8250 GCC clock bindings Vinod Koul
3 siblings, 0 replies; 7+ messages in thread
From: Vinod Koul @ 2020-02-16 10:27 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-arm-msm, Bjorn Andersson, Taniya Das, Rob Herring,
Mark Rutland, devicetree, Andy Gross, Michael Turquette,
linux-clk, linux-kernel, psodagud, tsoni, jshriram, vnkgutta,
Vinod Koul
From: Taniya Das <tdas@codeaurora.org>
Remove duplicate function for calculating the round rate of PLL and also
update the trion pll ops to use the common function.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/clk/qcom/clk-alpha-pll.c | 33 ++++++--------------------------
1 file changed, 6 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 0bdf6e45fac9..0adec585eb4f 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -845,33 +845,12 @@ static unsigned long
clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- struct regmap *regmap = pll->clkr.regmap;
- u32 l, frac;
- u64 prate = parent_rate;
-
- regmap_read(regmap, PLL_L_VAL(pll), &l);
- regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
-
- return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
-}
-
-static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
-{
- struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- unsigned long min_freq, max_freq;
- u32 l;
- u64 a;
-
- rate = alpha_pll_round_rate(rate, *prate,
- &l, &a, ALPHA_REG_16BIT_WIDTH);
- if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
- return rate;
+ u32 l, frac, alpha_width = pll_alpha_width(pll);
- min_freq = pll->vco_table[0].min_freq;
- max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
+ regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
- return clamp(rate, min_freq, max_freq);
+ return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
}
const struct clk_ops clk_alpha_pll_fixed_ops = {
@@ -917,7 +896,7 @@ const struct clk_ops clk_trion_fixed_pll_ops = {
.disable = clk_trion_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
- .round_rate = clk_trion_pll_round_rate,
+ .round_rate = clk_alpha_pll_round_rate,
};
EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
@@ -1173,7 +1152,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
* Due to limited number of bits for fractional rate programming, the
* rounded up rate could be marginally higher than the requested rate.
*/
- if (rrate > max || rrate < rate) {
+ if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
clk_hw_get_name(hw), rrate, rate, max);
return -EINVAL;
--
2.24.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 3/5] clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs
2020-02-16 10:27 [PATCH v3 0/5] Add clock drivers for SM8250 SoC Vinod Koul
2020-02-16 10:27 ` [PATCH v3 1/5] clk: qcom: clk-alpha-pll: Use common names for defines Vinod Koul
2020-02-16 10:27 ` [PATCH v3 2/5] clk: qcom: clk-alpha-pll: Refactor trion PLL Vinod Koul
@ 2020-02-16 10:27 ` Vinod Koul
2020-02-16 10:27 ` [PATCH v3 4/5] dt-bindings: clock: Add SM8250 GCC clock bindings Vinod Koul
3 siblings, 0 replies; 7+ messages in thread
From: Vinod Koul @ 2020-02-16 10:27 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-arm-msm, Bjorn Andersson, Taniya Das, Rob Herring,
Mark Rutland, devicetree, Andy Gross, Michael Turquette,
linux-clk, linux-kernel, psodagud, tsoni, jshriram, vnkgutta,
Vinod Koul
From: Taniya Das <tdas@codeaurora.org>
Add programming sequence support for managing the Lucid PLLs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/clk/qcom/clk-alpha-pll.c | 193 +++++++++++++++++++++++++++++++
drivers/clk/qcom/clk-alpha-pll.h | 12 ++
2 files changed, 205 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 0adec585eb4f..9b2dfa08acb2 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -52,6 +52,7 @@
#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
+#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
@@ -116,6 +117,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_ALPHA_VAL] = 0x40,
[PLL_OFF_CAL_VAL] = 0x44,
},
+ [CLK_ALPHA_PLL_TYPE_LUCID] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_CAL_L_VAL] = 0x08,
+ [PLL_OFF_USER_CTL] = 0x0c,
+ [PLL_OFF_USER_CTL_U] = 0x10,
+ [PLL_OFF_USER_CTL_U1] = 0x14,
+ [PLL_OFF_CONFIG_CTL] = 0x18,
+ [PLL_OFF_CONFIG_CTL_U] = 0x1c,
+ [PLL_OFF_CONFIG_CTL_U1] = 0x20,
+ [PLL_OFF_TEST_CTL] = 0x24,
+ [PLL_OFF_TEST_CTL_U] = 0x28,
+ [PLL_OFF_TEST_CTL_U1] = 0x2c,
+ [PLL_OFF_STATUS] = 0x30,
+ [PLL_OFF_OPMODE] = 0x38,
+ [PLL_OFF_ALPHA_VAL] = 0x40,
+ },
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
@@ -139,6 +156,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
#define PLL_OUT_MASK 0x7
#define PLL_RATE_MARGIN 500
+/* LUCID PLL specific settings and offsets */
+#define LUCID_PLL_CAL_VAL 0x44
+#define LUCID_PCAL_DONE BIT(26)
+
#define pll_alpha_width(p) \
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@@ -1370,3 +1391,175 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
+
+/**
+ * clk_lucid_pll_configure - configure the lucid pll
+ *
+ * @pll: clk alpha pll
+ * @regmap: register map
+ * @config: configuration to apply for pll
+ */
+void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+ const struct alpha_pll_config *config)
+{
+ if (config->l)
+ regmap_write(regmap, PLL_L_VAL(pll), config->l);
+
+ regmap_write(regmap, PLL_CAL_L_VAL(pll), LUCID_PLL_CAL_VAL);
+
+ if (config->alpha)
+ regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
+
+ if (config->config_ctl_val)
+ regmap_write(regmap, PLL_CONFIG_CTL(pll),
+ config->config_ctl_val);
+
+ if (config->config_ctl_hi_val)
+ regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
+ config->config_ctl_hi_val);
+
+ if (config->config_ctl_hi1_val)
+ regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
+ config->config_ctl_hi1_val);
+
+ if (config->user_ctl_val)
+ regmap_write(regmap, PLL_USER_CTL(pll),
+ config->user_ctl_val);
+
+ if (config->user_ctl_hi_val)
+ regmap_write(regmap, PLL_USER_CTL_U(pll),
+ config->user_ctl_hi_val);
+
+ if (config->user_ctl_hi1_val)
+ regmap_write(regmap, PLL_USER_CTL_U1(pll),
+ config->user_ctl_hi1_val);
+
+ if (config->test_ctl_val)
+ regmap_write(regmap, PLL_TEST_CTL(pll),
+ config->test_ctl_val);
+
+ if (config->test_ctl_hi_val)
+ regmap_write(regmap, PLL_TEST_CTL_U(pll),
+ config->test_ctl_hi_val);
+
+ if (config->test_ctl_hi1_val)
+ regmap_write(regmap, PLL_TEST_CTL_U1(pll),
+ config->test_ctl_hi1_val);
+
+ regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
+ PLL_UPDATE_BYPASS);
+
+ /* Disable PLL output */
+ regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
+
+ /* Set operation mode to OFF */
+ regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
+
+ /* Place the PLL in STANDBY mode */
+ regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
+}
+EXPORT_SYMBOL_GPL(clk_lucid_pll_configure);
+
+/*
+ * The Lucid PLL requires a power-on self-calibration which happens when the
+ * PLL comes out of reset. Calibrate in case it is not completed.
+ */
+static int alpha_pll_lucid_prepare(struct clk_hw *hw)
+{
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 regval;
+ int ret;
+
+ /* Return early if calibration is not needed. */
+ regmap_read(pll->clkr.regmap, PLL_STATUS(pll), ®val);
+ if (regval & LUCID_PCAL_DONE)
+ return 0;
+
+ /* On/off to calibrate */
+ ret = clk_trion_pll_enable(hw);
+ if (!ret)
+ clk_trion_pll_disable(hw);
+
+ return ret;
+}
+
+static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate)
+{
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ unsigned long rrate;
+ u32 regval, l, alpha_width = pll_alpha_width(pll);
+ u64 a;
+ int ret;
+
+ rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
+
+ /*
+ * Due to a limited number of bits for fractional rate programming, the
+ * rounded up rate could be marginally higher than the requested rate.
+ */
+ if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
+ pr_err("Call set rate on the PLL with rounded rates!\n");
+ return -EINVAL;
+ }
+
+ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
+
+ /* Latch the PLL input */
+ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
+ PLL_UPDATE, PLL_UPDATE);
+ if (ret)
+ return ret;
+
+ /* Wait for 2 reference cycles before checking the ACK bit. */
+ udelay(1);
+ regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val);
+ if (!(regval & ALPHA_PLL_ACK_LATCH)) {
+ pr_err("Lucid PLL latch failed. Output may be unstable!\n");
+ return -EINVAL;
+ }
+
+ /* Return the latch input to 0 */
+ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
+ PLL_UPDATE, 0);
+ if (ret)
+ return ret;
+
+ if (clk_hw_is_enabled(hw)) {
+ ret = wait_for_pll_enable_lock(pll);
+ if (ret)
+ return ret;
+ }
+
+ /* Wait for PLL output to stabilize */
+ udelay(100);
+ return 0;
+}
+
+const struct clk_ops clk_alpha_pll_lucid_ops = {
+ .prepare = alpha_pll_lucid_prepare,
+ .enable = clk_trion_pll_enable,
+ .disable = clk_trion_pll_disable,
+ .is_enabled = clk_trion_pll_is_enabled,
+ .recalc_rate = clk_trion_pll_recalc_rate,
+ .round_rate = clk_alpha_pll_round_rate,
+ .set_rate = alpha_pll_lucid_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
+
+const struct clk_ops clk_alpha_pll_fixed_lucid_ops = {
+ .enable = clk_trion_pll_enable,
+ .disable = clk_trion_pll_disable,
+ .is_enabled = clk_trion_pll_is_enabled,
+ .recalc_rate = clk_trion_pll_recalc_rate,
+ .round_rate = clk_alpha_pll_round_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_ops);
+
+const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
+ .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
+ .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
+ .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index fbc1f67c7a26..704674a153b6 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -14,6 +14,7 @@ enum {
CLK_ALPHA_PLL_TYPE_BRAMMO,
CLK_ALPHA_PLL_TYPE_FABIA,
CLK_ALPHA_PLL_TYPE_TRION,
+ CLK_ALPHA_PLL_TYPE_LUCID,
CLK_ALPHA_PLL_TYPE_MAX,
};
@@ -30,6 +31,7 @@ enum {
PLL_OFF_CONFIG_CTL_U1,
PLL_OFF_TEST_CTL,
PLL_OFF_TEST_CTL_U,
+ PLL_OFF_TEST_CTL_U1,
PLL_OFF_STATUS,
PLL_OFF_OPMODE,
PLL_OFF_FRAC,
@@ -94,10 +96,13 @@ struct alpha_pll_config {
u32 alpha_hi;
u32 config_ctl_val;
u32 config_ctl_hi_val;
+ u32 config_ctl_hi1_val;
u32 user_ctl_val;
u32 user_ctl_hi_val;
+ u32 user_ctl_hi1_val;
u32 test_ctl_val;
u32 test_ctl_hi_val;
+ u32 test_ctl_hi1_val;
u32 main_output_mask;
u32 aux_output_mask;
u32 aux2_output_mask;
@@ -123,10 +128,17 @@ extern const struct clk_ops clk_alpha_pll_fabia_ops;
extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
+extern const struct clk_ops clk_alpha_pll_lucid_ops;
+extern const struct clk_ops clk_alpha_pll_fixed_lucid_ops;
+extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
+
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
+void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+ const struct alpha_pll_config *config);
+
extern const struct clk_ops clk_trion_fixed_pll_ops;
extern const struct clk_ops clk_trion_pll_postdiv_ops;
--
2.24.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 4/5] dt-bindings: clock: Add SM8250 GCC clock bindings
2020-02-16 10:27 [PATCH v3 0/5] Add clock drivers for SM8250 SoC Vinod Koul
` (2 preceding siblings ...)
2020-02-16 10:27 ` [PATCH v3 3/5] clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs Vinod Koul
@ 2020-02-16 10:27 ` Vinod Koul
2020-02-18 20:33 ` Rob Herring
3 siblings, 1 reply; 7+ messages in thread
From: Vinod Koul @ 2020-02-16 10:27 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-arm-msm, Bjorn Andersson, Taniya Das, Rob Herring,
Mark Rutland, devicetree, Andy Gross, Michael Turquette,
linux-clk, linux-kernel, psodagud, tsoni, jshriram, vnkgutta,
Vinod Koul
From: Taniya Das <tdas@codeaurora.org>
Add device tree bindings for global clock controller on SM8250 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
.../bindings/clock/qcom,gcc-sm8250.yaml | 72 +++++
include/dt-bindings/clock/qcom,gcc-sm8250.h | 271 ++++++++++++++++++
2 files changed, 343 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8250.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
new file mode 100644
index 000000000000..d48fb25b0d44
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for SM8250
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <tdas@codeaurora.org>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on SM8250.
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-sm8250.h
+
+properties:
+ compatible:
+ const: qcom,gcc-sm8250
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: sleep_clk
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ protected-clocks:
+ description:
+ Protected clock specifier list as per common clock binding.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,gcc-sm8250";
+ reg = <0 0x00100000 0 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>;
+ clock-names = "bi_tcxo", "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8250.h b/include/dt-bindings/clock/qcom,gcc-sm8250.h
new file mode 100644
index 000000000000..7b7abe327e37
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sm8250.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
+
+/* GCC clocks */
+#define GPLL0 0
+#define GPLL0_OUT_EVEN 1
+#define GPLL4 2
+#define GPLL9 3
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK 4
+#define GCC_AGGRE_UFS_CARD_AXI_CLK 5
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 6
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 7
+#define GCC_AGGRE_USB3_SEC_AXI_CLK 8
+#define GCC_BOOT_ROM_AHB_CLK 9
+#define GCC_CAMERA_AHB_CLK 10
+#define GCC_CAMERA_HF_AXI_CLK 11
+#define GCC_CAMERA_SF_AXI_CLK 12
+#define GCC_CAMERA_XO_CLK 13
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 14
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 15
+#define GCC_CPUSS_AHB_CLK 16
+#define GCC_CPUSS_AHB_CLK_SRC 17
+#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 18
+#define GCC_CPUSS_DVM_BUS_CLK 19
+#define GCC_CPUSS_RBCPR_CLK 20
+#define GCC_DDRSS_GPU_AXI_CLK 21
+#define GCC_DDRSS_PCIE_SF_TBU_CLK 22
+#define GCC_DISP_AHB_CLK 23
+#define GCC_DISP_HF_AXI_CLK 24
+#define GCC_DISP_SF_AXI_CLK 25
+#define GCC_DISP_XO_CLK 26
+#define GCC_GP1_CLK 27
+#define GCC_GP1_CLK_SRC 28
+#define GCC_GP2_CLK 29
+#define GCC_GP2_CLK_SRC 30
+#define GCC_GP3_CLK 31
+#define GCC_GP3_CLK_SRC 32
+#define GCC_GPU_CFG_AHB_CLK 33
+#define GCC_GPU_GPLL0_CLK_SRC 34
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
+#define GCC_GPU_IREF_EN 36
+#define GCC_GPU_MEMNOC_GFX_CLK 37
+#define GCC_GPU_SNOC_DVM_GFX_CLK 38
+#define GCC_NPU_AXI_CLK 39
+#define GCC_NPU_BWMON_AXI_CLK 40
+#define GCC_NPU_BWMON_CFG_AHB_CLK 41
+#define GCC_NPU_CFG_AHB_CLK 42
+#define GCC_NPU_DMA_CLK 43
+#define GCC_NPU_GPLL0_CLK_SRC 44
+#define GCC_NPU_GPLL0_DIV_CLK_SRC 45
+#define GCC_PCIE0_PHY_REFGEN_CLK 46
+#define GCC_PCIE1_PHY_REFGEN_CLK 47
+#define GCC_PCIE2_PHY_REFGEN_CLK 48
+#define GCC_PCIE_0_AUX_CLK 49
+#define GCC_PCIE_0_AUX_CLK_SRC 50
+#define GCC_PCIE_0_CFG_AHB_CLK 51
+#define GCC_PCIE_0_MSTR_AXI_CLK 52
+#define GCC_PCIE_0_PIPE_CLK 53
+#define GCC_PCIE_0_SLV_AXI_CLK 54
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55
+#define GCC_PCIE_1_AUX_CLK 56
+#define GCC_PCIE_1_AUX_CLK_SRC 57
+#define GCC_PCIE_1_CFG_AHB_CLK 58
+#define GCC_PCIE_1_MSTR_AXI_CLK 59
+#define GCC_PCIE_1_PIPE_CLK 60
+#define GCC_PCIE_1_SLV_AXI_CLK 61
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 62
+#define GCC_PCIE_2_AUX_CLK 63
+#define GCC_PCIE_2_AUX_CLK_SRC 64
+#define GCC_PCIE_2_CFG_AHB_CLK 65
+#define GCC_PCIE_2_MSTR_AXI_CLK 66
+#define GCC_PCIE_2_PIPE_CLK 67
+#define GCC_PCIE_2_SLV_AXI_CLK 68
+#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 69
+#define GCC_PCIE_MDM_CLKREF_EN 70
+#define GCC_PCIE_PHY_AUX_CLK 71
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC 72
+#define GCC_PCIE_WIFI_CLKREF_EN 73
+#define GCC_PCIE_WIGIG_CLKREF_EN 74
+#define GCC_PDM2_CLK 75
+#define GCC_PDM2_CLK_SRC 76
+#define GCC_PDM_AHB_CLK 77
+#define GCC_PDM_XO4_CLK 78
+#define GCC_PRNG_AHB_CLK 79
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK 80
+#define GCC_QMIP_CAMERA_RT_AHB_CLK 81
+#define GCC_QMIP_DISP_AHB_CLK 82
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK 83
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 84
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK 85
+#define GCC_QUPV3_WRAP0_CORE_CLK 86
+#define GCC_QUPV3_WRAP0_S0_CLK 87
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 88
+#define GCC_QUPV3_WRAP0_S1_CLK 89
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 90
+#define GCC_QUPV3_WRAP0_S2_CLK 91
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 92
+#define GCC_QUPV3_WRAP0_S3_CLK 93
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 94
+#define GCC_QUPV3_WRAP0_S4_CLK 95
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 96
+#define GCC_QUPV3_WRAP0_S5_CLK 97
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 98
+#define GCC_QUPV3_WRAP0_S6_CLK 99
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC 100
+#define GCC_QUPV3_WRAP0_S7_CLK 101
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC 102
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 103
+#define GCC_QUPV3_WRAP1_CORE_CLK 104
+#define GCC_QUPV3_WRAP1_S0_CLK 105
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 106
+#define GCC_QUPV3_WRAP1_S1_CLK 107
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 108
+#define GCC_QUPV3_WRAP1_S2_CLK 109
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 110
+#define GCC_QUPV3_WRAP1_S3_CLK 111
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 112
+#define GCC_QUPV3_WRAP1_S4_CLK 113
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 114
+#define GCC_QUPV3_WRAP1_S5_CLK 115
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 116
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK 117
+#define GCC_QUPV3_WRAP2_CORE_CLK 118
+#define GCC_QUPV3_WRAP2_S0_CLK 119
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC 120
+#define GCC_QUPV3_WRAP2_S1_CLK 121
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC 122
+#define GCC_QUPV3_WRAP2_S2_CLK 123
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC 124
+#define GCC_QUPV3_WRAP2_S3_CLK 125
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC 126
+#define GCC_QUPV3_WRAP2_S4_CLK 127
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC 128
+#define GCC_QUPV3_WRAP2_S5_CLK 129
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC 130
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 131
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 132
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 133
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 134
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK 135
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK 136
+#define GCC_SDCC2_AHB_CLK 137
+#define GCC_SDCC2_APPS_CLK 138
+#define GCC_SDCC2_APPS_CLK_SRC 139
+#define GCC_SDCC4_AHB_CLK 140
+#define GCC_SDCC4_APPS_CLK 141
+#define GCC_SDCC4_APPS_CLK_SRC 142
+#define GCC_SYS_NOC_CPUSS_AHB_CLK 143
+#define GCC_TSIF_AHB_CLK 144
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK 145
+#define GCC_TSIF_REF_CLK 146
+#define GCC_TSIF_REF_CLK_SRC 147
+#define GCC_UFS_1X_CLKREF_EN 148
+#define GCC_UFS_CARD_AHB_CLK 149
+#define GCC_UFS_CARD_AXI_CLK 150
+#define GCC_UFS_CARD_AXI_CLK_SRC 151
+#define GCC_UFS_CARD_ICE_CORE_CLK 152
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 153
+#define GCC_UFS_CARD_PHY_AUX_CLK 154
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 155
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 156
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 157
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK 159
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 160
+#define GCC_UFS_PHY_AHB_CLK 161
+#define GCC_UFS_PHY_AXI_CLK 162
+#define GCC_UFS_PHY_AXI_CLK_SRC 163
+#define GCC_UFS_PHY_ICE_CORE_CLK 164
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 165
+#define GCC_UFS_PHY_PHY_AUX_CLK 166
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 167
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 168
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 169
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 170
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 171
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 172
+#define GCC_USB30_PRIM_MASTER_CLK 173
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
+#define GCC_USB30_PRIM_SLEEP_CLK 178
+#define GCC_USB30_SEC_MASTER_CLK 179
+#define GCC_USB30_SEC_MASTER_CLK_SRC 180
+#define GCC_USB30_SEC_MOCK_UTMI_CLK 181
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 182
+#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 183
+#define GCC_USB30_SEC_SLEEP_CLK 184
+#define GCC_USB3_PRIM_PHY_AUX_CLK 185
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 186
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 187
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 188
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 189
+#define GCC_USB3_SEC_CLKREF_EN 190
+#define GCC_USB3_SEC_PHY_AUX_CLK 191
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 192
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK 193
+#define GCC_USB3_SEC_PHY_PIPE_CLK 194
+#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 195
+#define GCC_VIDEO_AHB_CLK 196
+#define GCC_VIDEO_AXI0_CLK 197
+#define GCC_VIDEO_AXI1_CLK 198
+#define GCC_VIDEO_XO_CLK 199
+
+/* GCC resets */
+#define GCC_GPU_BCR 0
+#define GCC_MMSS_BCR 1
+#define GCC_NPU_BWMON_BCR 2
+#define GCC_NPU_BCR 3
+#define GCC_PCIE_0_BCR 4
+#define GCC_PCIE_0_LINK_DOWN_BCR 5
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
+#define GCC_PCIE_0_PHY_BCR 7
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
+#define GCC_PCIE_1_BCR 9
+#define GCC_PCIE_1_LINK_DOWN_BCR 10
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
+#define GCC_PCIE_1_PHY_BCR 12
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
+#define GCC_PCIE_2_BCR 14
+#define GCC_PCIE_2_LINK_DOWN_BCR 15
+#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16
+#define GCC_PCIE_2_PHY_BCR 17
+#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18
+#define GCC_PCIE_PHY_BCR 19
+#define GCC_PCIE_PHY_CFG_AHB_BCR 20
+#define GCC_PCIE_PHY_COM_BCR 21
+#define GCC_PDM_BCR 22
+#define GCC_PRNG_BCR 23
+#define GCC_QUPV3_WRAPPER_0_BCR 24
+#define GCC_QUPV3_WRAPPER_1_BCR 25
+#define GCC_QUPV3_WRAPPER_2_BCR 26
+#define GCC_QUSB2PHY_PRIM_BCR 27
+#define GCC_QUSB2PHY_SEC_BCR 28
+#define GCC_SDCC2_BCR 29
+#define GCC_SDCC4_BCR 30
+#define GCC_TSIF_BCR 31
+#define GCC_UFS_CARD_BCR 32
+#define GCC_UFS_PHY_BCR 33
+#define GCC_USB30_PRIM_BCR 34
+#define GCC_USB30_SEC_BCR 35
+#define GCC_USB3_DP_PHY_PRIM_BCR 36
+#define GCC_USB3_DP_PHY_SEC_BCR 37
+#define GCC_USB3_PHY_PRIM_BCR 38
+#define GCC_USB3_PHY_SEC_BCR 39
+#define GCC_USB3PHY_PHY_PRIM_BCR 40
+#define GCC_USB3PHY_PHY_SEC_BCR 41
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42
+#define GCC_VIDEO_AXI0_CLK_ARES 43
+#define GCC_VIDEO_AXI1_CLK_ARES 44
+
+/* GCC power domains */
+#define PCIE_0_GDSC 0
+#define PCIE_1_GDSC 1
+#define PCIE_2_GDSC 2
+#define UFS_CARD_GDSC 3
+#define UFS_PHY_GDSC 4
+#define USB30_PRIM_GDSC 5
+#define USB30_SEC_GDSC 6
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 9
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 10
+
+#endif
--
2.24.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 4/5] dt-bindings: clock: Add SM8250 GCC clock bindings
2020-02-16 10:27 ` [PATCH v3 4/5] dt-bindings: clock: Add SM8250 GCC clock bindings Vinod Koul
@ 2020-02-18 20:33 ` Rob Herring
2020-02-24 4:36 ` Vinod Koul
0 siblings, 1 reply; 7+ messages in thread
From: Rob Herring @ 2020-02-18 20:33 UTC (permalink / raw)
To: Vinod Koul
Cc: Stephen Boyd, linux-arm-msm, Bjorn Andersson, Taniya Das,
Mark Rutland, devicetree, Andy Gross, Michael Turquette,
linux-clk, linux-kernel, psodagud, tsoni, jshriram, vnkgutta
On Sun, Feb 16, 2020 at 03:57:24PM +0530, Vinod Koul wrote:
> From: Taniya Das <tdas@codeaurora.org>
>
> Add device tree bindings for global clock controller on SM8250 SoCs.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> .../bindings/clock/qcom,gcc-sm8250.yaml | 72 +++++
> include/dt-bindings/clock/qcom,gcc-sm8250.h | 271 ++++++++++++++++++
> 2 files changed, 343 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
> create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8250.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
> new file mode 100644
> index 000000000000..d48fb25b0d44
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: GPL-2.0-only
Dual license new bindings please:
(GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller Binding for SM8250
> +
> +maintainers:
> + - Stephen Boyd <sboyd@kernel.org>
> + - Taniya Das <tdas@codeaurora.org>
> +
> +description: |
> + Qualcomm global clock control module which supports the clocks, resets and
> + power domains on SM8250.
> +
> + See also:
> + - dt-bindings/clock/qcom,gcc-sm8250.h
> +
> +properties:
> + compatible:
> + const: qcom,gcc-sm8250
> +
> + clocks:
> + items:
> + - description: Board XO source
> + - description: Sleep clock source
> +
> + clock-names:
> + items:
> + - const: bi_tcxo
> + - const: sleep_clk
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + '#power-domain-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + protected-clocks:
> + description:
> + Protected clock specifier list as per common clock binding.
> +
> +required:
> + - compatible
> + - clocks
> + - clock-names
> + - reg
> + - '#clock-cells'
> + - '#reset-cells'
> + - '#power-domain-cells'
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + clock-controller@100000 {
> + compatible = "qcom,gcc-sm8250";
> + reg = <0 0x00100000 0 0x1f0000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&sleep_clk>;
> + clock-names = "bi_tcxo", "sleep_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +...
> diff --git a/include/dt-bindings/clock/qcom,gcc-sm8250.h b/include/dt-bindings/clock/qcom,gcc-sm8250.h
> new file mode 100644
> index 000000000000..7b7abe327e37
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gcc-sm8250.h
> @@ -0,0 +1,271 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
> +#define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
> +
> +/* GCC clocks */
> +#define GPLL0 0
> +#define GPLL0_OUT_EVEN 1
> +#define GPLL4 2
> +#define GPLL9 3
> +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 4
> +#define GCC_AGGRE_UFS_CARD_AXI_CLK 5
> +#define GCC_AGGRE_UFS_PHY_AXI_CLK 6
> +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 7
> +#define GCC_AGGRE_USB3_SEC_AXI_CLK 8
> +#define GCC_BOOT_ROM_AHB_CLK 9
> +#define GCC_CAMERA_AHB_CLK 10
> +#define GCC_CAMERA_HF_AXI_CLK 11
> +#define GCC_CAMERA_SF_AXI_CLK 12
> +#define GCC_CAMERA_XO_CLK 13
> +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 14
> +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 15
> +#define GCC_CPUSS_AHB_CLK 16
> +#define GCC_CPUSS_AHB_CLK_SRC 17
> +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 18
> +#define GCC_CPUSS_DVM_BUS_CLK 19
> +#define GCC_CPUSS_RBCPR_CLK 20
> +#define GCC_DDRSS_GPU_AXI_CLK 21
> +#define GCC_DDRSS_PCIE_SF_TBU_CLK 22
> +#define GCC_DISP_AHB_CLK 23
> +#define GCC_DISP_HF_AXI_CLK 24
> +#define GCC_DISP_SF_AXI_CLK 25
> +#define GCC_DISP_XO_CLK 26
> +#define GCC_GP1_CLK 27
> +#define GCC_GP1_CLK_SRC 28
> +#define GCC_GP2_CLK 29
> +#define GCC_GP2_CLK_SRC 30
> +#define GCC_GP3_CLK 31
> +#define GCC_GP3_CLK_SRC 32
> +#define GCC_GPU_CFG_AHB_CLK 33
> +#define GCC_GPU_GPLL0_CLK_SRC 34
> +#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
> +#define GCC_GPU_IREF_EN 36
> +#define GCC_GPU_MEMNOC_GFX_CLK 37
> +#define GCC_GPU_SNOC_DVM_GFX_CLK 38
> +#define GCC_NPU_AXI_CLK 39
> +#define GCC_NPU_BWMON_AXI_CLK 40
> +#define GCC_NPU_BWMON_CFG_AHB_CLK 41
> +#define GCC_NPU_CFG_AHB_CLK 42
> +#define GCC_NPU_DMA_CLK 43
> +#define GCC_NPU_GPLL0_CLK_SRC 44
> +#define GCC_NPU_GPLL0_DIV_CLK_SRC 45
> +#define GCC_PCIE0_PHY_REFGEN_CLK 46
> +#define GCC_PCIE1_PHY_REFGEN_CLK 47
> +#define GCC_PCIE2_PHY_REFGEN_CLK 48
> +#define GCC_PCIE_0_AUX_CLK 49
> +#define GCC_PCIE_0_AUX_CLK_SRC 50
> +#define GCC_PCIE_0_CFG_AHB_CLK 51
> +#define GCC_PCIE_0_MSTR_AXI_CLK 52
> +#define GCC_PCIE_0_PIPE_CLK 53
> +#define GCC_PCIE_0_SLV_AXI_CLK 54
> +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55
> +#define GCC_PCIE_1_AUX_CLK 56
> +#define GCC_PCIE_1_AUX_CLK_SRC 57
> +#define GCC_PCIE_1_CFG_AHB_CLK 58
> +#define GCC_PCIE_1_MSTR_AXI_CLK 59
> +#define GCC_PCIE_1_PIPE_CLK 60
> +#define GCC_PCIE_1_SLV_AXI_CLK 61
> +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 62
> +#define GCC_PCIE_2_AUX_CLK 63
> +#define GCC_PCIE_2_AUX_CLK_SRC 64
> +#define GCC_PCIE_2_CFG_AHB_CLK 65
> +#define GCC_PCIE_2_MSTR_AXI_CLK 66
> +#define GCC_PCIE_2_PIPE_CLK 67
> +#define GCC_PCIE_2_SLV_AXI_CLK 68
> +#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 69
> +#define GCC_PCIE_MDM_CLKREF_EN 70
> +#define GCC_PCIE_PHY_AUX_CLK 71
> +#define GCC_PCIE_PHY_REFGEN_CLK_SRC 72
> +#define GCC_PCIE_WIFI_CLKREF_EN 73
> +#define GCC_PCIE_WIGIG_CLKREF_EN 74
> +#define GCC_PDM2_CLK 75
> +#define GCC_PDM2_CLK_SRC 76
> +#define GCC_PDM_AHB_CLK 77
> +#define GCC_PDM_XO4_CLK 78
> +#define GCC_PRNG_AHB_CLK 79
> +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 80
> +#define GCC_QMIP_CAMERA_RT_AHB_CLK 81
> +#define GCC_QMIP_DISP_AHB_CLK 82
> +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 83
> +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 84
> +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 85
> +#define GCC_QUPV3_WRAP0_CORE_CLK 86
> +#define GCC_QUPV3_WRAP0_S0_CLK 87
> +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 88
> +#define GCC_QUPV3_WRAP0_S1_CLK 89
> +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 90
> +#define GCC_QUPV3_WRAP0_S2_CLK 91
> +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 92
> +#define GCC_QUPV3_WRAP0_S3_CLK 93
> +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 94
> +#define GCC_QUPV3_WRAP0_S4_CLK 95
> +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 96
> +#define GCC_QUPV3_WRAP0_S5_CLK 97
> +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 98
> +#define GCC_QUPV3_WRAP0_S6_CLK 99
> +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 100
> +#define GCC_QUPV3_WRAP0_S7_CLK 101
> +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 102
> +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 103
> +#define GCC_QUPV3_WRAP1_CORE_CLK 104
> +#define GCC_QUPV3_WRAP1_S0_CLK 105
> +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 106
> +#define GCC_QUPV3_WRAP1_S1_CLK 107
> +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 108
> +#define GCC_QUPV3_WRAP1_S2_CLK 109
> +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 110
> +#define GCC_QUPV3_WRAP1_S3_CLK 111
> +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 112
> +#define GCC_QUPV3_WRAP1_S4_CLK 113
> +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 114
> +#define GCC_QUPV3_WRAP1_S5_CLK 115
> +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 116
> +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 117
> +#define GCC_QUPV3_WRAP2_CORE_CLK 118
> +#define GCC_QUPV3_WRAP2_S0_CLK 119
> +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 120
> +#define GCC_QUPV3_WRAP2_S1_CLK 121
> +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 122
> +#define GCC_QUPV3_WRAP2_S2_CLK 123
> +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 124
> +#define GCC_QUPV3_WRAP2_S3_CLK 125
> +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 126
> +#define GCC_QUPV3_WRAP2_S4_CLK 127
> +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 128
> +#define GCC_QUPV3_WRAP2_S5_CLK 129
> +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 130
> +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 131
> +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 132
> +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 133
> +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 134
> +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 135
> +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 136
> +#define GCC_SDCC2_AHB_CLK 137
> +#define GCC_SDCC2_APPS_CLK 138
> +#define GCC_SDCC2_APPS_CLK_SRC 139
> +#define GCC_SDCC4_AHB_CLK 140
> +#define GCC_SDCC4_APPS_CLK 141
> +#define GCC_SDCC4_APPS_CLK_SRC 142
> +#define GCC_SYS_NOC_CPUSS_AHB_CLK 143
> +#define GCC_TSIF_AHB_CLK 144
> +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 145
> +#define GCC_TSIF_REF_CLK 146
> +#define GCC_TSIF_REF_CLK_SRC 147
> +#define GCC_UFS_1X_CLKREF_EN 148
> +#define GCC_UFS_CARD_AHB_CLK 149
> +#define GCC_UFS_CARD_AXI_CLK 150
> +#define GCC_UFS_CARD_AXI_CLK_SRC 151
> +#define GCC_UFS_CARD_ICE_CORE_CLK 152
> +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 153
> +#define GCC_UFS_CARD_PHY_AUX_CLK 154
> +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 155
> +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 156
> +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 157
> +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158
> +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 159
> +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 160
> +#define GCC_UFS_PHY_AHB_CLK 161
> +#define GCC_UFS_PHY_AXI_CLK 162
> +#define GCC_UFS_PHY_AXI_CLK_SRC 163
> +#define GCC_UFS_PHY_ICE_CORE_CLK 164
> +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 165
> +#define GCC_UFS_PHY_PHY_AUX_CLK 166
> +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 167
> +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 168
> +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 169
> +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 170
> +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 171
> +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 172
> +#define GCC_USB30_PRIM_MASTER_CLK 173
> +#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
> +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
> +#define GCC_USB30_PRIM_SLEEP_CLK 178
> +#define GCC_USB30_SEC_MASTER_CLK 179
> +#define GCC_USB30_SEC_MASTER_CLK_SRC 180
> +#define GCC_USB30_SEC_MOCK_UTMI_CLK 181
> +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 182
> +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 183
> +#define GCC_USB30_SEC_SLEEP_CLK 184
> +#define GCC_USB3_PRIM_PHY_AUX_CLK 185
> +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 186
> +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 187
> +#define GCC_USB3_PRIM_PHY_PIPE_CLK 188
> +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 189
> +#define GCC_USB3_SEC_CLKREF_EN 190
> +#define GCC_USB3_SEC_PHY_AUX_CLK 191
> +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 192
> +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 193
> +#define GCC_USB3_SEC_PHY_PIPE_CLK 194
> +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 195
> +#define GCC_VIDEO_AHB_CLK 196
> +#define GCC_VIDEO_AXI0_CLK 197
> +#define GCC_VIDEO_AXI1_CLK 198
> +#define GCC_VIDEO_XO_CLK 199
> +
> +/* GCC resets */
> +#define GCC_GPU_BCR 0
> +#define GCC_MMSS_BCR 1
> +#define GCC_NPU_BWMON_BCR 2
> +#define GCC_NPU_BCR 3
> +#define GCC_PCIE_0_BCR 4
> +#define GCC_PCIE_0_LINK_DOWN_BCR 5
> +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
> +#define GCC_PCIE_0_PHY_BCR 7
> +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
> +#define GCC_PCIE_1_BCR 9
> +#define GCC_PCIE_1_LINK_DOWN_BCR 10
> +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
> +#define GCC_PCIE_1_PHY_BCR 12
> +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
> +#define GCC_PCIE_2_BCR 14
> +#define GCC_PCIE_2_LINK_DOWN_BCR 15
> +#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16
> +#define GCC_PCIE_2_PHY_BCR 17
> +#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18
> +#define GCC_PCIE_PHY_BCR 19
> +#define GCC_PCIE_PHY_CFG_AHB_BCR 20
> +#define GCC_PCIE_PHY_COM_BCR 21
> +#define GCC_PDM_BCR 22
> +#define GCC_PRNG_BCR 23
> +#define GCC_QUPV3_WRAPPER_0_BCR 24
> +#define GCC_QUPV3_WRAPPER_1_BCR 25
> +#define GCC_QUPV3_WRAPPER_2_BCR 26
> +#define GCC_QUSB2PHY_PRIM_BCR 27
> +#define GCC_QUSB2PHY_SEC_BCR 28
> +#define GCC_SDCC2_BCR 29
> +#define GCC_SDCC4_BCR 30
> +#define GCC_TSIF_BCR 31
> +#define GCC_UFS_CARD_BCR 32
> +#define GCC_UFS_PHY_BCR 33
> +#define GCC_USB30_PRIM_BCR 34
> +#define GCC_USB30_SEC_BCR 35
> +#define GCC_USB3_DP_PHY_PRIM_BCR 36
> +#define GCC_USB3_DP_PHY_SEC_BCR 37
> +#define GCC_USB3_PHY_PRIM_BCR 38
> +#define GCC_USB3_PHY_SEC_BCR 39
> +#define GCC_USB3PHY_PHY_PRIM_BCR 40
> +#define GCC_USB3PHY_PHY_SEC_BCR 41
> +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42
> +#define GCC_VIDEO_AXI0_CLK_ARES 43
> +#define GCC_VIDEO_AXI1_CLK_ARES 44
> +
> +/* GCC power domains */
> +#define PCIE_0_GDSC 0
> +#define PCIE_1_GDSC 1
> +#define PCIE_2_GDSC 2
> +#define UFS_CARD_GDSC 3
> +#define UFS_PHY_GDSC 4
> +#define USB30_PRIM_GDSC 5
> +#define USB30_SEC_GDSC 6
> +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7
> +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8
> +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 9
> +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 10
> +
> +#endif
> --
> 2.24.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 4/5] dt-bindings: clock: Add SM8250 GCC clock bindings
2020-02-18 20:33 ` Rob Herring
@ 2020-02-24 4:36 ` Vinod Koul
0 siblings, 0 replies; 7+ messages in thread
From: Vinod Koul @ 2020-02-24 4:36 UTC (permalink / raw)
To: Rob Herring
Cc: Stephen Boyd, linux-arm-msm, Bjorn Andersson, Taniya Das,
Mark Rutland, devicetree, Andy Gross, Michael Turquette,
linux-clk, linux-kernel, psodagud, tsoni, jshriram, vnkgutta
On 18-02-20, 14:33, Rob Herring wrote:
> On Sun, Feb 16, 2020 at 03:57:24PM +0530, Vinod Koul wrote:
> > From: Taniya Das <tdas@codeaurora.org>
> >
> > Add device tree bindings for global clock controller on SM8250 SoCs.
> >
> > Signed-off-by: Taniya Das <tdas@codeaurora.org>
> > Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > .../bindings/clock/qcom,gcc-sm8250.yaml | 72 +++++
> > include/dt-bindings/clock/qcom,gcc-sm8250.h | 271 ++++++++++++++++++
> > 2 files changed, 343 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
> > create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8250.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
> > new file mode 100644
> > index 000000000000..d48fb25b0d44
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
> > @@ -0,0 +1,72 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
>
> Dual license new bindings please:
>
> (GPL-2.0-only OR BSD-2-Clause)
Sure will update, thanks for pointing
--
~Vinod
^ permalink raw reply [flat|nested] 7+ messages in thread