From: Matthias Kaehlcke <mka@chromium.org>
To: Rajendra Nayak <rnayak@codeaurora.org>
Cc: viresh.kumar@linaro.org, sboyd@kernel.org,
bjorn.andersson@linaro.org, agross@kernel.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Rob Clark <robdclark@gmail.com>,
Sean Paul <sean@poorly.run>,
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v2 05/17] drm/msm/dpu: Use OPP API to set clk/perf state
Date: Fri, 17 Apr 2020 11:17:24 -0700 [thread overview]
Message-ID: <20200417181724.GE199755@google.com> (raw)
In-Reply-To: <1587132279-27659-6-git-send-email-rnayak@codeaurora.org>
Hi Rajendra,
I have essentially the same comments as for "tty: serial: qcom_geni_serial:
Use OPP API to set clk/perf state" (https://patchwork.kernel.org/patch/11495209/).
about error handling of 'dev_pm_opp_of_add_table' and misleading struct
member names 'opp'/'opp_table'. Please apply the requested changes to the
entire series unless you disagree (we can keep the discussion in the patch
referenced above).
On Fri, Apr 17, 2020 at 07:34:27PM +0530, Rajendra Nayak wrote:
> On some qualcomm platforms DPU needs to express a perforamnce state
> requirement on a power domain depennding on the clock rates.
> Use OPP table from DT to register with OPP framework and use
> dev_pm_opp_set_rate() to set the clk/perf state.
>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Cc: Rob Clark <robdclark@gmail.com>
> Cc: Sean Paul <sean@poorly.run>
> Cc: dri-devel@lists.freedesktop.org
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 3 ++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 20 +++++++++++++++++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++++
> 3 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> index 11f2beb..fe5717df 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> @@ -7,6 +7,7 @@
> #include <linux/debugfs.h>
> #include <linux/errno.h>
> #include <linux/mutex.h>
> +#include <linux/pm_opp.h>
> #include <linux/sort.h>
> #include <linux/clk.h>
> #include <linux/bitmap.h>
> @@ -239,7 +240,7 @@ static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)
> rate = core_clk->max_rate;
>
> core_clk->rate = rate;
> - return msm_dss_clk_set_rate(core_clk, 1);
> + return dev_pm_opp_set_rate(&kms->pdev->dev, core_clk->rate);
> }
>
> static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index ce19f1d..cfce642 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -10,6 +10,7 @@
> #include <linux/debugfs.h>
> #include <linux/dma-buf.h>
> #include <linux/of_irq.h>
> +#include <linux/pm_opp.h>
>
> #include <drm/drm_crtc.h>
> #include <drm/drm_file.h>
> @@ -1033,11 +1034,18 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
> if (!dpu_kms)
> return -ENOMEM;
>
> + dpu_kms->opp = dev_pm_opp_set_clkname(dev, "core");
> + if (IS_ERR(dpu_kms->opp))
> + return PTR_ERR(dpu_kms->opp);
> + /* OPP table is optional */
> + if (!dev_pm_opp_of_add_table(dev))
> + dpu_kms->opp_table = true;
> +
> mp = &dpu_kms->mp;
> ret = msm_dss_parse_clock(pdev, mp);
> if (ret) {
> DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
> - return ret;
> + goto err;
> }
>
> platform_set_drvdata(pdev, dpu_kms);
> @@ -1051,6 +1059,11 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
>
> priv->kms = &dpu_kms->base;
> return ret;
> +err:
> + if (dpu_kms->opp_table)
> + dev_pm_opp_of_remove_table(dev);
> + dev_pm_opp_put_clkname(dpu_kms->opp);
> + return ret;
> }
>
> static void dpu_unbind(struct device *dev, struct device *master, void *data)
> @@ -1059,6 +1072,9 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data)
> struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
> struct dss_module_power *mp = &dpu_kms->mp;
>
> + if (dpu_kms->opp_table)
> + dev_pm_opp_of_remove_table(dev);
> + dev_pm_opp_put_clkname(dpu_kms->opp);
> msm_dss_put_clk(mp->clk_config, mp->num_clk);
> devm_kfree(&pdev->dev, mp->clk_config);
> mp->num_clk = 0;
> @@ -1090,6 +1106,8 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev)
> struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
> struct dss_module_power *mp = &dpu_kms->mp;
>
> + /* Drop the performance state vote */
> + dev_pm_opp_set_rate(dev, 0);
> rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
> if (rc)
> DPU_ERROR("clock disable failed rc:%d\n", rc);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> index 211f5de9..0060709 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> @@ -128,6 +128,10 @@ struct dpu_kms {
>
> struct platform_device *pdev;
> bool rpm_enabled;
> +
> + struct opp_table *opp;
> + bool opp_table;
> +
> struct dss_module_power mp;
>
> /* reference count bandwidth requests, so we know when we can
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2020-04-17 18:17 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-17 14:04 [PATCH v2 00/17] DVFS for IO devices on sdm845 and sc7180 Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 01/17] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-17 18:00 ` Matthias Kaehlcke
2020-04-18 8:05 ` Rajendra Nayak
2020-04-22 9:22 ` Rajendra Nayak
2020-04-23 13:51 ` Greg Kroah-Hartman
2020-04-17 14:04 ` [PATCH v2 02/17] spi: spi-geni-qcom: " Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 03/17] arm64: dts: sdm845: Add OPP table for all qup devices Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 04/17] arm64: dts: sc7180: " Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 05/17] drm/msm/dpu: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-17 18:17 ` Matthias Kaehlcke [this message]
2020-04-18 8:12 ` Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 06/17] drm/msm: dsi: " Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 07/17] arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 08/17] arm64: dts: sc7180: " Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 09/17] mmc: sdhci-msm: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-20 8:13 ` Ulf Hansson
2020-04-17 14:04 ` [PATCH v2 10/17] arm64: dts: sdm845: Add sdhc opps and power-domains Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 11/17] arm64: dts: sc7180: " Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 12/17] media: venus: core: Add support for opp tables/perf voting Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 13/17] arm64: dts: sdm845: Add OPP tables and power-domains for venus Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 14/17] arm64: dts: sc7180: " Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 15/17] spi: spi-qcom-qspi: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 16/17] arm64: dts: sdm845: Add qspi opps and power-domains Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 17/17] arm64: dts: sc7180: " Rajendra Nayak
2020-04-20 3:36 ` [PATCH v2 00/17] DVFS for IO devices on sdm845 and sc7180 Viresh Kumar
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