* [PATCH 0/2] Add adreno a405 GPU support
@ 2020-05-09 12:38 Shawn Guo
2020-05-09 12:38 ` [PATCH 1/2] drm/msm/a4xx: add adreno a405 support Shawn Guo
2020-05-09 12:38 ` [PATCH 2/2] drm/msm/a4xx: add a405_registers for a405 device Shawn Guo
0 siblings, 2 replies; 5+ messages in thread
From: Shawn Guo @ 2020-05-09 12:38 UTC (permalink / raw)
To: Rob Clark, Sean Paul, linux-arm-msm, dri-devel, freedreno
Cc: Brian Masney, Jordan Crouse, Konrad Dybcio, Shawn Guo
The series adds support for adreno a405 found on MSM8936/MSM8939 and APQ
variants.
Shawn Guo (2):
drm/msm/a4xx: add adreno a405 support
drm/msm/a4xx: add a405_registers for a405 device
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 82 ++++++++++++++++++----
drivers/gpu/drm/msm/adreno/adreno_device.c | 11 +++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++
4 files changed, 84 insertions(+), 16 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] drm/msm/a4xx: add adreno a405 support
2020-05-09 12:38 [PATCH 0/2] Add adreno a405 GPU support Shawn Guo
@ 2020-05-09 12:38 ` Shawn Guo
2020-05-18 14:38 ` Jordan Crouse
2020-05-09 12:38 ` [PATCH 2/2] drm/msm/a4xx: add a405_registers for a405 device Shawn Guo
1 sibling, 1 reply; 5+ messages in thread
From: Shawn Guo @ 2020-05-09 12:38 UTC (permalink / raw)
To: Rob Clark, Sean Paul, linux-arm-msm, dri-devel, freedreno
Cc: Brian Masney, Jordan Crouse, Konrad Dybcio, Shawn Guo
It adds support for adreno a405 found on MSM8939. The adreno_is_a430()
check in adreno_submit() needs an extension to cover a405. The
downstream driver suggests it should cover the whole a4xx generation.
That's why it gets changed to adreno_is_a4xx(), while a420 is not
tested though.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 29 +++++++++++++---------
drivers/gpu/drm/msm/adreno/adreno_device.c | 11 ++++++++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++++
4 files changed, 34 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index 253d8d85daad..70de59751188 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -66,19 +66,22 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
}
}
- for (i = 0; i < 4; i++) {
- gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i),
- 0x00000922);
- }
+ /* No CCU for A405 */
+ if (!adreno_is_a405(adreno_gpu)) {
+ for (i = 0; i < 4; i++) {
+ gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i),
+ 0x00000922);
+ }
- for (i = 0; i < 4; i++) {
- gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i),
- 0x00000000);
- }
+ for (i = 0; i < 4; i++) {
+ gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i),
+ 0x00000000);
+ }
- for (i = 0; i < 4; i++) {
- gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i),
- 0x00000001);
+ for (i = 0; i < 4; i++) {
+ gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i),
+ 0x00000001);
+ }
}
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_MODE_GPC, 0x02222222);
@@ -137,7 +140,9 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
uint32_t *ptr, len;
int i, ret;
- if (adreno_is_a420(adreno_gpu)) {
+ if (adreno_is_a405(adreno_gpu)) {
+ gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);
+ } else if (adreno_is_a420(adreno_gpu)) {
gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F);
gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4);
gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index cb3a6e597d76..b69757383965 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -92,6 +92,17 @@ static const struct adreno_info gpulist[] = {
.gmem = SZ_1M,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a3xx_gpu_init,
+ }, {
+ .rev = ADRENO_REV(4, 0, 5, ANY_ID),
+ .revn = 405,
+ .name = "A405",
+ .fw = {
+ [ADRENO_FW_PM4] = "a420_pm4.fw",
+ [ADRENO_FW_PFP] = "a420_pfp.fw",
+ },
+ .gmem = SZ_256K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a4xx_gpu_init,
}, {
.rev = ADRENO_REV(4, 2, 0, ANY_ID),
.revn = 420,
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 1d5c43c22269..3ddbf507941c 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -459,7 +459,7 @@ void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
break;
/* fall-thru */
case MSM_SUBMIT_CMD_BUF:
- OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
+ OUT_PKT3(ring, adreno_is_a4xx(adreno_gpu) ?
CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
OUT_RING(ring, submit->cmd[i].size);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 9ff4e550e7bd..35f744834ea9 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -202,6 +202,11 @@ static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
return (gpu->revn >= 400) && (gpu->revn < 500);
}
+static inline int adreno_is_a405(struct adreno_gpu *gpu)
+{
+ return gpu->revn == 405;
+}
+
static inline int adreno_is_a420(struct adreno_gpu *gpu)
{
return gpu->revn == 420;
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/msm/a4xx: add a405_registers for a405 device
2020-05-09 12:38 [PATCH 0/2] Add adreno a405 GPU support Shawn Guo
2020-05-09 12:38 ` [PATCH 1/2] drm/msm/a4xx: add adreno a405 support Shawn Guo
@ 2020-05-09 12:38 ` Shawn Guo
2020-05-18 14:39 ` Jordan Crouse
1 sibling, 1 reply; 5+ messages in thread
From: Shawn Guo @ 2020-05-09 12:38 UTC (permalink / raw)
To: Rob Clark, Sean Paul, linux-arm-msm, dri-devel, freedreno
Cc: Brian Masney, Jordan Crouse, Konrad Dybcio, Shawn Guo
A405 device has a different set of registers than a4xx_registers. It
has no VMIDMT or XPU registers, and VBIF registers are different. Let's
add a405_registers for a405 device.
As adreno_is_a405() works only after adreno_gpu_init() gets called, the
assignments get moved down after adreno_gpu_init().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 53 +++++++++++++++++++++++++--
1 file changed, 50 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index 70de59751188..9e244982974e 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -445,6 +445,52 @@ static const unsigned int a4xx_registers[] = {
~0 /* sentinel */
};
+static const unsigned int a405_registers[] = {
+ /* RBBM */
+ 0x0000, 0x0002, 0x0004, 0x0021, 0x0023, 0x0024, 0x0026, 0x0026,
+ 0x0028, 0x002B, 0x002E, 0x0034, 0x0037, 0x0044, 0x0047, 0x0066,
+ 0x0068, 0x0095, 0x009C, 0x0170, 0x0174, 0x01AF,
+ /* CP */
+ 0x0200, 0x0233, 0x0240, 0x0250, 0x04C0, 0x04DD, 0x0500, 0x050B,
+ 0x0578, 0x058F,
+ /* VSC */
+ 0x0C00, 0x0C03, 0x0C08, 0x0C41, 0x0C50, 0x0C51,
+ /* GRAS */
+ 0x0C80, 0x0C81, 0x0C88, 0x0C8F,
+ /* RB */
+ 0x0CC0, 0x0CC0, 0x0CC4, 0x0CD2,
+ /* PC */
+ 0x0D00, 0x0D0C, 0x0D10, 0x0D17, 0x0D20, 0x0D23,
+ /* VFD */
+ 0x0E40, 0x0E4A,
+ /* VPC */
+ 0x0E60, 0x0E61, 0x0E63, 0x0E68,
+ /* UCHE */
+ 0x0E80, 0x0E84, 0x0E88, 0x0E95,
+ /* GRAS CTX 0 */
+ 0x2000, 0x2004, 0x2008, 0x2067, 0x2070, 0x2078, 0x207B, 0x216E,
+ /* PC CTX 0 */
+ 0x21C0, 0x21C6, 0x21D0, 0x21D0, 0x21D9, 0x21D9, 0x21E5, 0x21E7,
+ /* VFD CTX 0 */
+ 0x2200, 0x2204, 0x2208, 0x22A9,
+ /* GRAS CTX 1 */
+ 0x2400, 0x2404, 0x2408, 0x2467, 0x2470, 0x2478, 0x247B, 0x256E,
+ /* PC CTX 1 */
+ 0x25C0, 0x25C6, 0x25D0, 0x25D0, 0x25D9, 0x25D9, 0x25E5, 0x25E7,
+ /* VFD CTX 1 */
+ 0x2600, 0x2604, 0x2608, 0x26A9,
+ /* VBIF version 0x20050000*/
+ 0x3000, 0x3007, 0x302C, 0x302C, 0x3030, 0x3030, 0x3034, 0x3036,
+ 0x3038, 0x3038, 0x303C, 0x303D, 0x3040, 0x3040, 0x3049, 0x3049,
+ 0x3058, 0x3058, 0x305B, 0x3061, 0x3064, 0x3068, 0x306C, 0x306D,
+ 0x3080, 0x3088, 0x308B, 0x308C, 0x3090, 0x3094, 0x3098, 0x3098,
+ 0x309C, 0x309C, 0x30C0, 0x30C0, 0x30C8, 0x30C8, 0x30D0, 0x30D0,
+ 0x30D8, 0x30D8, 0x30E0, 0x30E0, 0x3100, 0x3100, 0x3108, 0x3108,
+ 0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120, 0x3124, 0x3125,
+ 0x3129, 0x3129, 0x340C, 0x340C, 0x3410, 0x3410,
+ ~0 /* sentinel */
+};
+
static struct msm_gpu_state *a4xx_gpu_state_get(struct msm_gpu *gpu)
{
struct msm_gpu_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
@@ -568,13 +614,14 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
gpu->perfcntrs = NULL;
gpu->num_perfcntrs = 0;
- adreno_gpu->registers = a4xx_registers;
- adreno_gpu->reg_offsets = a4xx_register_offsets;
-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
if (ret)
goto fail;
+ adreno_gpu->registers = adreno_is_a405(adreno_gpu) ? a405_registers :
+ a4xx_registers;
+ adreno_gpu->reg_offsets = a4xx_register_offsets;
+
/* if needed, allocate gmem: */
if (adreno_is_a4xx(adreno_gpu)) {
ret = adreno_gpu_ocmem_init(dev->dev, adreno_gpu,
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/msm/a4xx: add adreno a405 support
2020-05-09 12:38 ` [PATCH 1/2] drm/msm/a4xx: add adreno a405 support Shawn Guo
@ 2020-05-18 14:38 ` Jordan Crouse
0 siblings, 0 replies; 5+ messages in thread
From: Jordan Crouse @ 2020-05-18 14:38 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Clark, Sean Paul, linux-arm-msm, dri-devel, freedreno,
Brian Masney, Konrad Dybcio
On Sat, May 09, 2020 at 08:38:45PM +0800, Shawn Guo wrote:
> It adds support for adreno a405 found on MSM8939. The adreno_is_a430()
> check in adreno_submit() needs an extension to cover a405. The
> downstream driver suggests it should cover the whole a4xx generation.
> That's why it gets changed to adreno_is_a4xx(), while a420 is not
> tested though.
This looks good to me and if it boots then that's the best test of all.
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 29 +++++++++++++---------
> drivers/gpu/drm/msm/adreno/adreno_device.c | 11 ++++++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++++
> 4 files changed, 34 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> index 253d8d85daad..70de59751188 100644
> --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> @@ -66,19 +66,22 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
> }
> }
>
> - for (i = 0; i < 4; i++) {
> - gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i),
> - 0x00000922);
> - }
> + /* No CCU for A405 */
> + if (!adreno_is_a405(adreno_gpu)) {
> + for (i = 0; i < 4; i++) {
> + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i),
> + 0x00000922);
> + }
>
> - for (i = 0; i < 4; i++) {
> - gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i),
> - 0x00000000);
> - }
> + for (i = 0; i < 4; i++) {
> + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i),
> + 0x00000000);
> + }
>
> - for (i = 0; i < 4; i++) {
> - gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i),
> - 0x00000001);
> + for (i = 0; i < 4; i++) {
> + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i),
> + 0x00000001);
> + }
> }
>
> gpu_write(gpu, REG_A4XX_RBBM_CLOCK_MODE_GPC, 0x02222222);
> @@ -137,7 +140,9 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
> uint32_t *ptr, len;
> int i, ret;
>
> - if (adreno_is_a420(adreno_gpu)) {
> + if (adreno_is_a405(adreno_gpu)) {
> + gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);
> + } else if (adreno_is_a420(adreno_gpu)) {
> gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F);
> gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4);
> gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index cb3a6e597d76..b69757383965 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -92,6 +92,17 @@ static const struct adreno_info gpulist[] = {
> .gmem = SZ_1M,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a3xx_gpu_init,
> + }, {
> + .rev = ADRENO_REV(4, 0, 5, ANY_ID),
> + .revn = 405,
> + .name = "A405",
> + .fw = {
> + [ADRENO_FW_PM4] = "a420_pm4.fw",
> + [ADRENO_FW_PFP] = "a420_pfp.fw",
> + },
> + .gmem = SZ_256K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a4xx_gpu_init,
> }, {
> .rev = ADRENO_REV(4, 2, 0, ANY_ID),
> .revn = 420,
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 1d5c43c22269..3ddbf507941c 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -459,7 +459,7 @@ void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
> break;
> /* fall-thru */
> case MSM_SUBMIT_CMD_BUF:
> - OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
> + OUT_PKT3(ring, adreno_is_a4xx(adreno_gpu) ?
> CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
> OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
> OUT_RING(ring, submit->cmd[i].size);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 9ff4e550e7bd..35f744834ea9 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -202,6 +202,11 @@ static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
> return (gpu->revn >= 400) && (gpu->revn < 500);
> }
>
> +static inline int adreno_is_a405(struct adreno_gpu *gpu)
> +{
> + return gpu->revn == 405;
> +}
> +
> static inline int adreno_is_a420(struct adreno_gpu *gpu)
> {
> return gpu->revn == 420;
> --
> 2.17.1
>
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] drm/msm/a4xx: add a405_registers for a405 device
2020-05-09 12:38 ` [PATCH 2/2] drm/msm/a4xx: add a405_registers for a405 device Shawn Guo
@ 2020-05-18 14:39 ` Jordan Crouse
0 siblings, 0 replies; 5+ messages in thread
From: Jordan Crouse @ 2020-05-18 14:39 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Clark, Sean Paul, linux-arm-msm, dri-devel, freedreno,
Brian Masney, Konrad Dybcio
On Sat, May 09, 2020 at 08:38:46PM +0800, Shawn Guo wrote:
> A405 device has a different set of registers than a4xx_registers. It
> has no VMIDMT or XPU registers, and VBIF registers are different. Let's
> add a405_registers for a405 device.
>
> As adreno_is_a405() works only after adreno_gpu_init() gets called, the
> assignments get moved down after adreno_gpu_init().
Reviewed-by: Jordan Crouse <jcrouse@codeauorora.org>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 53 +++++++++++++++++++++++++--
> 1 file changed, 50 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> index 70de59751188..9e244982974e 100644
> --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> @@ -445,6 +445,52 @@ static const unsigned int a4xx_registers[] = {
> ~0 /* sentinel */
> };
>
> +static const unsigned int a405_registers[] = {
> + /* RBBM */
> + 0x0000, 0x0002, 0x0004, 0x0021, 0x0023, 0x0024, 0x0026, 0x0026,
> + 0x0028, 0x002B, 0x002E, 0x0034, 0x0037, 0x0044, 0x0047, 0x0066,
> + 0x0068, 0x0095, 0x009C, 0x0170, 0x0174, 0x01AF,
> + /* CP */
> + 0x0200, 0x0233, 0x0240, 0x0250, 0x04C0, 0x04DD, 0x0500, 0x050B,
> + 0x0578, 0x058F,
> + /* VSC */
> + 0x0C00, 0x0C03, 0x0C08, 0x0C41, 0x0C50, 0x0C51,
> + /* GRAS */
> + 0x0C80, 0x0C81, 0x0C88, 0x0C8F,
> + /* RB */
> + 0x0CC0, 0x0CC0, 0x0CC4, 0x0CD2,
> + /* PC */
> + 0x0D00, 0x0D0C, 0x0D10, 0x0D17, 0x0D20, 0x0D23,
> + /* VFD */
> + 0x0E40, 0x0E4A,
> + /* VPC */
> + 0x0E60, 0x0E61, 0x0E63, 0x0E68,
> + /* UCHE */
> + 0x0E80, 0x0E84, 0x0E88, 0x0E95,
> + /* GRAS CTX 0 */
> + 0x2000, 0x2004, 0x2008, 0x2067, 0x2070, 0x2078, 0x207B, 0x216E,
> + /* PC CTX 0 */
> + 0x21C0, 0x21C6, 0x21D0, 0x21D0, 0x21D9, 0x21D9, 0x21E5, 0x21E7,
> + /* VFD CTX 0 */
> + 0x2200, 0x2204, 0x2208, 0x22A9,
> + /* GRAS CTX 1 */
> + 0x2400, 0x2404, 0x2408, 0x2467, 0x2470, 0x2478, 0x247B, 0x256E,
> + /* PC CTX 1 */
> + 0x25C0, 0x25C6, 0x25D0, 0x25D0, 0x25D9, 0x25D9, 0x25E5, 0x25E7,
> + /* VFD CTX 1 */
> + 0x2600, 0x2604, 0x2608, 0x26A9,
> + /* VBIF version 0x20050000*/
> + 0x3000, 0x3007, 0x302C, 0x302C, 0x3030, 0x3030, 0x3034, 0x3036,
> + 0x3038, 0x3038, 0x303C, 0x303D, 0x3040, 0x3040, 0x3049, 0x3049,
> + 0x3058, 0x3058, 0x305B, 0x3061, 0x3064, 0x3068, 0x306C, 0x306D,
> + 0x3080, 0x3088, 0x308B, 0x308C, 0x3090, 0x3094, 0x3098, 0x3098,
> + 0x309C, 0x309C, 0x30C0, 0x30C0, 0x30C8, 0x30C8, 0x30D0, 0x30D0,
> + 0x30D8, 0x30D8, 0x30E0, 0x30E0, 0x3100, 0x3100, 0x3108, 0x3108,
> + 0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120, 0x3124, 0x3125,
> + 0x3129, 0x3129, 0x340C, 0x340C, 0x3410, 0x3410,
> + ~0 /* sentinel */
> +};
> +
> static struct msm_gpu_state *a4xx_gpu_state_get(struct msm_gpu *gpu)
> {
> struct msm_gpu_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
> @@ -568,13 +614,14 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
> gpu->perfcntrs = NULL;
> gpu->num_perfcntrs = 0;
>
> - adreno_gpu->registers = a4xx_registers;
> - adreno_gpu->reg_offsets = a4xx_register_offsets;
> -
> ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
> if (ret)
> goto fail;
>
> + adreno_gpu->registers = adreno_is_a405(adreno_gpu) ? a405_registers :
> + a4xx_registers;
> + adreno_gpu->reg_offsets = a4xx_register_offsets;
> +
> /* if needed, allocate gmem: */
> if (adreno_is_a4xx(adreno_gpu)) {
> ret = adreno_gpu_ocmem_init(dev->dev, adreno_gpu,
> --
> 2.17.1
>
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-05-18 14:39 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-09 12:38 [PATCH 0/2] Add adreno a405 GPU support Shawn Guo
2020-05-09 12:38 ` [PATCH 1/2] drm/msm/a4xx: add adreno a405 support Shawn Guo
2020-05-18 14:38 ` Jordan Crouse
2020-05-09 12:38 ` [PATCH 2/2] drm/msm/a4xx: add a405_registers for a405 device Shawn Guo
2020-05-18 14:39 ` Jordan Crouse
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