[PATCH 00/11] drm/msm/dpu: cleanup plane state

[PATCH 00/11] drm/msm/dpu: cleanup plane state

[Dmitry Baryshkov]

This is a cleanup part of the DPU multirect patchset [1], split away to
ease review and merging per Abhinav's request.

Currently significant part of atomic plane state is stored in the
drm_plane's subclass rather than drm_plane_state's subclass. Move it
either to the drm_plane_state or even to the on-stack allocation.

[1] https://lore.kernel.org/linux-arm-msm/20210705012115.4179824-1-dmitry.baryshkov@linaro.org/

[PATCH 01/11] drm/msm/dpu: move LUT levels out of QOS config

[Dmitry Baryshkov]

LUT levels are setup outside of setup_qos_ctrl, so remove them from the
struct dpu_hw_pipe_qos_cfg.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 15 ++++++++-------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 ++++++----------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   | 17 ++++++-----------
 3 files changed, 20 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 69eed7932486..cbafb61404d0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -569,19 +569,20 @@ static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum
 }
 
 static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
-		struct dpu_hw_pipe_qos_cfg *cfg)
+			u32 danger_lut,
+			u32 safe_lut)
 {
 	u32 idx;
 
 	if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
 		return;
 
-	DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut);
-	DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut);
+	DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, danger_lut);
+	DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut);
 }
 
 static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
-		struct dpu_hw_pipe_qos_cfg *cfg)
+			u64 creq_lut)
 {
 	u32 idx;
 
@@ -589,11 +590,11 @@ static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
 		return;
 
 	if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) {
-		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut);
+		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, creq_lut);
 		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx,
-				cfg->creq_lut >> 32);
+				creq_lut >> 32);
 	} else {
-		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut);
+		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, creq_lut);
 	}
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index fdfd4b46e2c6..27263bc1a1ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -166,18 +166,12 @@ struct dpu_hw_pipe_cfg {
 
 /**
  * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration
- * @danger_lut: LUT for generate danger level based on fill level
- * @safe_lut: LUT for generate safe level based on fill level
- * @creq_lut: LUT for generate creq level based on fill level
  * @creq_vblank: creq value generated to vbif during vertical blanking
  * @danger_vblank: danger value generated during vertical blanking
  * @vblank_en: enable creq_vblank and danger_vblank during vblank
  * @danger_safe_en: enable danger safe generation
  */
 struct dpu_hw_pipe_qos_cfg {
-	u32 danger_lut;
-	u32 safe_lut;
-	u64 creq_lut;
 	u32 creq_vblank;
 	u32 danger_vblank;
 	bool vblank_en;
@@ -302,20 +296,22 @@ struct dpu_hw_sspp_ops {
 	/**
 	 * setup_danger_safe_lut - setup danger safe LUTs
 	 * @ctx: Pointer to pipe context
-	 * @cfg: Pointer to pipe QoS configuration
+	 * @danger_lut: LUT for generate danger level based on fill level
+	 * @safe_lut: LUT for generate safe level based on fill level
 	 *
 	 */
 	void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
-			struct dpu_hw_pipe_qos_cfg *cfg);
+			u32 danger_lut,
+			u32 safe_lut);
 
 	/**
 	 * setup_creq_lut - setup CREQ LUT
 	 * @ctx: Pointer to pipe context
-	 * @cfg: Pointer to pipe QoS configuration
+	 * @creq_lut: LUT for generate creq level based on fill level
 	 *
 	 */
 	void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
-			struct dpu_hw_pipe_qos_cfg *cfg);
+			u64 creq_lut);
 
 	/**
 	 * setup_qos_ctrl - setup QoS control
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index c989621209aa..5e0d06f26e53 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -348,8 +348,6 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
 	qos_lut = _dpu_plane_get_qos_lut(
 			&pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
 
-	pdpu->pipe_qos_cfg.creq_lut = qos_lut;
-
 	trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
 			(fmt) ? fmt->base.pixel_format : 0,
 			pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
@@ -359,7 +357,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
 			fmt ? (char *)&fmt->base.pixel_format : NULL,
 			pdpu->is_rt_pipe, total_fl, qos_lut);
 
-	pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg);
+	pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut);
 }
 
 /**
@@ -397,24 +395,21 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane,
 		}
 	}
 
-	pdpu->pipe_qos_cfg.danger_lut = danger_lut;
-	pdpu->pipe_qos_cfg.safe_lut = safe_lut;
-
 	trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
 			(fmt) ? fmt->base.pixel_format : 0,
 			(fmt) ? fmt->fetch_mode : 0,
-			pdpu->pipe_qos_cfg.danger_lut,
-			pdpu->pipe_qos_cfg.safe_lut);
+			danger_lut,
+			safe_lut);
 
 	DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
 		pdpu->pipe - SSPP_VIG0,
 		fmt ? (char *)&fmt->base.pixel_format : NULL,
 		fmt ? fmt->fetch_mode : -1,
-		pdpu->pipe_qos_cfg.danger_lut,
-		pdpu->pipe_qos_cfg.safe_lut);
+		danger_lut,
+		safe_lut);
 
 	pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
-			&pdpu->pipe_qos_cfg);
+			danger_lut, safe_lut);
 }
 
 /**
-- 
2.33.0

Re: [Freedreno] [PATCH 01/11] drm/msm/dpu: move LUT levels out of QOS config

[abhinavk]

On 2021-09-30 06:59, Dmitry Baryshkov wrote:
> LUT levels are setup outside of setup_qos_ctrl, so remove them from the
> struct dpu_hw_pipe_qos_cfg.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 15 ++++++++-------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 ++++++----------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   | 17 ++++++-----------
>  3 files changed, 20 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 69eed7932486..cbafb61404d0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -569,19 +569,20 @@ static void dpu_hw_sspp_setup_solidfill(struct
> dpu_hw_pipe *ctx, u32 color, enum
>  }
> 
>  static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx,
> -		struct dpu_hw_pipe_qos_cfg *cfg)
> +			u32 danger_lut,
> +			u32 safe_lut)
>  {
>  	u32 idx;
> 
>  	if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
>  		return;
> 
> -	DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut);
> -	DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut);
> +	DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, danger_lut);
> +	DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut);
>  }
> 
>  static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx,
> -		struct dpu_hw_pipe_qos_cfg *cfg)
> +			u64 creq_lut)
>  {
>  	u32 idx;
> 
> @@ -589,11 +590,11 @@ static void dpu_hw_sspp_setup_creq_lut(struct
> dpu_hw_pipe *ctx,
>  		return;
> 
>  	if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) {
> -		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut);
> +		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, creq_lut);
>  		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx,
> -				cfg->creq_lut >> 32);
> +				creq_lut >> 32);
>  	} else {
> -		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut);
> +		DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, creq_lut);
>  	}
>  }
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index fdfd4b46e2c6..27263bc1a1ef 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -166,18 +166,12 @@ struct dpu_hw_pipe_cfg {
> 
>  /**
>   * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration
> - * @danger_lut: LUT for generate danger level based on fill level
> - * @safe_lut: LUT for generate safe level based on fill level
> - * @creq_lut: LUT for generate creq level based on fill level
>   * @creq_vblank: creq value generated to vbif during vertical blanking
>   * @danger_vblank: danger value generated during vertical blanking
>   * @vblank_en: enable creq_vblank and danger_vblank during vblank
>   * @danger_safe_en: enable danger safe generation
>   */
>  struct dpu_hw_pipe_qos_cfg {
> -	u32 danger_lut;
> -	u32 safe_lut;
> -	u64 creq_lut;
>  	u32 creq_vblank;
>  	u32 danger_vblank;
>  	bool vblank_en;
> @@ -302,20 +296,22 @@ struct dpu_hw_sspp_ops {
>  	/**
>  	 * setup_danger_safe_lut - setup danger safe LUTs
>  	 * @ctx: Pointer to pipe context
> -	 * @cfg: Pointer to pipe QoS configuration
> +	 * @danger_lut: LUT for generate danger level based on fill level
> +	 * @safe_lut: LUT for generate safe level based on fill level
>  	 *
>  	 */
>  	void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
> -			struct dpu_hw_pipe_qos_cfg *cfg);
> +			u32 danger_lut,
> +			u32 safe_lut);
> 
>  	/**
>  	 * setup_creq_lut - setup CREQ LUT
>  	 * @ctx: Pointer to pipe context
> -	 * @cfg: Pointer to pipe QoS configuration
> +	 * @creq_lut: LUT for generate creq level based on fill level
>  	 *
>  	 */
>  	void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
> -			struct dpu_hw_pipe_qos_cfg *cfg);
> +			u64 creq_lut);
> 
>  	/**
>  	 * setup_qos_ctrl - setup QoS control
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index c989621209aa..5e0d06f26e53 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -348,8 +348,6 @@ static void _dpu_plane_set_qos_lut(struct drm_plane 
> *plane,
>  	qos_lut = _dpu_plane_get_qos_lut(
>  			&pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
> 
> -	pdpu->pipe_qos_cfg.creq_lut = qos_lut;
> -
>  	trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
>  			(fmt) ? fmt->base.pixel_format : 0,
>  			pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
> @@ -359,7 +357,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane 
> *plane,
>  			fmt ? (char *)&fmt->base.pixel_format : NULL,
>  			pdpu->is_rt_pipe, total_fl, qos_lut);
> 
> -	pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, 
> &pdpu->pipe_qos_cfg);
> +	pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut);
>  }
> 
>  /**
> @@ -397,24 +395,21 @@ static void _dpu_plane_set_danger_lut(struct
> drm_plane *plane,
>  		}
>  	}
> 
> -	pdpu->pipe_qos_cfg.danger_lut = danger_lut;
> -	pdpu->pipe_qos_cfg.safe_lut = safe_lut;
> -
>  	trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
>  			(fmt) ? fmt->base.pixel_format : 0,
>  			(fmt) ? fmt->fetch_mode : 0,
> -			pdpu->pipe_qos_cfg.danger_lut,
> -			pdpu->pipe_qos_cfg.safe_lut);
> +			danger_lut,
> +			safe_lut);
> 
>  	DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 
> 0x%x]\n",
>  		pdpu->pipe - SSPP_VIG0,
>  		fmt ? (char *)&fmt->base.pixel_format : NULL,
>  		fmt ? fmt->fetch_mode : -1,
> -		pdpu->pipe_qos_cfg.danger_lut,
> -		pdpu->pipe_qos_cfg.safe_lut);
> +		danger_lut,
> +		safe_lut);
> 
>  	pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw,
> -			&pdpu->pipe_qos_cfg);
> +			danger_lut, safe_lut);
>  }
> 
>  /**

[PATCH 02/11] drm/msm/dpu: remove pipe_qos_cfg from struct dpu_plane

[Dmitry Baryshkov]

The pipe_qos_cfg is used only in _dpu_plane_set_qos_ctrl(), so remove it
from the dpu_plane struct and allocate it on stack when necessary.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 30 ++++++++++++-----------
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 5e0d06f26e53..88d726133b8b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -105,7 +105,6 @@ struct dpu_plane {
 
 	struct dpu_hw_pipe *pipe_hw;
 	struct dpu_hw_pipe_cfg pipe_cfg;
-	struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
 	uint32_t color_fill;
 	bool is_error;
 	bool is_rt_pipe;
@@ -422,38 +421,41 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
 	bool enable, u32 flags)
 {
 	struct dpu_plane *pdpu = to_dpu_plane(plane);
+	struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
+
+	memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
 
 	if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
-		pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
-		pdpu->pipe_qos_cfg.danger_vblank =
+		pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
+		pipe_qos_cfg.danger_vblank =
 				pdpu->pipe_sblk->danger_vblank;
-		pdpu->pipe_qos_cfg.vblank_en = enable;
+		pipe_qos_cfg.vblank_en = enable;
 	}
 
 	if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) {
 		/* this feature overrules previous VBLANK_CTRL */
-		pdpu->pipe_qos_cfg.vblank_en = false;
-		pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
+		pipe_qos_cfg.vblank_en = false;
+		pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
 	}
 
 	if (flags & DPU_PLANE_QOS_PANIC_CTRL)
-		pdpu->pipe_qos_cfg.danger_safe_en = enable;
+		pipe_qos_cfg.danger_safe_en = enable;
 
 	if (!pdpu->is_rt_pipe) {
-		pdpu->pipe_qos_cfg.vblank_en = false;
-		pdpu->pipe_qos_cfg.danger_safe_en = false;
+		pipe_qos_cfg.vblank_en = false;
+		pipe_qos_cfg.danger_safe_en = false;
 	}
 
 	DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
 		pdpu->pipe - SSPP_VIG0,
-		pdpu->pipe_qos_cfg.danger_safe_en,
-		pdpu->pipe_qos_cfg.vblank_en,
-		pdpu->pipe_qos_cfg.creq_vblank,
-		pdpu->pipe_qos_cfg.danger_vblank,
+		pipe_qos_cfg.danger_safe_en,
+		pipe_qos_cfg.vblank_en,
+		pipe_qos_cfg.creq_vblank,
+		pipe_qos_cfg.danger_vblank,
 		pdpu->is_rt_pipe);
 
 	pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
-			&pdpu->pipe_qos_cfg);
+			&pipe_qos_cfg);
 }
 
 /**
-- 
2.33.0

Re: [Freedreno] [PATCH 02/11] drm/msm/dpu: remove pipe_qos_cfg from struct dpu_plane

[abhinavk]

On 2021-09-30 06:59, Dmitry Baryshkov wrote:
> The pipe_qos_cfg is used only in _dpu_plane_set_qos_ctrl(), so remove 
> it
> from the dpu_plane struct and allocate it on stack when necessary.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 30 ++++++++++++-----------
>  1 file changed, 16 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 5e0d06f26e53..88d726133b8b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -105,7 +105,6 @@ struct dpu_plane {
> 
>  	struct dpu_hw_pipe *pipe_hw;
>  	struct dpu_hw_pipe_cfg pipe_cfg;
> -	struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
>  	uint32_t color_fill;
>  	bool is_error;
>  	bool is_rt_pipe;
> @@ -422,38 +421,41 @@ static void _dpu_plane_set_qos_ctrl(struct
> drm_plane *plane,
>  	bool enable, u32 flags)
>  {
>  	struct dpu_plane *pdpu = to_dpu_plane(plane);
> +	struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
> +
> +	memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
> 
>  	if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
> -		pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
> -		pdpu->pipe_qos_cfg.danger_vblank =
> +		pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
> +		pipe_qos_cfg.danger_vblank =
>  				pdpu->pipe_sblk->danger_vblank;
> -		pdpu->pipe_qos_cfg.vblank_en = enable;
> +		pipe_qos_cfg.vblank_en = enable;
>  	}
> 
>  	if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) {
>  		/* this feature overrules previous VBLANK_CTRL */
> -		pdpu->pipe_qos_cfg.vblank_en = false;
> -		pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
> +		pipe_qos_cfg.vblank_en = false;
> +		pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
>  	}
> 
>  	if (flags & DPU_PLANE_QOS_PANIC_CTRL)
> -		pdpu->pipe_qos_cfg.danger_safe_en = enable;
> +		pipe_qos_cfg.danger_safe_en = enable;
> 
>  	if (!pdpu->is_rt_pipe) {
> -		pdpu->pipe_qos_cfg.vblank_en = false;
> -		pdpu->pipe_qos_cfg.danger_safe_en = false;
> +		pipe_qos_cfg.vblank_en = false;
> +		pipe_qos_cfg.danger_safe_en = false;
>  	}
> 
>  	DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] 
> is_rt:%d\n",
>  		pdpu->pipe - SSPP_VIG0,
> -		pdpu->pipe_qos_cfg.danger_safe_en,
> -		pdpu->pipe_qos_cfg.vblank_en,
> -		pdpu->pipe_qos_cfg.creq_vblank,
> -		pdpu->pipe_qos_cfg.danger_vblank,
> +		pipe_qos_cfg.danger_safe_en,
> +		pipe_qos_cfg.vblank_en,
> +		pipe_qos_cfg.creq_vblank,
> +		pipe_qos_cfg.danger_vblank,
>  		pdpu->is_rt_pipe);
> 
>  	pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw,
> -			&pdpu->pipe_qos_cfg);
> +			&pipe_qos_cfg);
>  }
> 
>  /**

[PATCH 03/11] drm/msm/dpu: drop pipe_name from struct dpu_plane

[Dmitry Baryshkov]

Use plane->name instead of artificial pipe_name.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 88d726133b8b..ef3737642b0c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -115,7 +115,6 @@ struct dpu_plane {
 	struct dpu_csc_cfg *csc_ptr;
 
 	const struct dpu_sspp_sub_blks *pipe_sblk;
-	char pipe_name[DPU_NAME_SIZE];
 
 	/* debugfs related stuff */
 	struct dentry *debugfs_root;
@@ -1429,7 +1428,7 @@ static int _dpu_plane_init_debugfs(struct drm_plane *plane)
 
 	/* create overall sub-directory for the pipe */
 	pdpu->debugfs_root =
-		debugfs_create_dir(pdpu->pipe_name,
+		debugfs_create_dir(plane->name,
 				plane->dev->primary->debugfs_root);
 
 	/* don't error check these */
@@ -1660,12 +1659,9 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
 	/* success! finalize initialization */
 	drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
 
-	/* save user friendly pipe name for later */
-	snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id);
-
 	mutex_init(&pdpu->lock);
 
-	DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name,
+	DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", plane->name,
 					pipe, plane->base.id, master_plane_id);
 	return plane;
 
-- 
2.33.0

Re: [Freedreno] [PATCH 03/11] drm/msm/dpu: drop pipe_name from struct dpu_plane

[abhinavk]

On 2021-09-30 06:59, Dmitry Baryshkov wrote:
> Use plane->name instead of artificial pipe_name.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 8 ++------
>  1 file changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 88d726133b8b..ef3737642b0c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -115,7 +115,6 @@ struct dpu_plane {
>  	struct dpu_csc_cfg *csc_ptr;
> 
>  	const struct dpu_sspp_sub_blks *pipe_sblk;
> -	char pipe_name[DPU_NAME_SIZE];
> 
>  	/* debugfs related stuff */
>  	struct dentry *debugfs_root;
> @@ -1429,7 +1428,7 @@ static int _dpu_plane_init_debugfs(struct
> drm_plane *plane)
> 
>  	/* create overall sub-directory for the pipe */
>  	pdpu->debugfs_root =
> -		debugfs_create_dir(pdpu->pipe_name,
> +		debugfs_create_dir(plane->name,
>  				plane->dev->primary->debugfs_root);
> 
>  	/* don't error check these */
> @@ -1660,12 +1659,9 @@ struct drm_plane *dpu_plane_init(struct 
> drm_device *dev,
>  	/* success! finalize initialization */
>  	drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
> 
> -	/* save user friendly pipe name for later */
> -	snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id);
> -
>  	mutex_init(&pdpu->lock);
> 
> -	DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", 
> pdpu->pipe_name,
> +	DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", plane->name,
>  					pipe, plane->base.id, master_plane_id);
>  	return plane;

[PATCH 04/11] drm/msm/dpu: remove stage_cfg from struct dpu_crtc

[Dmitry Baryshkov]

The stage_cfg is not used outside of _dpu_crtc_blend_setup(), so remove
the temporary config from global struct.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 ++++++-----
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |  2 --
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 768012243b44..19f0715a4089 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -207,7 +207,8 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
 }
 
 static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
-	struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer)
+	struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer,
+	struct dpu_hw_stage_cfg *stage_cfg)
 {
 	struct drm_plane *plane;
 	struct drm_framebuffer *fb;
@@ -216,7 +217,6 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
 	struct dpu_plane_state *pstate = NULL;
 	struct dpu_format *format;
 	struct dpu_hw_ctl *ctl = mixer->lm_ctl;
-	struct dpu_hw_stage_cfg *stage_cfg = &dpu_crtc->stage_cfg;
 
 	u32 flush_mask;
 	uint32_t stage_idx, lm_idx;
@@ -292,6 +292,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
 	struct dpu_crtc_mixer *mixer = cstate->mixers;
 	struct dpu_hw_ctl *ctl;
 	struct dpu_hw_mixer *lm;
+	struct dpu_hw_stage_cfg stage_cfg;
 	int i;
 
 	DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name);
@@ -305,9 +306,9 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
 	}
 
 	/* initialize stage cfg */
-	memset(&dpu_crtc->stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));
+	memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));
 
-	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
+	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg);
 
 	for (i = 0; i < cstate->num_mixers; i++) {
 		ctl = mixer[i].lm_ctl;
@@ -328,7 +329,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
 			mixer[i].flush_mask);
 
 		ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
-			&dpu_crtc->stage_cfg);
+			&stage_cfg);
 	}
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index cec3474340e8..30535acec670 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -116,7 +116,6 @@ struct dpu_crtc_frame_event {
  * @drm_requested_vblank : Whether vblanks have been enabled in the encoder
  * @property_info : Opaque structure for generic property support
  * @property_defaults : Array of default values for generic property support
- * @stage_cfg     : H/w mixer stage configuration
  * @debugfs_root  : Parent of debugfs node
  * @vblank_cb_count : count of vblank callback since last reset
  * @play_count    : frame count between crtc enable and disable
@@ -147,7 +146,6 @@ struct dpu_crtc {
 	struct drm_pending_vblank_event *event;
 	u32 vsync_count;
 
-	struct dpu_hw_stage_cfg stage_cfg;
 	struct dentry *debugfs_root;
 
 	u32 vblank_cb_count;
-- 
2.33.0

Re: [Freedreno] [PATCH 04/11] drm/msm/dpu: remove stage_cfg from struct dpu_crtc

[abhinavk]

On 2021-09-30 06:59, Dmitry Baryshkov wrote:
> The stage_cfg is not used outside of _dpu_crtc_blend_setup(), so remove
> the temporary config from global struct.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 ++++++-----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |  2 --
>  2 files changed, 6 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 768012243b44..19f0715a4089 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -207,7 +207,8 @@ static void _dpu_crtc_program_lm_output_roi(struct
> drm_crtc *crtc)
>  }
> 
>  static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
> -	struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer)
> +	struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer,
> +	struct dpu_hw_stage_cfg *stage_cfg)
>  {
>  	struct drm_plane *plane;
>  	struct drm_framebuffer *fb;
> @@ -216,7 +217,6 @@ static void _dpu_crtc_blend_setup_mixer(struct
> drm_crtc *crtc,
>  	struct dpu_plane_state *pstate = NULL;
>  	struct dpu_format *format;
>  	struct dpu_hw_ctl *ctl = mixer->lm_ctl;
> -	struct dpu_hw_stage_cfg *stage_cfg = &dpu_crtc->stage_cfg;
> 
>  	u32 flush_mask;
>  	uint32_t stage_idx, lm_idx;
> @@ -292,6 +292,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc 
> *crtc)
>  	struct dpu_crtc_mixer *mixer = cstate->mixers;
>  	struct dpu_hw_ctl *ctl;
>  	struct dpu_hw_mixer *lm;
> +	struct dpu_hw_stage_cfg stage_cfg;
>  	int i;
> 
>  	DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name);
> @@ -305,9 +306,9 @@ static void _dpu_crtc_blend_setup(struct drm_crtc 
> *crtc)
>  	}
> 
>  	/* initialize stage cfg */
> -	memset(&dpu_crtc->stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));
> +	memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));
> 
> -	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
> +	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg);
> 
>  	for (i = 0; i < cstate->num_mixers; i++) {
>  		ctl = mixer[i].lm_ctl;
> @@ -328,7 +329,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc 
> *crtc)
>  			mixer[i].flush_mask);
> 
>  		ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
> -			&dpu_crtc->stage_cfg);
> +			&stage_cfg);
>  	}
>  }
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index cec3474340e8..30535acec670 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -116,7 +116,6 @@ struct dpu_crtc_frame_event {
>   * @drm_requested_vblank : Whether vblanks have been enabled in the 
> encoder
>   * @property_info : Opaque structure for generic property support
>   * @property_defaults : Array of default values for generic property 
> support
> - * @stage_cfg     : H/w mixer stage configuration
>   * @debugfs_root  : Parent of debugfs node
>   * @vblank_cb_count : count of vblank callback since last reset
>   * @play_count    : frame count between crtc enable and disable
> @@ -147,7 +146,6 @@ struct dpu_crtc {
>  	struct drm_pending_vblank_event *event;
>  	u32 vsync_count;
> 
> -	struct dpu_hw_stage_cfg stage_cfg;
>  	struct dentry *debugfs_root;
> 
>  	u32 vblank_cb_count;

[PATCH 05/11] drm/msm/dpu: move dpu_hw_pipe_cfg out of struct dpu_plane

[Dmitry Baryshkov]

struct dpu_hw_pipe_cfg represents an interim state during atomic
update/color fill, so move it out of struct dpu_plane.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 104 ++++++++++++----------
 1 file changed, 57 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index ef3737642b0c..5288b5b824f8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -104,7 +104,6 @@ struct dpu_plane {
 	uint32_t features;      /* capabilities from catalog */
 
 	struct dpu_hw_pipe *pipe_hw;
-	struct dpu_hw_pipe_cfg pipe_cfg;
 	uint32_t color_fill;
 	bool is_error;
 	bool is_rt_pipe;
@@ -143,14 +142,15 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
  * _dpu_plane_calc_bw - calculate bandwidth required for a plane
  * @plane: Pointer to drm plane.
  * @fb:   Pointer to framebuffer associated with the given plane
+ * @pipe_cfg: Pointer to pipe configuration
  * Result: Updates calculated bandwidth in the plane state.
  * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest)
  * Prefill BW Equation: line src bytes * line_time
  */
 static void _dpu_plane_calc_bw(struct drm_plane *plane,
-	struct drm_framebuffer *fb)
+	struct drm_framebuffer *fb,
+	struct dpu_hw_pipe_cfg *pipe_cfg)
 {
-	struct dpu_plane *pdpu = to_dpu_plane(plane);
 	struct dpu_plane_state *pstate;
 	struct drm_display_mode *mode;
 	const struct dpu_format *fmt = NULL;
@@ -167,9 +167,9 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
 
 	fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier);
 
-	src_width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
-	src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
-	dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect);
+	src_width = drm_rect_width(&pipe_cfg->src_rect);
+	src_height = drm_rect_height(&pipe_cfg->src_rect);
+	dst_height = drm_rect_height(&pipe_cfg->dst_rect);
 	fps = drm_mode_vrefresh(mode);
 	vbp = mode->vtotal - mode->vsync_end;
 	vpw = mode->vsync_end - mode->vsync_start;
@@ -200,12 +200,12 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
 /**
  * _dpu_plane_calc_clk - calculate clock required for a plane
  * @plane: Pointer to drm plane.
+ * @pipe_cfg: Pointer to pipe configuration
  * Result: Updates calculated clock in the plane state.
  * Clock equation: dst_w * v_total * fps * (src_h / dst_h)
  */
-static void _dpu_plane_calc_clk(struct drm_plane *plane)
+static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_pipe_cfg *pipe_cfg)
 {
-	struct dpu_plane *pdpu = to_dpu_plane(plane);
 	struct dpu_plane_state *pstate;
 	struct drm_display_mode *mode;
 	int dst_width, src_height, dst_height, fps;
@@ -213,9 +213,9 @@ static void _dpu_plane_calc_clk(struct drm_plane *plane)
 	pstate = to_dpu_plane_state(plane->state);
 	mode = &plane->state->crtc->mode;
 
-	src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
-	dst_width = drm_rect_width(&pdpu->pipe_cfg.dst_rect);
-	dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect);
+	src_height = drm_rect_height(&pipe_cfg->src_rect);
+	dst_width = drm_rect_width(&pipe_cfg->dst_rect);
+	dst_height = drm_rect_height(&pipe_cfg->dst_rect);
 	fps = drm_mode_vrefresh(mode);
 
 	pstate->plane_clk =
@@ -252,14 +252,17 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
 	fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
 
 	list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
+		u32 tmp_width;
+
 		if (!tmp->base.state->visible)
 			continue;
+		tmp_width = drm_rect_width(&tmp->base.state->src) >> 16;
 		DPU_DEBUG("plane%d/%d src_width:%d/%d\n",
 				pdpu->base.base.id, tmp->base.base.id,
 				src_width,
-				drm_rect_width(&tmp->pipe_cfg.src_rect));
+				tmp_width);
 		src_width = max_t(u32, src_width,
-				  drm_rect_width(&tmp->pipe_cfg.src_rect));
+				  tmp_width);
 	}
 
 	if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
@@ -319,9 +322,10 @@ static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
  * _dpu_plane_set_qos_lut - set QoS LUT of the given plane
  * @plane:		Pointer to drm plane
  * @fb:			Pointer to framebuffer associated with the given plane
+ * @pipe_cfg:		Pointer to pipe configuration
  */
 static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
-		struct drm_framebuffer *fb)
+		struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg)
 {
 	struct dpu_plane *pdpu = to_dpu_plane(plane);
 	const struct dpu_format *fmt = NULL;
@@ -335,7 +339,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
 				fb->format->format,
 				fb->modifier);
 		total_fl = _dpu_plane_calc_fill_level(plane, fmt,
-				drm_rect_width(&pdpu->pipe_cfg.src_rect));
+				drm_rect_width(&pipe_cfg->src_rect));
 
 		if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
 			lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
@@ -461,9 +465,10 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
  * _dpu_plane_set_ot_limit - set OT limit for the given plane
  * @plane:		Pointer to drm plane
  * @crtc:		Pointer to drm crtc
+ * @pipe_cfg:		Pointer to pipe configuration
  */
 static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
-		struct drm_crtc *crtc)
+		struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg)
 {
 	struct dpu_plane *pdpu = to_dpu_plane(plane);
 	struct dpu_vbif_set_ot_params ot_params;
@@ -472,8 +477,8 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
 	memset(&ot_params, 0, sizeof(ot_params));
 	ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
 	ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
-	ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
-	ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
+	ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
+	ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
 	ot_params.is_wfd = !pdpu->is_rt_pipe;
 	ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
 	ot_params.vbif_idx = VBIF_RT;
@@ -651,17 +656,18 @@ static void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
 
 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
 		struct dpu_plane_state *pstate,
-		const struct dpu_format *fmt, bool color_fill)
+		const struct dpu_format *fmt, bool color_fill,
+		struct dpu_hw_pipe_cfg *pipe_cfg)
 {
 	const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
 
 	/* don't chroma subsample if decimating */
 	/* update scaler. calculate default config for QSEED3 */
 	_dpu_plane_setup_scaler3(pdpu, pstate,
-			drm_rect_width(&pdpu->pipe_cfg.src_rect),
-			drm_rect_height(&pdpu->pipe_cfg.src_rect),
-			drm_rect_width(&pdpu->pipe_cfg.dst_rect),
-			drm_rect_height(&pdpu->pipe_cfg.dst_rect),
+			drm_rect_width(&pipe_cfg->src_rect),
+			drm_rect_height(&pipe_cfg->src_rect),
+			drm_rect_width(&pipe_cfg->dst_rect),
+			drm_rect_height(&pipe_cfg->dst_rect),
 			&pstate->scaler3_cfg, fmt,
 			info->hsub, info->vsub);
 }
@@ -679,6 +685,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
 	const struct dpu_format *fmt;
 	const struct drm_plane *plane = &pdpu->base;
 	struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
+	struct dpu_hw_pipe_cfg pipe_cfg;
 
 	DPU_DEBUG_PLANE(pdpu, "\n");
 
@@ -695,13 +702,15 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
 				pstate->multirect_index);
 
 		/* override scaler/decimation if solid fill */
-		pdpu->pipe_cfg.src_rect.x1 = 0;
-		pdpu->pipe_cfg.src_rect.y1 = 0;
-		pdpu->pipe_cfg.src_rect.x2 =
-			drm_rect_width(&pdpu->pipe_cfg.dst_rect);
-		pdpu->pipe_cfg.src_rect.y2 =
-			drm_rect_height(&pdpu->pipe_cfg.dst_rect);
-		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true);
+		pipe_cfg.dst_rect = pstate->base.dst;
+
+		pipe_cfg.src_rect.x1 = 0;
+		pipe_cfg.src_rect.y1 = 0;
+		pipe_cfg.src_rect.x2 =
+			drm_rect_width(&pipe_cfg.dst_rect);
+		pipe_cfg.src_rect.y2 =
+			drm_rect_height(&pipe_cfg.dst_rect);
+		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
 
 		if (pdpu->pipe_hw->ops.setup_format)
 			pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
@@ -710,7 +719,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
 
 		if (pdpu->pipe_hw->ops.setup_rects)
 			pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
-					&pdpu->pipe_cfg,
+					&pipe_cfg,
 					pstate->multirect_index);
 
 		if (pdpu->pipe_hw->ops.setup_pe)
@@ -720,7 +729,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
 		if (pdpu->pipe_hw->ops.setup_scaler &&
 				pstate->multirect_index != DPU_SSPP_RECT_1)
 			pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
-					&pdpu->pipe_cfg, &pstate->pixel_ext,
+					&pipe_cfg, &pstate->pixel_ext,
 					&pstate->scaler3_cfg);
 	}
 
@@ -1087,10 +1096,11 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 	bool is_rt_pipe, update_qos_remap;
 	const struct dpu_format *fmt =
 		to_dpu_format(msm_framebuffer_format(fb));
+	struct dpu_hw_pipe_cfg pipe_cfg;
 
-	memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg));
+	memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
 
-	_dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb);
+	_dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
 
 	pstate->pending = true;
 
@@ -1102,17 +1112,17 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 			crtc->base.id, DRM_RECT_ARG(&state->dst),
 			(char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
 
-	pdpu->pipe_cfg.src_rect = state->src;
+	pipe_cfg.src_rect = state->src;
 
 	/* state->src is 16.16, src_rect is not */
-	pdpu->pipe_cfg.src_rect.x1 >>= 16;
-	pdpu->pipe_cfg.src_rect.x2 >>= 16;
-	pdpu->pipe_cfg.src_rect.y1 >>= 16;
-	pdpu->pipe_cfg.src_rect.y2 >>= 16;
+	pipe_cfg.src_rect.x1 >>= 16;
+	pipe_cfg.src_rect.x2 >>= 16;
+	pipe_cfg.src_rect.y1 >>= 16;
+	pipe_cfg.src_rect.y2 >>= 16;
 
-	pdpu->pipe_cfg.dst_rect = state->dst;
+	pipe_cfg.dst_rect = state->dst;
 
-	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false);
+	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
 
 	/* override for color fill */
 	if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
@@ -1122,7 +1132,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 
 	if (pdpu->pipe_hw->ops.setup_rects) {
 		pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
-				&pdpu->pipe_cfg,
+				&pipe_cfg,
 				pstate->multirect_index);
 	}
 
@@ -1139,7 +1149,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 	if (pdpu->pipe_hw->ops.setup_scaler &&
 			pstate->multirect_index != DPU_SSPP_RECT_1)
 		pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
-				&pdpu->pipe_cfg, &pstate->pixel_ext,
+				&pipe_cfg, &pstate->pixel_ext,
 				&pstate->scaler3_cfg);
 
 	if (pdpu->pipe_hw->ops.setup_multirect)
@@ -1192,12 +1202,12 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 			pdpu->csc_ptr = 0;
 	}
 
-	_dpu_plane_set_qos_lut(plane, fb);
+	_dpu_plane_set_qos_lut(plane, fb, &pipe_cfg);
 	_dpu_plane_set_danger_lut(plane, fb);
 
 	if (plane->type != DRM_PLANE_TYPE_CURSOR) {
 		_dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
-		_dpu_plane_set_ot_limit(plane, crtc);
+		_dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg);
 	}
 
 	update_qos_remap = (is_rt_pipe != pdpu->is_rt_pipe) ||
@@ -1211,9 +1221,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 		_dpu_plane_set_qos_remap(plane);
 	}
 
-	_dpu_plane_calc_bw(plane, fb);
+	_dpu_plane_calc_bw(plane, fb, &pipe_cfg);
 
-	_dpu_plane_calc_clk(plane);
+	_dpu_plane_calc_clk(plane, &pipe_cfg);
 }
 
 static void _dpu_plane_atomic_disable(struct drm_plane *plane)
-- 
2.33.0

Re: [Freedreno] [PATCH 05/11] drm/msm/dpu: move dpu_hw_pipe_cfg out of struct dpu_plane

[abhinavk]

On 2021-09-30 06:59, Dmitry Baryshkov wrote:
> struct dpu_hw_pipe_cfg represents an interim state during atomic
> update/color fill, so move it out of struct dpu_plane.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 104 ++++++++++++----------
>  1 file changed, 57 insertions(+), 47 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index ef3737642b0c..5288b5b824f8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -104,7 +104,6 @@ struct dpu_plane {
>  	uint32_t features;      /* capabilities from catalog */
> 
>  	struct dpu_hw_pipe *pipe_hw;
> -	struct dpu_hw_pipe_cfg pipe_cfg;
>  	uint32_t color_fill;
>  	bool is_error;
>  	bool is_rt_pipe;
> @@ -143,14 +142,15 @@ static struct dpu_kms *_dpu_plane_get_kms(struct
> drm_plane *plane)
>   * _dpu_plane_calc_bw - calculate bandwidth required for a plane
>   * @plane: Pointer to drm plane.
>   * @fb:   Pointer to framebuffer associated with the given plane
> + * @pipe_cfg: Pointer to pipe configuration
>   * Result: Updates calculated bandwidth in the plane state.
>   * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest)
>   * Prefill BW Equation: line src bytes * line_time
>   */
>  static void _dpu_plane_calc_bw(struct drm_plane *plane,
> -	struct drm_framebuffer *fb)
> +	struct drm_framebuffer *fb,
> +	struct dpu_hw_pipe_cfg *pipe_cfg)
>  {
> -	struct dpu_plane *pdpu = to_dpu_plane(plane);
>  	struct dpu_plane_state *pstate;
>  	struct drm_display_mode *mode;
>  	const struct dpu_format *fmt = NULL;
> @@ -167,9 +167,9 @@ static void _dpu_plane_calc_bw(struct drm_plane 
> *plane,
> 
>  	fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier);
> 
> -	src_width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
> -	src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
> -	dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect);
> +	src_width = drm_rect_width(&pipe_cfg->src_rect);
> +	src_height = drm_rect_height(&pipe_cfg->src_rect);
> +	dst_height = drm_rect_height(&pipe_cfg->dst_rect);
>  	fps = drm_mode_vrefresh(mode);
>  	vbp = mode->vtotal - mode->vsync_end;
>  	vpw = mode->vsync_end - mode->vsync_start;
> @@ -200,12 +200,12 @@ static void _dpu_plane_calc_bw(struct drm_plane 
> *plane,
>  /**
>   * _dpu_plane_calc_clk - calculate clock required for a plane
>   * @plane: Pointer to drm plane.
> + * @pipe_cfg: Pointer to pipe configuration
>   * Result: Updates calculated clock in the plane state.
>   * Clock equation: dst_w * v_total * fps * (src_h / dst_h)
>   */
> -static void _dpu_plane_calc_clk(struct drm_plane *plane)
> +static void _dpu_plane_calc_clk(struct drm_plane *plane, struct
> dpu_hw_pipe_cfg *pipe_cfg)
>  {
> -	struct dpu_plane *pdpu = to_dpu_plane(plane);
>  	struct dpu_plane_state *pstate;
>  	struct drm_display_mode *mode;
>  	int dst_width, src_height, dst_height, fps;
> @@ -213,9 +213,9 @@ static void _dpu_plane_calc_clk(struct drm_plane 
> *plane)
>  	pstate = to_dpu_plane_state(plane->state);
>  	mode = &plane->state->crtc->mode;
> 
> -	src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
> -	dst_width = drm_rect_width(&pdpu->pipe_cfg.dst_rect);
> -	dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect);
> +	src_height = drm_rect_height(&pipe_cfg->src_rect);
> +	dst_width = drm_rect_width(&pipe_cfg->dst_rect);
> +	dst_height = drm_rect_height(&pipe_cfg->dst_rect);
>  	fps = drm_mode_vrefresh(mode);
> 
>  	pstate->plane_clk =
> @@ -252,14 +252,17 @@ static int _dpu_plane_calc_fill_level(struct
> drm_plane *plane,
>  	fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
> 
>  	list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
> +		u32 tmp_width;
> +
>  		if (!tmp->base.state->visible)
>  			continue;
> +		tmp_width = drm_rect_width(&tmp->base.state->src) >> 16;
>  		DPU_DEBUG("plane%d/%d src_width:%d/%d\n",
>  				pdpu->base.base.id, tmp->base.base.id,
>  				src_width,
> -				drm_rect_width(&tmp->pipe_cfg.src_rect));
> +				tmp_width);
>  		src_width = max_t(u32, src_width,
> -				  drm_rect_width(&tmp->pipe_cfg.src_rect));
> +				  tmp_width);
>  	}
> 
>  	if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
> @@ -319,9 +322,10 @@ static u64 _dpu_plane_get_qos_lut(const struct
> dpu_qos_lut_tbl *tbl,
>   * _dpu_plane_set_qos_lut - set QoS LUT of the given plane
>   * @plane:		Pointer to drm plane
>   * @fb:			Pointer to framebuffer associated with the given plane
> + * @pipe_cfg:		Pointer to pipe configuration
>   */
>  static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
> -		struct drm_framebuffer *fb)
> +		struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg)
>  {
>  	struct dpu_plane *pdpu = to_dpu_plane(plane);
>  	const struct dpu_format *fmt = NULL;
> @@ -335,7 +339,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane 
> *plane,
>  				fb->format->format,
>  				fb->modifier);
>  		total_fl = _dpu_plane_calc_fill_level(plane, fmt,
> -				drm_rect_width(&pdpu->pipe_cfg.src_rect));
> +				drm_rect_width(&pipe_cfg->src_rect));
> 
>  		if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
>  			lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
> @@ -461,9 +465,10 @@ static void _dpu_plane_set_qos_ctrl(struct
> drm_plane *plane,
>   * _dpu_plane_set_ot_limit - set OT limit for the given plane
>   * @plane:		Pointer to drm plane
>   * @crtc:		Pointer to drm crtc
> + * @pipe_cfg:		Pointer to pipe configuration
>   */
>  static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
> -		struct drm_crtc *crtc)
> +		struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg)
>  {
>  	struct dpu_plane *pdpu = to_dpu_plane(plane);
>  	struct dpu_vbif_set_ot_params ot_params;
> @@ -472,8 +477,8 @@ static void _dpu_plane_set_ot_limit(struct 
> drm_plane *plane,
>  	memset(&ot_params, 0, sizeof(ot_params));
>  	ot_params.xin_id = pdpu->pipe_hw->cap->xin_id;
>  	ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE;
> -	ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect);
> -	ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect);
> +	ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
> +	ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
>  	ot_params.is_wfd = !pdpu->is_rt_pipe;
>  	ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
>  	ot_params.vbif_idx = VBIF_RT;
> @@ -651,17 +656,18 @@ static void _dpu_plane_setup_csc(struct dpu_plane 
> *pdpu)
> 
>  static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
>  		struct dpu_plane_state *pstate,
> -		const struct dpu_format *fmt, bool color_fill)
> +		const struct dpu_format *fmt, bool color_fill,
> +		struct dpu_hw_pipe_cfg *pipe_cfg)
>  {
>  	const struct drm_format_info *info = 
> drm_format_info(fmt->base.pixel_format);
> 
>  	/* don't chroma subsample if decimating */
>  	/* update scaler. calculate default config for QSEED3 */
>  	_dpu_plane_setup_scaler3(pdpu, pstate,
> -			drm_rect_width(&pdpu->pipe_cfg.src_rect),
> -			drm_rect_height(&pdpu->pipe_cfg.src_rect),
> -			drm_rect_width(&pdpu->pipe_cfg.dst_rect),
> -			drm_rect_height(&pdpu->pipe_cfg.dst_rect),
> +			drm_rect_width(&pipe_cfg->src_rect),
> +			drm_rect_height(&pipe_cfg->src_rect),
> +			drm_rect_width(&pipe_cfg->dst_rect),
> +			drm_rect_height(&pipe_cfg->dst_rect),
>  			&pstate->scaler3_cfg, fmt,
>  			info->hsub, info->vsub);
>  }
> @@ -679,6 +685,7 @@ static int _dpu_plane_color_fill(struct dpu_plane 
> *pdpu,
>  	const struct dpu_format *fmt;
>  	const struct drm_plane *plane = &pdpu->base;
>  	struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> +	struct dpu_hw_pipe_cfg pipe_cfg;
> 
>  	DPU_DEBUG_PLANE(pdpu, "\n");
> 
> @@ -695,13 +702,15 @@ static int _dpu_plane_color_fill(struct dpu_plane 
> *pdpu,
>  				pstate->multirect_index);
> 
>  		/* override scaler/decimation if solid fill */
> -		pdpu->pipe_cfg.src_rect.x1 = 0;
> -		pdpu->pipe_cfg.src_rect.y1 = 0;
> -		pdpu->pipe_cfg.src_rect.x2 =
> -			drm_rect_width(&pdpu->pipe_cfg.dst_rect);
> -		pdpu->pipe_cfg.src_rect.y2 =
> -			drm_rect_height(&pdpu->pipe_cfg.dst_rect);
> -		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true);
> +		pipe_cfg.dst_rect = pstate->base.dst;
> +
> +		pipe_cfg.src_rect.x1 = 0;
> +		pipe_cfg.src_rect.y1 = 0;
> +		pipe_cfg.src_rect.x2 =
> +			drm_rect_width(&pipe_cfg.dst_rect);
> +		pipe_cfg.src_rect.y2 =
> +			drm_rect_height(&pipe_cfg.dst_rect);
> +		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
> 
>  		if (pdpu->pipe_hw->ops.setup_format)
>  			pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
> @@ -710,7 +719,7 @@ static int _dpu_plane_color_fill(struct dpu_plane 
> *pdpu,
> 
>  		if (pdpu->pipe_hw->ops.setup_rects)
>  			pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
> -					&pdpu->pipe_cfg,
> +					&pipe_cfg,
>  					pstate->multirect_index);
> 
>  		if (pdpu->pipe_hw->ops.setup_pe)
> @@ -720,7 +729,7 @@ static int _dpu_plane_color_fill(struct dpu_plane 
> *pdpu,
>  		if (pdpu->pipe_hw->ops.setup_scaler &&
>  				pstate->multirect_index != DPU_SSPP_RECT_1)
>  			pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
> -					&pdpu->pipe_cfg, &pstate->pixel_ext,
> +					&pipe_cfg, &pstate->pixel_ext,
>  					&pstate->scaler3_cfg);
>  	}
> 
> @@ -1087,10 +1096,11 @@ static void
> dpu_plane_sspp_atomic_update(struct drm_plane *plane)
>  	bool is_rt_pipe, update_qos_remap;
>  	const struct dpu_format *fmt =
>  		to_dpu_format(msm_framebuffer_format(fb));
> +	struct dpu_hw_pipe_cfg pipe_cfg;
> 
> -	memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg));
> +	memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg));
> 
> -	_dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb);
> +	_dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb);
> 
>  	pstate->pending = true;
> 
> @@ -1102,17 +1112,17 @@ static void
> dpu_plane_sspp_atomic_update(struct drm_plane *plane)
>  			crtc->base.id, DRM_RECT_ARG(&state->dst),
>  			(char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
> 
> -	pdpu->pipe_cfg.src_rect = state->src;
> +	pipe_cfg.src_rect = state->src;
> 
>  	/* state->src is 16.16, src_rect is not */
> -	pdpu->pipe_cfg.src_rect.x1 >>= 16;
> -	pdpu->pipe_cfg.src_rect.x2 >>= 16;
> -	pdpu->pipe_cfg.src_rect.y1 >>= 16;
> -	pdpu->pipe_cfg.src_rect.y2 >>= 16;
> +	pipe_cfg.src_rect.x1 >>= 16;
> +	pipe_cfg.src_rect.x2 >>= 16;
> +	pipe_cfg.src_rect.y1 >>= 16;
> +	pipe_cfg.src_rect.y2 >>= 16;
> 
> -	pdpu->pipe_cfg.dst_rect = state->dst;
> +	pipe_cfg.dst_rect = state->dst;
> 
> -	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false);
> +	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
> 
>  	/* override for color fill */
>  	if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
> @@ -1122,7 +1132,7 @@ static void dpu_plane_sspp_atomic_update(struct
> drm_plane *plane)
> 
>  	if (pdpu->pipe_hw->ops.setup_rects) {
>  		pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw,
> -				&pdpu->pipe_cfg,
> +				&pipe_cfg,
>  				pstate->multirect_index);
>  	}
> 
> @@ -1139,7 +1149,7 @@ static void dpu_plane_sspp_atomic_update(struct
> drm_plane *plane)
>  	if (pdpu->pipe_hw->ops.setup_scaler &&
>  			pstate->multirect_index != DPU_SSPP_RECT_1)
>  		pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
> -				&pdpu->pipe_cfg, &pstate->pixel_ext,
> +				&pipe_cfg, &pstate->pixel_ext,
>  				&pstate->scaler3_cfg);
> 
>  	if (pdpu->pipe_hw->ops.setup_multirect)
> @@ -1192,12 +1202,12 @@ static void
> dpu_plane_sspp_atomic_update(struct drm_plane *plane)
>  			pdpu->csc_ptr = 0;
>  	}
> 
> -	_dpu_plane_set_qos_lut(plane, fb);
> +	_dpu_plane_set_qos_lut(plane, fb, &pipe_cfg);
>  	_dpu_plane_set_danger_lut(plane, fb);
> 
>  	if (plane->type != DRM_PLANE_TYPE_CURSOR) {
>  		_dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL);
> -		_dpu_plane_set_ot_limit(plane, crtc);
> +		_dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg);
>  	}
> 
>  	update_qos_remap = (is_rt_pipe != pdpu->is_rt_pipe) ||
> @@ -1211,9 +1221,9 @@ static void dpu_plane_sspp_atomic_update(struct
> drm_plane *plane)
>  		_dpu_plane_set_qos_remap(plane);
>  	}
> 
> -	_dpu_plane_calc_bw(plane, fb);
> +	_dpu_plane_calc_bw(plane, fb, &pipe_cfg);
> 
> -	_dpu_plane_calc_clk(plane);
> +	_dpu_plane_calc_clk(plane, &pipe_cfg);
>  }
> 
>  static void _dpu_plane_atomic_disable(struct drm_plane *plane)

[PATCH 06/11] drm/msm/dpu: drop scaler config from plane state

[Dmitry Baryshkov]

Scaler and pixel_ext configuration does not contain a long living state,
it is used only during plane update, so remove these two fiels from
dpu_plane_state and allocate them on stack.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 59 ++++++++++-------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |  6 ---
 2 files changed, 26 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 5288b5b824f8..4259c4ecde9b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -542,14 +542,12 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
 		struct dpu_plane_state *pstate,
 		uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
 		struct dpu_hw_scaler3_cfg *scale_cfg,
+		struct dpu_hw_pixel_ext *pixel_ext,
 		const struct dpu_format *fmt,
 		uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
 {
 	uint32_t i;
 
-	memset(scale_cfg, 0, sizeof(*scale_cfg));
-	memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext));
-
 	scale_cfg->phase_step_x[DPU_SSPP_COMP_0] =
 		mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);
 	scale_cfg->phase_step_y[DPU_SSPP_COMP_0] =
@@ -588,9 +586,9 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
 			scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
 		}
 
-		pstate->pixel_ext.num_ext_pxls_top[i] =
+		pixel_ext->num_ext_pxls_top[i] =
 			scale_cfg->src_height[i];
-		pstate->pixel_ext.num_ext_pxls_left[i] =
+		pixel_ext->num_ext_pxls_left[i] =
 			scale_cfg->src_width[i];
 	}
 	if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
@@ -660,6 +658,11 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
 		struct dpu_hw_pipe_cfg *pipe_cfg)
 {
 	const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
+	struct dpu_hw_scaler3_cfg scaler3_cfg;
+	struct dpu_hw_pixel_ext pixel_ext;
+
+	memset(&scaler3_cfg, 0, sizeof(scaler3_cfg));
+	memset(&pixel_ext, 0, sizeof(pixel_ext));
 
 	/* don't chroma subsample if decimating */
 	/* update scaler. calculate default config for QSEED3 */
@@ -668,8 +671,23 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
 			drm_rect_height(&pipe_cfg->src_rect),
 			drm_rect_width(&pipe_cfg->dst_rect),
 			drm_rect_height(&pipe_cfg->dst_rect),
-			&pstate->scaler3_cfg, fmt,
+			&scaler3_cfg, &pixel_ext, fmt,
 			info->hsub, info->vsub);
+
+	if (pdpu->pipe_hw->ops.setup_pe)
+		pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
+				&pixel_ext);
+
+	/**
+	 * when programmed in multirect mode, scalar block will be
+	 * bypassed. Still we need to update alpha and bitwidth
+	 * ONLY for RECT0
+	 */
+	if (pdpu->pipe_hw->ops.setup_scaler &&
+			pstate->multirect_index != DPU_SSPP_RECT_1)
+		pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
+				pipe_cfg, &pixel_ext,
+				&scaler3_cfg);
 }
 
 /**
@@ -710,7 +728,6 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
 			drm_rect_width(&pipe_cfg.dst_rect);
 		pipe_cfg.src_rect.y2 =
 			drm_rect_height(&pipe_cfg.dst_rect);
-		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
 
 		if (pdpu->pipe_hw->ops.setup_format)
 			pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
@@ -722,15 +739,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
 					&pipe_cfg,
 					pstate->multirect_index);
 
-		if (pdpu->pipe_hw->ops.setup_pe)
-			pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
-					&pstate->pixel_ext);
-
-		if (pdpu->pipe_hw->ops.setup_scaler &&
-				pstate->multirect_index != DPU_SSPP_RECT_1)
-			pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
-					&pipe_cfg, &pstate->pixel_ext,
-					&pstate->scaler3_cfg);
+		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
 	}
 
 	return 0;
@@ -1122,8 +1131,6 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 
 	pipe_cfg.dst_rect = state->dst;
 
-	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
-
 	/* override for color fill */
 	if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
 		/* skip remaining processing on color fill */
@@ -1136,21 +1143,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 				pstate->multirect_index);
 	}
 
-	if (pdpu->pipe_hw->ops.setup_pe &&
-			(pstate->multirect_index != DPU_SSPP_RECT_1))
-		pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
-				&pstate->pixel_ext);
-
-	/**
-	 * when programmed in multirect mode, scalar block will be
-	 * bypassed. Still we need to update alpha and bitwidth
-	 * ONLY for RECT0
-	 */
-	if (pdpu->pipe_hw->ops.setup_scaler &&
-			pstate->multirect_index != DPU_SSPP_RECT_1)
-		pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
-				&pipe_cfg, &pstate->pixel_ext,
-				&pstate->scaler3_cfg);
+	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
 
 	if (pdpu->pipe_hw->ops.setup_multirect)
 		pdpu->pipe_hw->ops.setup_multirect(
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 34e03ac05f4a..087194be3c22 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -23,8 +23,6 @@
  * @multirect_index: index of the rectangle of SSPP
  * @multirect_mode: parallel or time multiplex multirect mode
  * @pending:	whether the current update is still pending
- * @scaler3_cfg: configuration data for scaler3
- * @pixel_ext: configuration data for pixel extensions
  * @cdp_cfg:	CDP configuration
  * @plane_fetch_bw: calculated BW per plane
  * @plane_clk: calculated clk per plane
@@ -38,10 +36,6 @@ struct dpu_plane_state {
 	uint32_t multirect_mode;
 	bool pending;
 
-	/* scaler configuration */
-	struct dpu_hw_scaler3_cfg scaler3_cfg;
-	struct dpu_hw_pixel_ext pixel_ext;
-
 	struct dpu_hw_pipe_cdp_cfg cdp_cfg;
 	u64 plane_fetch_bw;
 	u64 plane_clk;
-- 
2.33.0

Re: [Freedreno] [PATCH 06/11] drm/msm/dpu: drop scaler config from plane state

[abhinavk]

On 2021-09-30 06:59, Dmitry Baryshkov wrote:
> Scaler and pixel_ext configuration does not contain a long living 
> state,
> it is used only during plane update, so remove these two fiels from
fiels ---> fields
> dpu_plane_state and allocate them on stack.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

While addressing the bugs reported by the smatch tool, I saw that pe is 
not
being used at the moment.

412 static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx,
413 		struct dpu_hw_pipe_cfg *sspp,
414 		struct dpu_hw_pixel_ext *pe,
415 		void *scaler_cfg)
416 {
417 	u32 idx;
418 	struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
419
420 	(void)pe;
421 	if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp
422 		|| !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk)
423 		return;
424
425 	dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
426 			ctx->cap->sblk->scaler_blk.version,
427 			sspp->layout.format);
428 }

As part of this change, can you please drop this?

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 59 ++++++++++-------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |  6 ---
>  2 files changed, 26 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 5288b5b824f8..4259c4ecde9b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -542,14 +542,12 @@ static void _dpu_plane_setup_scaler3(struct
> dpu_plane *pdpu,
>  		struct dpu_plane_state *pstate,
>  		uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
>  		struct dpu_hw_scaler3_cfg *scale_cfg,
> +		struct dpu_hw_pixel_ext *pixel_ext,
>  		const struct dpu_format *fmt,
>  		uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
>  {
>  	uint32_t i;
> 
> -	memset(scale_cfg, 0, sizeof(*scale_cfg));
> -	memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext));
> -
>  	scale_cfg->phase_step_x[DPU_SSPP_COMP_0] =
>  		mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);
>  	scale_cfg->phase_step_y[DPU_SSPP_COMP_0] =
> @@ -588,9 +586,9 @@ static void _dpu_plane_setup_scaler3(struct 
> dpu_plane *pdpu,
>  			scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
>  		}
> 
> -		pstate->pixel_ext.num_ext_pxls_top[i] =
> +		pixel_ext->num_ext_pxls_top[i] =
>  			scale_cfg->src_height[i];
> -		pstate->pixel_ext.num_ext_pxls_left[i] =
> +		pixel_ext->num_ext_pxls_left[i] =
>  			scale_cfg->src_width[i];
>  	}
>  	if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
> @@ -660,6 +658,11 @@ static void _dpu_plane_setup_scaler(struct 
> dpu_plane *pdpu,
>  		struct dpu_hw_pipe_cfg *pipe_cfg)
>  {
>  	const struct drm_format_info *info = 
> drm_format_info(fmt->base.pixel_format);
> +	struct dpu_hw_scaler3_cfg scaler3_cfg;
> +	struct dpu_hw_pixel_ext pixel_ext;
> +
> +	memset(&scaler3_cfg, 0, sizeof(scaler3_cfg));
> +	memset(&pixel_ext, 0, sizeof(pixel_ext));
> 
>  	/* don't chroma subsample if decimating */
>  	/* update scaler. calculate default config for QSEED3 */
> @@ -668,8 +671,23 @@ static void _dpu_plane_setup_scaler(struct 
> dpu_plane *pdpu,
>  			drm_rect_height(&pipe_cfg->src_rect),
>  			drm_rect_width(&pipe_cfg->dst_rect),
>  			drm_rect_height(&pipe_cfg->dst_rect),
> -			&pstate->scaler3_cfg, fmt,
> +			&scaler3_cfg, &pixel_ext, fmt,
>  			info->hsub, info->vsub);
> +
> +	if (pdpu->pipe_hw->ops.setup_pe)
> +		pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
> +				&pixel_ext);
> +
> +	/**
> +	 * when programmed in multirect mode, scalar block will be
> +	 * bypassed. Still we need to update alpha and bitwidth
> +	 * ONLY for RECT0
> +	 */
> +	if (pdpu->pipe_hw->ops.setup_scaler &&
> +			pstate->multirect_index != DPU_SSPP_RECT_1)
> +		pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
> +				pipe_cfg, &pixel_ext,
> +				&scaler3_cfg);
>  }
> 
>  /**
> @@ -710,7 +728,6 @@ static int _dpu_plane_color_fill(struct dpu_plane 
> *pdpu,
>  			drm_rect_width(&pipe_cfg.dst_rect);
>  		pipe_cfg.src_rect.y2 =
>  			drm_rect_height(&pipe_cfg.dst_rect);
> -		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
> 
>  		if (pdpu->pipe_hw->ops.setup_format)
>  			pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
> @@ -722,15 +739,7 @@ static int _dpu_plane_color_fill(struct dpu_plane 
> *pdpu,
>  					&pipe_cfg,
>  					pstate->multirect_index);
> 
> -		if (pdpu->pipe_hw->ops.setup_pe)
> -			pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
> -					&pstate->pixel_ext);
> -
> -		if (pdpu->pipe_hw->ops.setup_scaler &&
> -				pstate->multirect_index != DPU_SSPP_RECT_1)
> -			pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
> -					&pipe_cfg, &pstate->pixel_ext,
> -					&pstate->scaler3_cfg);
> +		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);
>  	}
> 
>  	return 0;
> @@ -1122,8 +1131,6 @@ static void dpu_plane_sspp_atomic_update(struct
> drm_plane *plane)
> 
>  	pipe_cfg.dst_rect = state->dst;
> 
> -	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
> -
>  	/* override for color fill */
>  	if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
>  		/* skip remaining processing on color fill */
> @@ -1136,21 +1143,7 @@ static void dpu_plane_sspp_atomic_update(struct
> drm_plane *plane)
>  				pstate->multirect_index);
>  	}
> 
> -	if (pdpu->pipe_hw->ops.setup_pe &&
> -			(pstate->multirect_index != DPU_SSPP_RECT_1))
> -		pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,
> -				&pstate->pixel_ext);
> -
> -	/**
> -	 * when programmed in multirect mode, scalar block will be
> -	 * bypassed. Still we need to update alpha and bitwidth
> -	 * ONLY for RECT0
> -	 */
> -	if (pdpu->pipe_hw->ops.setup_scaler &&
> -			pstate->multirect_index != DPU_SSPP_RECT_1)
> -		pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,
> -				&pipe_cfg, &pstate->pixel_ext,
> -				&pstate->scaler3_cfg);
> +	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);
> 
>  	if (pdpu->pipe_hw->ops.setup_multirect)
>  		pdpu->pipe_hw->ops.setup_multirect(
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> index 34e03ac05f4a..087194be3c22 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -23,8 +23,6 @@
>   * @multirect_index: index of the rectangle of SSPP
>   * @multirect_mode: parallel or time multiplex multirect mode
>   * @pending:	whether the current update is still pending
> - * @scaler3_cfg: configuration data for scaler3
> - * @pixel_ext: configuration data for pixel extensions
>   * @cdp_cfg:	CDP configuration
>   * @plane_fetch_bw: calculated BW per plane
>   * @plane_clk: calculated clk per plane
> @@ -38,10 +36,6 @@ struct dpu_plane_state {
>  	uint32_t multirect_mode;
>  	bool pending;
> 
> -	/* scaler configuration */
> -	struct dpu_hw_scaler3_cfg scaler3_cfg;
> -	struct dpu_hw_pixel_ext pixel_ext;
> -
>  	struct dpu_hw_pipe_cdp_cfg cdp_cfg;
>  	u64 plane_fetch_bw;
>  	u64 plane_clk;

[PATCH 07/11] drm/msm/dpu: drop dpu_csc_cfg from dpu_plane

[Dmitry Baryshkov]

Simplify code surrounding CSC table setup by removing struct dpu_csc_cfg
pointer from dpu_plane and getting it directly at the CSC setup time.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   | 96 +++++++++++----------
 5 files changed, 54 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index cbafb61404d0..103d4bd7585b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -537,7 +537,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx,
 }
 
 static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
-		struct dpu_csc_cfg *data)
+		const struct dpu_csc_cfg *data)
 {
 	u32 idx;
 	bool csc10 = false;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 27263bc1a1ef..e8939d7387cb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -262,7 +262,7 @@ struct dpu_hw_sspp_ops {
 	 * @ctx: Pointer to pipe context
 	 * @data: Pointer to config structure
 	 */
-	void (*setup_csc)(struct dpu_hw_pipe *ctx, struct dpu_csc_cfg *data);
+	void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct dpu_csc_cfg *data);
 
 	/**
 	 * setup_solidfill - enable/disable colorfill
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index f94584c982cd..aad85116b0a0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -374,7 +374,7 @@ u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,
 
 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
 		u32 csc_reg_off,
-		struct dpu_csc_cfg *data, bool csc10)
+		const struct dpu_csc_cfg *data, bool csc10)
 {
 	static const u32 matrix_shift = 7;
 	u32 clamp_shift = csc10 ? 16 : 8;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index ff3cffde84cd..bc2fdb2b8f5f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -321,6 +321,6 @@ u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,
 
 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map  *c,
 		u32 csc_reg_off,
-		struct dpu_csc_cfg *data, bool csc10);
+		const struct dpu_csc_cfg *data, bool csc10);
 
 #endif /* _DPU_HW_UTIL_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 4259c4ecde9b..b8836c089863 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -90,7 +90,6 @@ enum dpu_plane_qos {
 /*
  * struct dpu_plane - local dpu plane structure
  * @aspace: address space pointer
- * @csc_ptr: Points to dpu_csc_cfg structure to use for current
  * @mplane_list: List of multirect planes of the same pipe
  * @catalog: Points to dpu catalog structure
  * @revalidate: force revalidation of all the plane properties
@@ -111,8 +110,6 @@ struct dpu_plane {
 	struct list_head mplane_list;
 	struct dpu_mdss_cfg *catalog;
 
-	struct dpu_csc_cfg *csc_ptr;
-
 	const struct dpu_sspp_sub_blks *pipe_sblk;
 
 	/* debugfs related stuff */
@@ -605,51 +602,59 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu,
 	scale_cfg->enable = 1;
 }
 
-static void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
-{
-	static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
-		{
-			/* S15.16 format */
-			0x00012A00, 0x00000000, 0x00019880,
-			0x00012A00, 0xFFFF9B80, 0xFFFF3000,
-			0x00012A00, 0x00020480, 0x00000000,
+static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
+	{
+		/* S15.16 format */
+		0x00012A00, 0x00000000, 0x00019880,
+		0x00012A00, 0xFFFF9B80, 0xFFFF3000,
+		0x00012A00, 0x00020480, 0x00000000,
+	},
+	/* signed bias */
+	{ 0xfff0, 0xff80, 0xff80,},
+	{ 0x0, 0x0, 0x0,},
+	/* unsigned clamp */
+	{ 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
+	{ 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
+};
+
+static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
+	{
+		/* S15.16 format */
+		0x00012A00, 0x00000000, 0x00019880,
+		0x00012A00, 0xFFFF9B80, 0xFFFF3000,
+		0x00012A00, 0x00020480, 0x00000000,
 		},
-		/* signed bias */
-		{ 0xfff0, 0xff80, 0xff80,},
-		{ 0x0, 0x0, 0x0,},
-		/* unsigned clamp */
-		{ 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
-		{ 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
-	};
-	static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
-		{
-			/* S15.16 format */
-			0x00012A00, 0x00000000, 0x00019880,
-			0x00012A00, 0xFFFF9B80, 0xFFFF3000,
-			0x00012A00, 0x00020480, 0x00000000,
-			},
-		/* signed bias */
-		{ 0xffc0, 0xfe00, 0xfe00,},
-		{ 0x0, 0x0, 0x0,},
-		/* unsigned clamp */
-		{ 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
-		{ 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
-	};
+	/* signed bias */
+	{ 0xffc0, 0xfe00, 0xfe00,},
+	{ 0x0, 0x0, 0x0,},
+	/* unsigned clamp */
+	{ 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
+	{ 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
+};
+
+static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt)
+{
+	const struct dpu_csc_cfg *csc_ptr;
 
 	if (!pdpu) {
 		DPU_ERROR("invalid plane\n");
-		return;
+		return NULL;
 	}
 
+	if (!DPU_FORMAT_IS_YUV(fmt))
+		return NULL;
+
 	if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features)
-		pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L;
+		csc_ptr = &dpu_csc10_YUV2RGB_601L;
 	else
-		pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L;
+		csc_ptr = &dpu_csc_YUV2RGB_601L;
 
 	DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
-			pdpu->csc_ptr->csc_mv[0],
-			pdpu->csc_ptr->csc_mv[1],
-			pdpu->csc_ptr->csc_mv[2]);
+			csc_ptr->csc_mv[0],
+			csc_ptr->csc_mv[1],
+			csc_ptr->csc_mv[2]);
+
+	return csc_ptr;
 }
 
 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
@@ -1070,8 +1075,13 @@ void dpu_plane_flush(struct drm_plane *plane)
 	else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
 		/* force 100% alpha */
 		_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
-	else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc)
-		pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr);
+	else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) {
+		const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb));
+		const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);
+
+		if (csc_ptr)
+			pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr);
+	}
 
 	/* flag h/w flush complete */
 	if (plane->state)
@@ -1187,12 +1197,6 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 
 			pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
 		}
-
-		/* update csc */
-		if (DPU_FORMAT_IS_YUV(fmt))
-			_dpu_plane_setup_csc(pdpu);
-		else
-			pdpu->csc_ptr = 0;
 	}
 
 	_dpu_plane_set_qos_lut(plane, fb, &pipe_cfg);
-- 
2.33.0

Re: [Freedreno] [PATCH 07/11] drm/msm/dpu: drop dpu_csc_cfg from dpu_plane

[abhinavk]

On 2021-09-30 06:59, Dmitry Baryshkov wrote:
> Simplify code surrounding CSC table setup by removing struct 
> dpu_csc_cfg
> pointer from dpu_plane and getting it directly at the CSC setup time.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c |  2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h |  2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c |  2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h |  2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   | 96 +++++++++++----------
>  5 files changed, 54 insertions(+), 50 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index cbafb61404d0..103d4bd7585b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -537,7 +537,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct
> dpu_hw_pipe *ctx,
>  }
> 
>  static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx,
> -		struct dpu_csc_cfg *data)
> +		const struct dpu_csc_cfg *data)
>  {
>  	u32 idx;
>  	bool csc10 = false;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index 27263bc1a1ef..e8939d7387cb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -262,7 +262,7 @@ struct dpu_hw_sspp_ops {
>  	 * @ctx: Pointer to pipe context
>  	 * @data: Pointer to config structure
>  	 */
> -	void (*setup_csc)(struct dpu_hw_pipe *ctx, struct dpu_csc_cfg *data);
> +	void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct dpu_csc_cfg 
> *data);
> 
>  	/**
>  	 * setup_solidfill - enable/disable colorfill
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> index f94584c982cd..aad85116b0a0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> @@ -374,7 +374,7 @@ u32 dpu_hw_get_scaler3_ver(struct 
> dpu_hw_blk_reg_map *c,
> 
>  void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
>  		u32 csc_reg_off,
> -		struct dpu_csc_cfg *data, bool csc10)
> +		const struct dpu_csc_cfg *data, bool csc10)
>  {
>  	static const u32 matrix_shift = 7;
>  	u32 clamp_shift = csc10 ? 16 : 8;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> index ff3cffde84cd..bc2fdb2b8f5f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> @@ -321,6 +321,6 @@ u32 dpu_hw_get_scaler3_ver(struct 
> dpu_hw_blk_reg_map *c,
> 
>  void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map  *c,
>  		u32 csc_reg_off,
> -		struct dpu_csc_cfg *data, bool csc10);
> +		const struct dpu_csc_cfg *data, bool csc10);
> 
>  #endif /* _DPU_HW_UTIL_H */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 4259c4ecde9b..b8836c089863 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -90,7 +90,6 @@ enum dpu_plane_qos {
>  /*
>   * struct dpu_plane - local dpu plane structure
>   * @aspace: address space pointer
> - * @csc_ptr: Points to dpu_csc_cfg structure to use for current
>   * @mplane_list: List of multirect planes of the same pipe
>   * @catalog: Points to dpu catalog structure
>   * @revalidate: force revalidation of all the plane properties
> @@ -111,8 +110,6 @@ struct dpu_plane {
>  	struct list_head mplane_list;
>  	struct dpu_mdss_cfg *catalog;
> 
> -	struct dpu_csc_cfg *csc_ptr;
> -
>  	const struct dpu_sspp_sub_blks *pipe_sblk;
> 
>  	/* debugfs related stuff */
> @@ -605,51 +602,59 @@ static void _dpu_plane_setup_scaler3(struct
> dpu_plane *pdpu,
>  	scale_cfg->enable = 1;
>  }
> 
> -static void _dpu_plane_setup_csc(struct dpu_plane *pdpu)
> -{
> -	static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
> -		{
> -			/* S15.16 format */
> -			0x00012A00, 0x00000000, 0x00019880,
> -			0x00012A00, 0xFFFF9B80, 0xFFFF3000,
> -			0x00012A00, 0x00020480, 0x00000000,
> +static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {
> +	{
> +		/* S15.16 format */
> +		0x00012A00, 0x00000000, 0x00019880,
> +		0x00012A00, 0xFFFF9B80, 0xFFFF3000,
> +		0x00012A00, 0x00020480, 0x00000000,
> +	},
> +	/* signed bias */
> +	{ 0xfff0, 0xff80, 0xff80,},
> +	{ 0x0, 0x0, 0x0,},
> +	/* unsigned clamp */
> +	{ 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
> +	{ 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
> +};
> +
> +static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
> +	{
> +		/* S15.16 format */
> +		0x00012A00, 0x00000000, 0x00019880,
> +		0x00012A00, 0xFFFF9B80, 0xFFFF3000,
> +		0x00012A00, 0x00020480, 0x00000000,
>  		},
> -		/* signed bias */
> -		{ 0xfff0, 0xff80, 0xff80,},
> -		{ 0x0, 0x0, 0x0,},
> -		/* unsigned clamp */
> -		{ 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
> -		{ 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
> -	};
> -	static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
> -		{
> -			/* S15.16 format */
> -			0x00012A00, 0x00000000, 0x00019880,
> -			0x00012A00, 0xFFFF9B80, 0xFFFF3000,
> -			0x00012A00, 0x00020480, 0x00000000,
> -			},
> -		/* signed bias */
> -		{ 0xffc0, 0xfe00, 0xfe00,},
> -		{ 0x0, 0x0, 0x0,},
> -		/* unsigned clamp */
> -		{ 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
> -		{ 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
> -	};
> +	/* signed bias */
> +	{ 0xffc0, 0xfe00, 0xfe00,},
> +	{ 0x0, 0x0, 0x0,},
> +	/* unsigned clamp */
> +	{ 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
> +	{ 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
> +};
> +
> +static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane
> *pdpu, const struct dpu_format *fmt)
> +{
> +	const struct dpu_csc_cfg *csc_ptr;
> 
>  	if (!pdpu) {
>  		DPU_ERROR("invalid plane\n");
> -		return;
> +		return NULL;
>  	}
> 
> +	if (!DPU_FORMAT_IS_YUV(fmt))
> +		return NULL;
> +
>  	if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features)
> -		pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L;
> +		csc_ptr = &dpu_csc10_YUV2RGB_601L;
>  	else
> -		pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L;
> +		csc_ptr = &dpu_csc_YUV2RGB_601L;
> 
>  	DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
> -			pdpu->csc_ptr->csc_mv[0],
> -			pdpu->csc_ptr->csc_mv[1],
> -			pdpu->csc_ptr->csc_mv[2]);
> +			csc_ptr->csc_mv[0],
> +			csc_ptr->csc_mv[1],
> +			csc_ptr->csc_mv[2]);
> +
> +	return csc_ptr;
>  }
> 
>  static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
> @@ -1070,8 +1075,13 @@ void dpu_plane_flush(struct drm_plane *plane)
>  	else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
>  		/* force 100% alpha */
>  		_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
> -	else if (pdpu->pipe_hw && pdpu->csc_ptr && 
> pdpu->pipe_hw->ops.setup_csc)
> -		pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr);
> +	else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) {
> +		const struct dpu_format *fmt =
> to_dpu_format(msm_framebuffer_format(plane->state->fb));
> +		const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt);
> +
> +		if (csc_ptr)
> +			pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr);
> +	}
> 
>  	/* flag h/w flush complete */
>  	if (plane->state)
> @@ -1187,12 +1197,6 @@ static void dpu_plane_sspp_atomic_update(struct
> drm_plane *plane)
> 
>  			pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
>  		}
> -
> -		/* update csc */
> -		if (DPU_FORMAT_IS_YUV(fmt))
> -			_dpu_plane_setup_csc(pdpu);
> -		else
> -			pdpu->csc_ptr = 0;
>  	}
> 
>  	_dpu_plane_set_qos_lut(plane, fb, &pipe_cfg);

[PATCH 08/11] drm/msm/dpu: remove dpu_hw_pipe_cdp_cfg from dpu_plane

[Dmitry Baryshkov]

Remove struct dpu_hw_pipe_cdp_cfg instance from dpu_plane, it is an
interim configuration structure. Allocate it on stack instead.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 14 +++++++-------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |  2 --
 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index b8836c089863..d3ae0cb2047c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1182,20 +1182,20 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
 				pstate->multirect_index);
 
 		if (pdpu->pipe_hw->ops.setup_cdp) {
-			struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
+			struct dpu_hw_pipe_cdp_cfg cdp_cfg;
 
-			memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
+			memset(&cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
 
-			cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg
+			cdp_cfg.enable = pdpu->catalog->perf.cdp_cfg
 					[DPU_PERF_CDP_USAGE_RT].rd_enable;
-			cdp_cfg->ubwc_meta_enable =
+			cdp_cfg.ubwc_meta_enable =
 					DPU_FORMAT_IS_UBWC(fmt);
-			cdp_cfg->tile_amortize_enable =
+			cdp_cfg.tile_amortize_enable =
 					DPU_FORMAT_IS_UBWC(fmt) ||
 					DPU_FORMAT_IS_TILE(fmt);
-			cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
+			cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
 
-			pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
+			pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg);
 		}
 	}
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 087194be3c22..1ee5ca5fcdf7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -23,7 +23,6 @@
  * @multirect_index: index of the rectangle of SSPP
  * @multirect_mode: parallel or time multiplex multirect mode
  * @pending:	whether the current update is still pending
- * @cdp_cfg:	CDP configuration
  * @plane_fetch_bw: calculated BW per plane
  * @plane_clk: calculated clk per plane
  */
@@ -36,7 +35,6 @@ struct dpu_plane_state {
 	uint32_t multirect_mode;
 	bool pending;
 
-	struct dpu_hw_pipe_cdp_cfg cdp_cfg;
 	u64 plane_fetch_bw;
 	u64 plane_clk;
 };
-- 
2.33.0

Re: [Freedreno] [PATCH 08/11] drm/msm/dpu: remove dpu_hw_pipe_cdp_cfg from dpu_plane

[abhinavk]

On 2021-09-30 06:59, Dmitry Baryshkov wrote:
> Remove struct dpu_hw_pipe_cdp_cfg instance from dpu_plane, it is an
> interim configuration structure. Allocate it on stack instead.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 14 +++++++-------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |  2 --
>  2 files changed, 7 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index b8836c089863..d3ae0cb2047c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -1182,20 +1182,20 @@ static void
> dpu_plane_sspp_atomic_update(struct drm_plane *plane)
>  				pstate->multirect_index);
> 
>  		if (pdpu->pipe_hw->ops.setup_cdp) {
> -			struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
> +			struct dpu_hw_pipe_cdp_cfg cdp_cfg;
> 
> -			memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
> +			memset(&cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
> 
> -			cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg
> +			cdp_cfg.enable = pdpu->catalog->perf.cdp_cfg
>  					[DPU_PERF_CDP_USAGE_RT].rd_enable;
> -			cdp_cfg->ubwc_meta_enable =
> +			cdp_cfg.ubwc_meta_enable =
>  					DPU_FORMAT_IS_UBWC(fmt);
> -			cdp_cfg->tile_amortize_enable =
> +			cdp_cfg.tile_amortize_enable =
>  					DPU_FORMAT_IS_UBWC(fmt) ||
>  					DPU_FORMAT_IS_TILE(fmt);
> -			cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
> +			cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
> 
> -			pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
> +			pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg);
>  		}
>  	}
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> index 087194be3c22..1ee5ca5fcdf7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -23,7 +23,6 @@
>   * @multirect_index: index of the rectangle of SSPP
>   * @multirect_mode: parallel or time multiplex multirect mode
>   * @pending:	whether the current update is still pending
> - * @cdp_cfg:	CDP configuration
>   * @plane_fetch_bw: calculated BW per plane
>   * @plane_clk: calculated clk per plane
>   */
> @@ -36,7 +35,6 @@ struct dpu_plane_state {
>  	uint32_t multirect_mode;
>  	bool pending;
> 
> -	struct dpu_hw_pipe_cdp_cfg cdp_cfg;
>  	u64 plane_fetch_bw;
>  	u64 plane_clk;
>  };

[PATCH 09/11] drm/msm/dpu: don't cache pipe->cap->features in dpu_plane

[Dmitry Baryshkov]

Do not cache hw_pipe's features in dpu_plane. Use
pdpu->pipe_hw->cap->features directly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index d3ae0cb2047c..af403c0d3d7d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -100,7 +100,6 @@ struct dpu_plane {
 	struct mutex lock;
 
 	enum dpu_sspp pipe;
-	uint32_t features;      /* capabilities from catalog */
 
 	struct dpu_hw_pipe *pipe_hw;
 	uint32_t color_fill;
@@ -644,7 +643,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons
 	if (!DPU_FORMAT_IS_YUV(fmt))
 		return NULL;
 
-	if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features)
+	if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features)
 		csc_ptr = &dpu_csc10_YUV2RGB_601L;
 	else
 		csc_ptr = &dpu_csc_YUV2RGB_601L;
@@ -1012,8 +1011,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
 	min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
 
 	if (DPU_FORMAT_IS_YUV(fmt) &&
-		(!(pdpu->features & DPU_SSPP_SCALER) ||
-		 !(pdpu->features & (BIT(DPU_SSPP_CSC)
+		(!(pdpu->pipe_hw->cap->features & DPU_SSPP_SCALER) ||
+		 !(pdpu->pipe_hw->cap->features & (BIT(DPU_SSPP_CSC)
 		 | BIT(DPU_SSPP_CSC_10BIT))))) {
 		DPU_DEBUG_PLANE(pdpu,
 				"plane doesn't have scaler/csc for yuv\n");
@@ -1439,8 +1438,8 @@ static int _dpu_plane_init_debugfs(struct drm_plane *plane)
 				plane->dev->primary->debugfs_root);
 
 	/* don't error check these */
-	debugfs_create_x32("features", 0600,
-			pdpu->debugfs_root, &pdpu->features);
+	debugfs_create_xul("features", 0600,
+			pdpu->debugfs_root, (unsigned long *)&pdpu->pipe_hw->cap->features);
 
 	/* add register dump support */
 	dpu_debugfs_setup_regset32(&pdpu->debugfs_src,
@@ -1613,7 +1612,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
 	}
 
 	/* cache features mask for later */
-	pdpu->features = pdpu->pipe_hw->cap->features;
 	pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk;
 	if (!pdpu->pipe_sblk) {
 		DPU_ERROR("[%u]invalid sblk\n", pipe);
-- 
2.33.0

Re: [Freedreno] [PATCH 09/11] drm/msm/dpu: don't cache pipe->cap->features in dpu_plane

[abhinavk]

On 2021-09-30 07:00, Dmitry Baryshkov wrote:
> Do not cache hw_pipe's features in dpu_plane. Use
> pdpu->pipe_hw->cap->features directly.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index d3ae0cb2047c..af403c0d3d7d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -100,7 +100,6 @@ struct dpu_plane {
>  	struct mutex lock;
> 
>  	enum dpu_sspp pipe;
> -	uint32_t features;      /* capabilities from catalog */
> 
>  	struct dpu_hw_pipe *pipe_hw;
>  	uint32_t color_fill;
> @@ -644,7 +643,7 @@ static const struct dpu_csc_cfg
> *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons
>  	if (!DPU_FORMAT_IS_YUV(fmt))
>  		return NULL;
> 
> -	if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features)
> +	if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features)
>  		csc_ptr = &dpu_csc10_YUV2RGB_601L;
>  	else
>  		csc_ptr = &dpu_csc_YUV2RGB_601L;
> @@ -1012,8 +1011,8 @@ static int dpu_plane_atomic_check(struct 
> drm_plane *plane,
>  	min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
> 
>  	if (DPU_FORMAT_IS_YUV(fmt) &&
> -		(!(pdpu->features & DPU_SSPP_SCALER) ||
> -		 !(pdpu->features & (BIT(DPU_SSPP_CSC)
> +		(!(pdpu->pipe_hw->cap->features & DPU_SSPP_SCALER) ||
> +		 !(pdpu->pipe_hw->cap->features & (BIT(DPU_SSPP_CSC)
>  		 | BIT(DPU_SSPP_CSC_10BIT))))) {
>  		DPU_DEBUG_PLANE(pdpu,
>  				"plane doesn't have scaler/csc for yuv\n");
> @@ -1439,8 +1438,8 @@ static int _dpu_plane_init_debugfs(struct
> drm_plane *plane)
>  				plane->dev->primary->debugfs_root);
> 
>  	/* don't error check these */
> -	debugfs_create_x32("features", 0600,
> -			pdpu->debugfs_root, &pdpu->features);
> +	debugfs_create_xul("features", 0600,
> +			pdpu->debugfs_root, (unsigned long 
> *)&pdpu->pipe_hw->cap->features);
> 
>  	/* add register dump support */
>  	dpu_debugfs_setup_regset32(&pdpu->debugfs_src,
> @@ -1613,7 +1612,6 @@ struct drm_plane *dpu_plane_init(struct 
> drm_device *dev,
>  	}
> 
>  	/* cache features mask for later */
> -	pdpu->features = pdpu->pipe_hw->cap->features;
>  	pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk;
>  	if (!pdpu->pipe_sblk) {
>  		DPU_ERROR("[%u]invalid sblk\n", pipe);

[PATCH 10/11] drm/msm/dpu: don't cache pipe->cap->sblk in dpu_plane

[Dmitry Baryshkov]

Do not cache hw_pipe's sblk in dpu_plane. Use
pdpu->pipe_hw->cap->sblk directly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 25 ++++++++---------------
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index af403c0d3d7d..d8018e664925 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -109,8 +109,6 @@ struct dpu_plane {
 	struct list_head mplane_list;
 	struct dpu_mdss_cfg *catalog;
 
-	const struct dpu_sspp_sub_blks *pipe_sblk;
-
 	/* debugfs related stuff */
 	struct dentry *debugfs_root;
 	struct dpu_debugfs_regset32 debugfs_src;
@@ -425,9 +423,9 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
 	memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
 
 	if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
-		pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
+		pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank;
 		pipe_qos_cfg.danger_vblank =
-				pdpu->pipe_sblk->danger_vblank;
+				pdpu->pipe_hw->cap->sblk->danger_vblank;
 		pipe_qos_cfg.vblank_en = enable;
 	}
 
@@ -982,10 +980,10 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
 		crtc_state = drm_atomic_get_new_crtc_state(state,
 							   new_plane_state->crtc);
 
-	min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxupscale);
+	min_scale = FRAC_16_16(1, pdpu->pipe_hw->cap->sblk->maxupscale);
 	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
 						  min_scale,
-						  pdpu->pipe_sblk->maxdwnscale << 16,
+						  pdpu->pipe_hw->cap->sblk->maxdwnscale << 16,
 						  true, true);
 	if (ret) {
 		DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
@@ -1611,20 +1609,13 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
 		goto clean_sspp;
 	}
 
-	/* cache features mask for later */
-	pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk;
-	if (!pdpu->pipe_sblk) {
-		DPU_ERROR("[%u]invalid sblk\n", pipe);
-		goto clean_sspp;
-	}
-
 	if (pdpu->is_virtual) {
-		format_list = pdpu->pipe_sblk->virt_format_list;
-		num_formats = pdpu->pipe_sblk->virt_num_formats;
+		format_list = pdpu->pipe_hw->cap->sblk->virt_format_list;
+		num_formats = pdpu->pipe_hw->cap->sblk->virt_num_formats;
 	}
 	else {
-		format_list = pdpu->pipe_sblk->format_list;
-		num_formats = pdpu->pipe_sblk->num_formats;
+		format_list = pdpu->pipe_hw->cap->sblk->format_list;
+		num_formats = pdpu->pipe_hw->cap->sblk->num_formats;
 	}
 
 	ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,
-- 
2.33.0

Re: [Freedreno] [PATCH 10/11] drm/msm/dpu: don't cache pipe->cap->sblk in dpu_plane

[abhinavk]

On 2021-09-30 07:00, Dmitry Baryshkov wrote:
> Do not cache hw_pipe's sblk in dpu_plane. Use
> pdpu->pipe_hw->cap->sblk directly.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 25 ++++++++---------------
>  1 file changed, 8 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index af403c0d3d7d..d8018e664925 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -109,8 +109,6 @@ struct dpu_plane {
>  	struct list_head mplane_list;
>  	struct dpu_mdss_cfg *catalog;
> 
> -	const struct dpu_sspp_sub_blks *pipe_sblk;
> -
>  	/* debugfs related stuff */
>  	struct dentry *debugfs_root;
>  	struct dpu_debugfs_regset32 debugfs_src;
> @@ -425,9 +423,9 @@ static void _dpu_plane_set_qos_ctrl(struct 
> drm_plane *plane,
>  	memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg));
> 
>  	if (flags & DPU_PLANE_QOS_VBLANK_CTRL) {
> -		pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank;
> +		pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank;
>  		pipe_qos_cfg.danger_vblank =
> -				pdpu->pipe_sblk->danger_vblank;
> +				pdpu->pipe_hw->cap->sblk->danger_vblank;
>  		pipe_qos_cfg.vblank_en = enable;
>  	}
> 
> @@ -982,10 +980,10 @@ static int dpu_plane_atomic_check(struct 
> drm_plane *plane,
>  		crtc_state = drm_atomic_get_new_crtc_state(state,
>  							   new_plane_state->crtc);
> 
> -	min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxupscale);
> +	min_scale = FRAC_16_16(1, pdpu->pipe_hw->cap->sblk->maxupscale);
>  	ret = drm_atomic_helper_check_plane_state(new_plane_state, 
> crtc_state,
>  						  min_scale,
> -						  pdpu->pipe_sblk->maxdwnscale << 16,
> +						  pdpu->pipe_hw->cap->sblk->maxdwnscale << 16,
>  						  true, true);
>  	if (ret) {
>  		DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
> @@ -1611,20 +1609,13 @@ struct drm_plane *dpu_plane_init(struct 
> drm_device *dev,
>  		goto clean_sspp;
>  	}
> 
> -	/* cache features mask for later */
> -	pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk;
> -	if (!pdpu->pipe_sblk) {
> -		DPU_ERROR("[%u]invalid sblk\n", pipe);
> -		goto clean_sspp;
> -	}
> -
>  	if (pdpu->is_virtual) {
> -		format_list = pdpu->pipe_sblk->virt_format_list;
> -		num_formats = pdpu->pipe_sblk->virt_num_formats;
> +		format_list = pdpu->pipe_hw->cap->sblk->virt_format_list;
> +		num_formats = pdpu->pipe_hw->cap->sblk->virt_num_formats;
>  	}
>  	else {
> -		format_list = pdpu->pipe_sblk->format_list;
> -		num_formats = pdpu->pipe_sblk->num_formats;
> +		format_list = pdpu->pipe_hw->cap->sblk->format_list;
> +		num_formats = pdpu->pipe_hw->cap->sblk->num_formats;
>  	}
> 
>  	ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs,

[PATCH 11/11] drm/msm/dpu: rip out debugfs support from dpu_plane

[Dmitry Baryshkov]

In preparations of virtualizing the dpu_plane rip out debugfs support
from dpu_plane (as it is mostly used to expose plane's pipe registers).
Also move disable_danger file to danger/ debugfs subdir where it belongs.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   | 123 ++++++++--------
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h   |  69 ---------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 171 +---------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |   6 +
 4 files changed, 69 insertions(+), 300 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ae48f41821cf..fe33273cdf57 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -101,84 +101,85 @@ static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v)
 }
 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats);
 
-static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
-		struct dentry *parent)
+static ssize_t _dpu_plane_danger_read(struct file *file,
+			char __user *buff, size_t count, loff_t *ppos)
 {
-	struct dentry *entry = debugfs_create_dir("danger", parent);
+	struct dpu_kms *kms = file->private_data;
+	int len;
+	char buf[40];
 
-	debugfs_create_file("danger_status", 0600, entry,
-			dpu_kms, &dpu_debugfs_danger_stats_fops);
-	debugfs_create_file("safe_status", 0600, entry,
-			dpu_kms, &dpu_debugfs_safe_stats_fops);
+	len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
+
+	return simple_read_from_buffer(buff, count, ppos, buf, len);
 }
 
-static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
+static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)
 {
-	struct dpu_debugfs_regset32 *regset = s->private;
-	struct dpu_kms *dpu_kms = regset->dpu_kms;
-	void __iomem *base;
-	uint32_t i, addr;
-
-	if (!dpu_kms->mmio)
-		return 0;
-
-	base = dpu_kms->mmio + regset->offset;
-
-	/* insert padding spaces, if needed */
-	if (regset->offset & 0xF) {
-		seq_printf(s, "[%x]", regset->offset & ~0xF);
-		for (i = 0; i < (regset->offset & 0xF); i += 4)
-			seq_puts(s, "         ");
-	}
-
-	pm_runtime_get_sync(&dpu_kms->pdev->dev);
-
-	/* main register output */
-	for (i = 0; i < regset->blk_len; i += 4) {
-		addr = regset->offset + i;
-		if ((addr & 0xF) == 0x0)
-			seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
-		seq_printf(s, " %08x", readl_relaxed(base + i));
+	struct drm_plane *plane;
+
+	drm_for_each_plane(plane, kms->dev) {
+		if (plane->fb && plane->state) {
+			dpu_plane_danger_signal_ctrl(plane, enable);
+			DPU_DEBUG("plane:%d img:%dx%d ",
+				plane->base.id, plane->fb->width,
+				plane->fb->height);
+			DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
+				plane->state->src_x >> 16,
+				plane->state->src_y >> 16,
+				plane->state->src_w >> 16,
+				plane->state->src_h >> 16,
+				plane->state->crtc_x, plane->state->crtc_y,
+				plane->state->crtc_w, plane->state->crtc_h);
+		} else {
+			DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
+		}
 	}
-	seq_puts(s, "\n");
-	pm_runtime_put_sync(&dpu_kms->pdev->dev);
-
-	return 0;
 }
 
-static int dpu_debugfs_open_regset32(struct inode *inode,
-		struct file *file)
+static ssize_t _dpu_plane_danger_write(struct file *file,
+		    const char __user *user_buf, size_t count, loff_t *ppos)
 {
-	return single_open(file, _dpu_debugfs_show_regset32, inode->i_private);
-}
+	struct dpu_kms *kms = file->private_data;
+	int disable_panic;
+	int ret;
 
-static const struct file_operations dpu_fops_regset32 = {
-	.open =		dpu_debugfs_open_regset32,
-	.read =		seq_read,
-	.llseek =	seq_lseek,
-	.release =	single_release,
-};
+	ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
+	if (ret)
+		return ret;
 
-void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset,
-		uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)
-{
-	if (regset) {
-		regset->offset = offset;
-		regset->blk_len = length;
-		regset->dpu_kms = dpu_kms;
+	if (disable_panic) {
+		/* Disable panic signal for all active pipes */
+		DPU_DEBUG("Disabling danger:\n");
+		_dpu_plane_set_danger_state(kms, false);
+		kms->has_danger_ctrl = false;
+	} else {
+		/* Enable panic signal for all active pipes */
+		DPU_DEBUG("Enabling danger:\n");
+		kms->has_danger_ctrl = true;
+		_dpu_plane_set_danger_state(kms, true);
 	}
+
+	return count;
 }
 
-void dpu_debugfs_create_regset32(const char *name, umode_t mode,
-		void *parent, struct dpu_debugfs_regset32 *regset)
+static const struct file_operations dpu_plane_danger_enable = {
+	.open = simple_open,
+	.read = _dpu_plane_danger_read,
+	.write = _dpu_plane_danger_write,
+};
+
+static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
+		struct dentry *parent)
 {
-	if (!name || !regset || !regset->dpu_kms || !regset->blk_len)
-		return;
+	struct dentry *entry = debugfs_create_dir("danger", parent);
 
-	/* make sure offset is a multiple of 4 */
-	regset->offset = round_down(regset->offset, 4);
+	debugfs_create_file("danger_status", 0600, entry,
+			dpu_kms, &dpu_debugfs_danger_stats_fops);
+	debugfs_create_file("safe_status", 0600, entry,
+			dpu_kms, &dpu_debugfs_safe_stats_fops);
+	debugfs_create_file("disable_danger", 0600, entry,
+			dpu_kms, &dpu_plane_danger_enable);
 
-	debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32);
 }
 
 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index 323a6bce9e64..ab65c817eb42 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -166,75 +166,6 @@ struct dpu_global_state
 struct dpu_global_state
 	*__must_check dpu_kms_get_global_state(struct drm_atomic_state *s);
 
-/**
- * Debugfs functions - extra helper functions for debugfs support
- *
- * Main debugfs documentation is located at,
- *
- * Documentation/filesystems/debugfs.rst
- *
- * @dpu_debugfs_setup_regset32: Initialize data for dpu_debugfs_create_regset32
- * @dpu_debugfs_create_regset32: Create 32-bit register dump file
- * @dpu_debugfs_get_root: Get root dentry for DPU_KMS's debugfs node
- */
-
-/**
- * Companion structure for dpu_debugfs_create_regset32. Do not initialize the
- * members of this structure explicitly; use dpu_debugfs_setup_regset32 instead.
- */
-struct dpu_debugfs_regset32 {
-	uint32_t offset;
-	uint32_t blk_len;
-	struct dpu_kms *dpu_kms;
-};
-
-/**
- * dpu_debugfs_setup_regset32 - Initialize register block definition for debugfs
- * This function is meant to initialize dpu_debugfs_regset32 structures for use
- * with dpu_debugfs_create_regset32.
- * @regset: opaque register definition structure
- * @offset: sub-block offset
- * @length: sub-block length, in bytes
- * @dpu_kms: pointer to dpu kms structure
- */
-void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset,
-		uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms);
-
-/**
- * dpu_debugfs_create_regset32 - Create register read back file for debugfs
- *
- * This function is almost identical to the standard debugfs_create_regset32()
- * function, with the main difference being that a list of register
- * names/offsets do not need to be provided. The 'read' function simply outputs
- * sequential register values over a specified range.
- *
- * Similar to the related debugfs_create_regset32 API, the structure pointed to
- * by regset needs to persist for the lifetime of the created file. The calling
- * code is responsible for initialization/management of this structure.
- *
- * The structure pointed to by regset is meant to be opaque. Please use
- * dpu_debugfs_setup_regset32 to initialize it.
- *
- * @name:   File name within debugfs
- * @mode:   File mode within debugfs
- * @parent: Parent directory entry within debugfs, can be NULL
- * @regset: Pointer to persistent register block definition
- */
-void dpu_debugfs_create_regset32(const char *name, umode_t mode,
-		void *parent, struct dpu_debugfs_regset32 *regset);
-
-/**
- * dpu_debugfs_get_root - Return root directory entry for KMS's debugfs
- *
- * The return value should be passed as the 'parent' argument to subsequent
- * debugfs create calls.
- *
- * @dpu_kms: Pointer to DPU's KMS structure
- *
- * Return: dentry pointer for DPU's debugfs location
- */
-void *dpu_debugfs_get_root(struct dpu_kms *dpu_kms);
-
 /**
  * DPU info management functions
  * These functions/definitions allow for building up a 'dpu_info' structure
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index d8018e664925..42bcde1ddd0f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -108,13 +108,6 @@ struct dpu_plane {
 	bool is_virtual;
 	struct list_head mplane_list;
 	struct dpu_mdss_cfg *catalog;
-
-	/* debugfs related stuff */
-	struct dentry *debugfs_root;
-	struct dpu_debugfs_regset32 debugfs_src;
-	struct dpu_debugfs_regset32 debugfs_scaler;
-	struct dpu_debugfs_regset32 debugfs_csc;
-	bool debugfs_default_scale;
 };
 
 static const uint64_t supported_format_modifiers[] = {
@@ -1343,7 +1336,7 @@ static void dpu_plane_reset(struct drm_plane *plane)
 }
 
 #ifdef CONFIG_DEBUG_FS
-static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
+void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
 {
 	struct dpu_plane *pdpu = to_dpu_plane(plane);
 	struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
@@ -1355,168 +1348,8 @@ static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
 	_dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
 }
-
-static ssize_t _dpu_plane_danger_read(struct file *file,
-			char __user *buff, size_t count, loff_t *ppos)
-{
-	struct dpu_kms *kms = file->private_data;
-	int len;
-	char buf[40];
-
-	len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
-
-	return simple_read_from_buffer(buff, count, ppos, buf, len);
-}
-
-static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)
-{
-	struct drm_plane *plane;
-
-	drm_for_each_plane(plane, kms->dev) {
-		if (plane->fb && plane->state) {
-			dpu_plane_danger_signal_ctrl(plane, enable);
-			DPU_DEBUG("plane:%d img:%dx%d ",
-				plane->base.id, plane->fb->width,
-				plane->fb->height);
-			DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
-				plane->state->src_x >> 16,
-				plane->state->src_y >> 16,
-				plane->state->src_w >> 16,
-				plane->state->src_h >> 16,
-				plane->state->crtc_x, plane->state->crtc_y,
-				plane->state->crtc_w, plane->state->crtc_h);
-		} else {
-			DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
-		}
-	}
-}
-
-static ssize_t _dpu_plane_danger_write(struct file *file,
-		    const char __user *user_buf, size_t count, loff_t *ppos)
-{
-	struct dpu_kms *kms = file->private_data;
-	int disable_panic;
-	int ret;
-
-	ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
-	if (ret)
-		return ret;
-
-	if (disable_panic) {
-		/* Disable panic signal for all active pipes */
-		DPU_DEBUG("Disabling danger:\n");
-		_dpu_plane_set_danger_state(kms, false);
-		kms->has_danger_ctrl = false;
-	} else {
-		/* Enable panic signal for all active pipes */
-		DPU_DEBUG("Enabling danger:\n");
-		kms->has_danger_ctrl = true;
-		_dpu_plane_set_danger_state(kms, true);
-	}
-
-	return count;
-}
-
-static const struct file_operations dpu_plane_danger_enable = {
-	.open = simple_open,
-	.read = _dpu_plane_danger_read,
-	.write = _dpu_plane_danger_write,
-};
-
-static int _dpu_plane_init_debugfs(struct drm_plane *plane)
-{
-	struct dpu_plane *pdpu = to_dpu_plane(plane);
-	struct dpu_kms *kms = _dpu_plane_get_kms(plane);
-	const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap;
-	const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
-
-	/* create overall sub-directory for the pipe */
-	pdpu->debugfs_root =
-		debugfs_create_dir(plane->name,
-				plane->dev->primary->debugfs_root);
-
-	/* don't error check these */
-	debugfs_create_xul("features", 0600,
-			pdpu->debugfs_root, (unsigned long *)&pdpu->pipe_hw->cap->features);
-
-	/* add register dump support */
-	dpu_debugfs_setup_regset32(&pdpu->debugfs_src,
-			sblk->src_blk.base + cfg->base,
-			sblk->src_blk.len,
-			kms);
-	dpu_debugfs_create_regset32("src_blk", 0400,
-			pdpu->debugfs_root, &pdpu->debugfs_src);
-
-	if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
-			cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) ||
-			cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) ||
-			cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) {
-		dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler,
-				sblk->scaler_blk.base + cfg->base,
-				sblk->scaler_blk.len,
-				kms);
-		dpu_debugfs_create_regset32("scaler_blk", 0400,
-				pdpu->debugfs_root,
-				&pdpu->debugfs_scaler);
-		debugfs_create_bool("default_scaling",
-				0600,
-				pdpu->debugfs_root,
-				&pdpu->debugfs_default_scale);
-	}
-
-	if (cfg->features & BIT(DPU_SSPP_CSC) ||
-			cfg->features & BIT(DPU_SSPP_CSC_10BIT)) {
-		dpu_debugfs_setup_regset32(&pdpu->debugfs_csc,
-				sblk->csc_blk.base + cfg->base,
-				sblk->csc_blk.len,
-				kms);
-		dpu_debugfs_create_regset32("csc_blk", 0400,
-				pdpu->debugfs_root, &pdpu->debugfs_csc);
-	}
-
-	debugfs_create_u32("xin_id",
-			0400,
-			pdpu->debugfs_root,
-			(u32 *) &cfg->xin_id);
-	debugfs_create_u32("clk_ctrl",
-			0400,
-			pdpu->debugfs_root,
-			(u32 *) &cfg->clk_ctrl);
-	debugfs_create_x32("creq_vblank",
-			0600,
-			pdpu->debugfs_root,
-			(u32 *) &sblk->creq_vblank);
-	debugfs_create_x32("danger_vblank",
-			0600,
-			pdpu->debugfs_root,
-			(u32 *) &sblk->danger_vblank);
-
-	debugfs_create_file("disable_danger",
-			0600,
-			pdpu->debugfs_root,
-			kms, &dpu_plane_danger_enable);
-
-	return 0;
-}
-#else
-static int _dpu_plane_init_debugfs(struct drm_plane *plane)
-{
-	return 0;
-}
 #endif
 
-static int dpu_plane_late_register(struct drm_plane *plane)
-{
-	return _dpu_plane_init_debugfs(plane);
-}
-
-static void dpu_plane_early_unregister(struct drm_plane *plane)
-{
-	struct dpu_plane *pdpu = to_dpu_plane(plane);
-
-	debugfs_remove_recursive(pdpu->debugfs_root);
-}
-
 static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
 		uint32_t format, uint64_t modifier)
 {
@@ -1541,8 +1374,6 @@ static const struct drm_plane_funcs dpu_plane_funcs = {
 		.reset = dpu_plane_reset,
 		.atomic_duplicate_state = dpu_plane_duplicate_state,
 		.atomic_destroy_state = dpu_plane_destroy_state,
-		.late_register = dpu_plane_late_register,
-		.early_unregister = dpu_plane_early_unregister,
 		.format_mod_supported = dpu_plane_format_mod_supported,
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 1ee5ca5fcdf7..9d51dad5c6a5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -126,4 +126,10 @@ void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state);
 int dpu_plane_color_fill(struct drm_plane *plane,
 		uint32_t color, uint32_t alpha);
 
+#ifdef CONFIG_DEBUG_FS
+void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable);
+#else
+static inline void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) {}
+#endif
+
 #endif /* _DPU_PLANE_H_ */
-- 
2.33.0

Re: [Freedreno] [PATCH 11/11] drm/msm/dpu: rip out debugfs support from dpu_plane

[abhinavk]

On 2021-09-30 07:00, Dmitry Baryshkov wrote:
> In preparations of virtualizing the dpu_plane rip out debugfs support
> from dpu_plane (as it is mostly used to expose plane's pipe registers).
> Also move disable_danger file to danger/ debugfs subdir where it 
> belongs.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

I am yet to review the second part of the virtual plane series to 
understand why this removal
is necessary so I might be missing something.

The plane's debugfs holds useful information to check a few things 
rightaway.

So if there is some misconfiguration or corruption in addition to the 
plane state,
this is good to check.

localhost /sys/kernel/debug/dri/1/plane35 # cat src_blk
[4000] 03000556 00000000 00000000 03000556
[4010] 00000000 00414000 00000000 0040e000
[4020] 00000000 00001600 00000080 00000000
[4030] 800236ff 03010002 80000001 00000000
[4040] 00000000 00000030 000c0087 00000707
[4050] 00000000 00000000 00000000 00000000
[4060] 0000ffff 00000000 00000000 00000001
[4070] 00000000 44556677 00112233 00000000
[4080] 00000000 00000000 00000000 00000000
[4090] 00000000 00000000 00000000 00000000
[40a0] 00000000 00414000 00000000 0040e000
[40b0] 00000000 00000000 00000000 00000000
[40c0] 00000000 00000000 00000000 00000000
[40d0] 0003f820 00000000 00000000 00000000
[40e0] 0003e2c4 00000000 00000000 00000000
[40f0] 000f000f 00010330 02e402e4 00000000
[4100] 00000000 00000000 03000556 00000000
[4110] 00000000 00000000 03000556 00000000
[4120] 00000000 00000000 03000556 00000000
[4130] 00000000 0000000f 00000000 0000000f
[4140] 00000000 00000000 00000000 00000000

So I would like to keep this functionality unless there is some 
compelling reason
to remove this.

BTW, are you going to submit the second half as a new series now that 
most
of the first one has been reviewed?

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   | 123 ++++++++--------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h   |  69 ---------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 171 +---------------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |   6 +
>  4 files changed, 69 insertions(+), 300 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index ae48f41821cf..fe33273cdf57 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -101,84 +101,85 @@ static int dpu_debugfs_safe_stats_show(struct
> seq_file *s, void *v)
>  }
>  DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats);
> 
> -static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
> -		struct dentry *parent)
> +static ssize_t _dpu_plane_danger_read(struct file *file,
> +			char __user *buff, size_t count, loff_t *ppos)
>  {
> -	struct dentry *entry = debugfs_create_dir("danger", parent);
> +	struct dpu_kms *kms = file->private_data;
> +	int len;
> +	char buf[40];
> 
> -	debugfs_create_file("danger_status", 0600, entry,
> -			dpu_kms, &dpu_debugfs_danger_stats_fops);
> -	debugfs_create_file("safe_status", 0600, entry,
> -			dpu_kms, &dpu_debugfs_safe_stats_fops);
> +	len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
> +
> +	return simple_read_from_buffer(buff, count, ppos, buf, len);
>  }
> 
> -static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
> +static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool 
> enable)
>  {
> -	struct dpu_debugfs_regset32 *regset = s->private;
> -	struct dpu_kms *dpu_kms = regset->dpu_kms;
> -	void __iomem *base;
> -	uint32_t i, addr;
> -
> -	if (!dpu_kms->mmio)
> -		return 0;
> -
> -	base = dpu_kms->mmio + regset->offset;
> -
> -	/* insert padding spaces, if needed */
> -	if (regset->offset & 0xF) {
> -		seq_printf(s, "[%x]", regset->offset & ~0xF);
> -		for (i = 0; i < (regset->offset & 0xF); i += 4)
> -			seq_puts(s, "         ");
> -	}
> -
> -	pm_runtime_get_sync(&dpu_kms->pdev->dev);
> -
> -	/* main register output */
> -	for (i = 0; i < regset->blk_len; i += 4) {
> -		addr = regset->offset + i;
> -		if ((addr & 0xF) == 0x0)
> -			seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
> -		seq_printf(s, " %08x", readl_relaxed(base + i));
> +	struct drm_plane *plane;
> +
> +	drm_for_each_plane(plane, kms->dev) {
> +		if (plane->fb && plane->state) {
> +			dpu_plane_danger_signal_ctrl(plane, enable);
> +			DPU_DEBUG("plane:%d img:%dx%d ",
> +				plane->base.id, plane->fb->width,
> +				plane->fb->height);
> +			DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
> +				plane->state->src_x >> 16,
> +				plane->state->src_y >> 16,
> +				plane->state->src_w >> 16,
> +				plane->state->src_h >> 16,
> +				plane->state->crtc_x, plane->state->crtc_y,
> +				plane->state->crtc_w, plane->state->crtc_h);
> +		} else {
> +			DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
> +		}
>  	}
> -	seq_puts(s, "\n");
> -	pm_runtime_put_sync(&dpu_kms->pdev->dev);
> -
> -	return 0;
>  }
> 
> -static int dpu_debugfs_open_regset32(struct inode *inode,
> -		struct file *file)
> +static ssize_t _dpu_plane_danger_write(struct file *file,
> +		    const char __user *user_buf, size_t count, loff_t *ppos)
>  {
> -	return single_open(file, _dpu_debugfs_show_regset32, 
> inode->i_private);
> -}
> +	struct dpu_kms *kms = file->private_data;
> +	int disable_panic;
> +	int ret;
> 
> -static const struct file_operations dpu_fops_regset32 = {
> -	.open =		dpu_debugfs_open_regset32,
> -	.read =		seq_read,
> -	.llseek =	seq_lseek,
> -	.release =	single_release,
> -};
> +	ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
> +	if (ret)
> +		return ret;
> 
> -void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset,
> -		uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)
> -{
> -	if (regset) {
> -		regset->offset = offset;
> -		regset->blk_len = length;
> -		regset->dpu_kms = dpu_kms;
> +	if (disable_panic) {
> +		/* Disable panic signal for all active pipes */
> +		DPU_DEBUG("Disabling danger:\n");
> +		_dpu_plane_set_danger_state(kms, false);
> +		kms->has_danger_ctrl = false;
> +	} else {
> +		/* Enable panic signal for all active pipes */
> +		DPU_DEBUG("Enabling danger:\n");
> +		kms->has_danger_ctrl = true;
> +		_dpu_plane_set_danger_state(kms, true);
>  	}
> +
> +	return count;
>  }
> 
> -void dpu_debugfs_create_regset32(const char *name, umode_t mode,
> -		void *parent, struct dpu_debugfs_regset32 *regset)
> +static const struct file_operations dpu_plane_danger_enable = {
> +	.open = simple_open,
> +	.read = _dpu_plane_danger_read,
> +	.write = _dpu_plane_danger_write,
> +};
> +
> +static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
> +		struct dentry *parent)
>  {
> -	if (!name || !regset || !regset->dpu_kms || !regset->blk_len)
> -		return;
> +	struct dentry *entry = debugfs_create_dir("danger", parent);
> 
> -	/* make sure offset is a multiple of 4 */
> -	regset->offset = round_down(regset->offset, 4);
> +	debugfs_create_file("danger_status", 0600, entry,
> +			dpu_kms, &dpu_debugfs_danger_stats_fops);
> +	debugfs_create_file("safe_status", 0600, entry,
> +			dpu_kms, &dpu_debugfs_safe_stats_fops);
> +	debugfs_create_file("disable_danger", 0600, entry,
> +			dpu_kms, &dpu_plane_danger_enable);
> 
> -	debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32);
>  }
> 
>  static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor 
> *minor)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> index 323a6bce9e64..ab65c817eb42 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> @@ -166,75 +166,6 @@ struct dpu_global_state
>  struct dpu_global_state
>  	*__must_check dpu_kms_get_global_state(struct drm_atomic_state *s);
> 
> -/**
> - * Debugfs functions - extra helper functions for debugfs support
> - *
> - * Main debugfs documentation is located at,
> - *
> - * Documentation/filesystems/debugfs.rst
> - *
> - * @dpu_debugfs_setup_regset32: Initialize data for 
> dpu_debugfs_create_regset32
> - * @dpu_debugfs_create_regset32: Create 32-bit register dump file
> - * @dpu_debugfs_get_root: Get root dentry for DPU_KMS's debugfs node
> - */
> -
> -/**
> - * Companion structure for dpu_debugfs_create_regset32. Do not 
> initialize the
> - * members of this structure explicitly; use
> dpu_debugfs_setup_regset32 instead.
> - */
> -struct dpu_debugfs_regset32 {
> -	uint32_t offset;
> -	uint32_t blk_len;
> -	struct dpu_kms *dpu_kms;
> -};
> -
> -/**
> - * dpu_debugfs_setup_regset32 - Initialize register block definition
> for debugfs
> - * This function is meant to initialize dpu_debugfs_regset32 
> structures for use
> - * with dpu_debugfs_create_regset32.
> - * @regset: opaque register definition structure
> - * @offset: sub-block offset
> - * @length: sub-block length, in bytes
> - * @dpu_kms: pointer to dpu kms structure
> - */
> -void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset,
> -		uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms);
> -
> -/**
> - * dpu_debugfs_create_regset32 - Create register read back file for 
> debugfs
> - *
> - * This function is almost identical to the standard 
> debugfs_create_regset32()
> - * function, with the main difference being that a list of register
> - * names/offsets do not need to be provided. The 'read' function 
> simply outputs
> - * sequential register values over a specified range.
> - *
> - * Similar to the related debugfs_create_regset32 API, the structure 
> pointed to
> - * by regset needs to persist for the lifetime of the created file. 
> The calling
> - * code is responsible for initialization/management of this 
> structure.
> - *
> - * The structure pointed to by regset is meant to be opaque. Please 
> use
> - * dpu_debugfs_setup_regset32 to initialize it.
> - *
> - * @name:   File name within debugfs
> - * @mode:   File mode within debugfs
> - * @parent: Parent directory entry within debugfs, can be NULL
> - * @regset: Pointer to persistent register block definition
> - */
> -void dpu_debugfs_create_regset32(const char *name, umode_t mode,
> -		void *parent, struct dpu_debugfs_regset32 *regset);
> -
> -/**
> - * dpu_debugfs_get_root - Return root directory entry for KMS's 
> debugfs
> - *
> - * The return value should be passed as the 'parent' argument to 
> subsequent
> - * debugfs create calls.
> - *
> - * @dpu_kms: Pointer to DPU's KMS structure
> - *
> - * Return: dentry pointer for DPU's debugfs location
> - */
> -void *dpu_debugfs_get_root(struct dpu_kms *dpu_kms);
> -
>  /**
>   * DPU info management functions
>   * These functions/definitions allow for building up a 'dpu_info' 
> structure
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index d8018e664925..42bcde1ddd0f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -108,13 +108,6 @@ struct dpu_plane {
>  	bool is_virtual;
>  	struct list_head mplane_list;
>  	struct dpu_mdss_cfg *catalog;
> -
> -	/* debugfs related stuff */
> -	struct dentry *debugfs_root;
> -	struct dpu_debugfs_regset32 debugfs_src;
> -	struct dpu_debugfs_regset32 debugfs_scaler;
> -	struct dpu_debugfs_regset32 debugfs_csc;
> -	bool debugfs_default_scale;
>  };
> 
>  static const uint64_t supported_format_modifiers[] = {
> @@ -1343,7 +1336,7 @@ static void dpu_plane_reset(struct drm_plane 
> *plane)
>  }
> 
>  #ifdef CONFIG_DEBUG_FS
> -static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool 
> enable)
> +void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool 
> enable)
>  {
>  	struct dpu_plane *pdpu = to_dpu_plane(plane);
>  	struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
> @@ -1355,168 +1348,8 @@ static void
> dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
>  	_dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
>  	pm_runtime_put_sync(&dpu_kms->pdev->dev);
>  }
> -
> -static ssize_t _dpu_plane_danger_read(struct file *file,
> -			char __user *buff, size_t count, loff_t *ppos)
> -{
> -	struct dpu_kms *kms = file->private_data;
> -	int len;
> -	char buf[40];
> -
> -	len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
> -
> -	return simple_read_from_buffer(buff, count, ppos, buf, len);
> -}
> -
> -static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool 
> enable)
> -{
> -	struct drm_plane *plane;
> -
> -	drm_for_each_plane(plane, kms->dev) {
> -		if (plane->fb && plane->state) {
> -			dpu_plane_danger_signal_ctrl(plane, enable);
> -			DPU_DEBUG("plane:%d img:%dx%d ",
> -				plane->base.id, plane->fb->width,
> -				plane->fb->height);
> -			DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
> -				plane->state->src_x >> 16,
> -				plane->state->src_y >> 16,
> -				plane->state->src_w >> 16,
> -				plane->state->src_h >> 16,
> -				plane->state->crtc_x, plane->state->crtc_y,
> -				plane->state->crtc_w, plane->state->crtc_h);
> -		} else {
> -			DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
> -		}
> -	}
> -}
> -
> -static ssize_t _dpu_plane_danger_write(struct file *file,
> -		    const char __user *user_buf, size_t count, loff_t *ppos)
> -{
> -	struct dpu_kms *kms = file->private_data;
> -	int disable_panic;
> -	int ret;
> -
> -	ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
> -	if (ret)
> -		return ret;
> -
> -	if (disable_panic) {
> -		/* Disable panic signal for all active pipes */
> -		DPU_DEBUG("Disabling danger:\n");
> -		_dpu_plane_set_danger_state(kms, false);
> -		kms->has_danger_ctrl = false;
> -	} else {
> -		/* Enable panic signal for all active pipes */
> -		DPU_DEBUG("Enabling danger:\n");
> -		kms->has_danger_ctrl = true;
> -		_dpu_plane_set_danger_state(kms, true);
> -	}
> -
> -	return count;
> -}
> -
> -static const struct file_operations dpu_plane_danger_enable = {
> -	.open = simple_open,
> -	.read = _dpu_plane_danger_read,
> -	.write = _dpu_plane_danger_write,
> -};
> -
> -static int _dpu_plane_init_debugfs(struct drm_plane *plane)
> -{
> -	struct dpu_plane *pdpu = to_dpu_plane(plane);
> -	struct dpu_kms *kms = _dpu_plane_get_kms(plane);
> -	const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap;
> -	const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
> -
> -	/* create overall sub-directory for the pipe */
> -	pdpu->debugfs_root =
> -		debugfs_create_dir(plane->name,
> -				plane->dev->primary->debugfs_root);
> -
> -	/* don't error check these */
> -	debugfs_create_xul("features", 0600,
> -			pdpu->debugfs_root, (unsigned long 
> *)&pdpu->pipe_hw->cap->features);
> -
> -	/* add register dump support */
> -	dpu_debugfs_setup_regset32(&pdpu->debugfs_src,
> -			sblk->src_blk.base + cfg->base,
> -			sblk->src_blk.len,
> -			kms);
> -	dpu_debugfs_create_regset32("src_blk", 0400,
> -			pdpu->debugfs_root, &pdpu->debugfs_src);
> -
> -	if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
> -			cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) ||
> -			cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) ||
> -			cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) {
> -		dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler,
> -				sblk->scaler_blk.base + cfg->base,
> -				sblk->scaler_blk.len,
> -				kms);
> -		dpu_debugfs_create_regset32("scaler_blk", 0400,
> -				pdpu->debugfs_root,
> -				&pdpu->debugfs_scaler);
> -		debugfs_create_bool("default_scaling",
> -				0600,
> -				pdpu->debugfs_root,
> -				&pdpu->debugfs_default_scale);
> -	}
> -
> -	if (cfg->features & BIT(DPU_SSPP_CSC) ||
> -			cfg->features & BIT(DPU_SSPP_CSC_10BIT)) {
> -		dpu_debugfs_setup_regset32(&pdpu->debugfs_csc,
> -				sblk->csc_blk.base + cfg->base,
> -				sblk->csc_blk.len,
> -				kms);
> -		dpu_debugfs_create_regset32("csc_blk", 0400,
> -				pdpu->debugfs_root, &pdpu->debugfs_csc);
> -	}
> -
> -	debugfs_create_u32("xin_id",
> -			0400,
> -			pdpu->debugfs_root,
> -			(u32 *) &cfg->xin_id);
> -	debugfs_create_u32("clk_ctrl",
> -			0400,
> -			pdpu->debugfs_root,
> -			(u32 *) &cfg->clk_ctrl);
> -	debugfs_create_x32("creq_vblank",
> -			0600,
> -			pdpu->debugfs_root,
> -			(u32 *) &sblk->creq_vblank);
> -	debugfs_create_x32("danger_vblank",
> -			0600,
> -			pdpu->debugfs_root,
> -			(u32 *) &sblk->danger_vblank);
> -
> -	debugfs_create_file("disable_danger",
> -			0600,
> -			pdpu->debugfs_root,
> -			kms, &dpu_plane_danger_enable);
> -
> -	return 0;
> -}
> -#else
> -static int _dpu_plane_init_debugfs(struct drm_plane *plane)
> -{
> -	return 0;
> -}
>  #endif
> 
> -static int dpu_plane_late_register(struct drm_plane *plane)
> -{
> -	return _dpu_plane_init_debugfs(plane);
> -}
> -
> -static void dpu_plane_early_unregister(struct drm_plane *plane)
> -{
> -	struct dpu_plane *pdpu = to_dpu_plane(plane);
> -
> -	debugfs_remove_recursive(pdpu->debugfs_root);
> -}
> -
>  static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
>  		uint32_t format, uint64_t modifier)
>  {
> @@ -1541,8 +1374,6 @@ static const struct drm_plane_funcs 
> dpu_plane_funcs = {
>  		.reset = dpu_plane_reset,
>  		.atomic_duplicate_state = dpu_plane_duplicate_state,
>  		.atomic_destroy_state = dpu_plane_destroy_state,
> -		.late_register = dpu_plane_late_register,
> -		.early_unregister = dpu_plane_early_unregister,
>  		.format_mod_supported = dpu_plane_format_mod_supported,
>  };
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> index 1ee5ca5fcdf7..9d51dad5c6a5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -126,4 +126,10 @@ void dpu_plane_clear_multirect(const struct
> drm_plane_state *drm_state);
>  int dpu_plane_color_fill(struct drm_plane *plane,
>  		uint32_t color, uint32_t alpha);
> 
> +#ifdef CONFIG_DEBUG_FS
> +void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool 
> enable);
> +#else
> +static inline void dpu_plane_danger_signal_ctrl(struct drm_plane
> *plane, bool enable) {}
> +#endif
> +
>  #endif /* _DPU_PLANE_H_ */

Re: [Freedreno] [PATCH 11/11] drm/msm/dpu: rip out debugfs support from dpu_plane

[Dmitry Baryshkov]

Hi,

On Fri, 22 Oct 2021 at 02:53, <abhinavk@codeaurora.org> wrote:
>
> On 2021-09-30 07:00, Dmitry Baryshkov wrote:
> > In preparations of virtualizing the dpu_plane rip out debugfs support
> > from dpu_plane (as it is mostly used to expose plane's pipe registers).
> > Also move disable_danger file to danger/ debugfs subdir where it
> > belongs.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> I am yet to review the second part of the virtual plane series to
> understand why this removal
> is necessary so I might be missing something.

See below

>
> The plane's debugfs holds useful information to check a few things
> rightaway.
>
> So if there is some misconfiguration or corruption in addition to the
> plane state,
> this is good to check.
>
> localhost /sys/kernel/debug/dri/1/plane35 # cat src_blk
> [4000] 03000556 00000000 00000000 03000556
> [4010] 00000000 00414000 00000000 0040e000
> [4020] 00000000 00001600 00000080 00000000
> [4030] 800236ff 03010002 80000001 00000000
> [4040] 00000000 00000030 000c0087 00000707
> [4050] 00000000 00000000 00000000 00000000
> [4060] 0000ffff 00000000 00000000 00000001
> [4070] 00000000 44556677 00112233 00000000
> [4080] 00000000 00000000 00000000 00000000
> [4090] 00000000 00000000 00000000 00000000
> [40a0] 00000000 00414000 00000000 0040e000
> [40b0] 00000000 00000000 00000000 00000000
> [40c0] 00000000 00000000 00000000 00000000
> [40d0] 0003f820 00000000 00000000 00000000
> [40e0] 0003e2c4 00000000 00000000 00000000
> [40f0] 000f000f 00010330 02e402e4 00000000
> [4100] 00000000 00000000 03000556 00000000
> [4110] 00000000 00000000 03000556 00000000
> [4120] 00000000 00000000 03000556 00000000
> [4130] 00000000 0000000f 00000000 0000000f
> [4140] 00000000 00000000 00000000 00000000
>
> So I would like to keep this functionality unless there is some
> compelling reason
> to remove this.

Ok, I'll take a look if I can keep it or rework somehow.
The problem is that if you have the plane is virtual, there is no
strong plane <-> sspp mapping. Consider wide planes, where you'd have
two SSPPs per single plane.

I think it would make sense to move src_blk to global namespace (as
ssppN_src) and then add a file giving plane -> sspp relationship.

>
> BTW, are you going to submit the second half as a new series now that
> most
> of the first one has been reviewed?
>
> > ---
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   | 123 ++++++++--------
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h   |  69 ---------
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 171 +---------------------
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |   6 +
> >  4 files changed, 69 insertions(+), 300 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > index ae48f41821cf..fe33273cdf57 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > @@ -101,84 +101,85 @@ static int dpu_debugfs_safe_stats_show(struct
> > seq_file *s, void *v)
> >  }
> >  DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats);
> >
> > -static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
> > -             struct dentry *parent)
> > +static ssize_t _dpu_plane_danger_read(struct file *file,
> > +                     char __user *buff, size_t count, loff_t *ppos)
> >  {
> > -     struct dentry *entry = debugfs_create_dir("danger", parent);
> > +     struct dpu_kms *kms = file->private_data;
> > +     int len;
> > +     char buf[40];
> >
> > -     debugfs_create_file("danger_status", 0600, entry,
> > -                     dpu_kms, &dpu_debugfs_danger_stats_fops);
> > -     debugfs_create_file("safe_status", 0600, entry,
> > -                     dpu_kms, &dpu_debugfs_safe_stats_fops);
> > +     len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
> > +
> > +     return simple_read_from_buffer(buff, count, ppos, buf, len);
> >  }
> >
> > -static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
> > +static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool
> > enable)
> >  {
> > -     struct dpu_debugfs_regset32 *regset = s->private;
> > -     struct dpu_kms *dpu_kms = regset->dpu_kms;
> > -     void __iomem *base;
> > -     uint32_t i, addr;
> > -
> > -     if (!dpu_kms->mmio)
> > -             return 0;
> > -
> > -     base = dpu_kms->mmio + regset->offset;
> > -
> > -     /* insert padding spaces, if needed */
> > -     if (regset->offset & 0xF) {
> > -             seq_printf(s, "[%x]", regset->offset & ~0xF);
> > -             for (i = 0; i < (regset->offset & 0xF); i += 4)
> > -                     seq_puts(s, "         ");
> > -     }
> > -
> > -     pm_runtime_get_sync(&dpu_kms->pdev->dev);
> > -
> > -     /* main register output */
> > -     for (i = 0; i < regset->blk_len; i += 4) {
> > -             addr = regset->offset + i;
> > -             if ((addr & 0xF) == 0x0)
> > -                     seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
> > -             seq_printf(s, " %08x", readl_relaxed(base + i));
> > +     struct drm_plane *plane;
> > +
> > +     drm_for_each_plane(plane, kms->dev) {
> > +             if (plane->fb && plane->state) {
> > +                     dpu_plane_danger_signal_ctrl(plane, enable);
> > +                     DPU_DEBUG("plane:%d img:%dx%d ",
> > +                             plane->base.id, plane->fb->width,
> > +                             plane->fb->height);
> > +                     DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
> > +                             plane->state->src_x >> 16,
> > +                             plane->state->src_y >> 16,
> > +                             plane->state->src_w >> 16,
> > +                             plane->state->src_h >> 16,
> > +                             plane->state->crtc_x, plane->state->crtc_y,
> > +                             plane->state->crtc_w, plane->state->crtc_h);
> > +             } else {
> > +                     DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
> > +             }
> >       }
> > -     seq_puts(s, "\n");
> > -     pm_runtime_put_sync(&dpu_kms->pdev->dev);
> > -
> > -     return 0;
> >  }
> >
> > -static int dpu_debugfs_open_regset32(struct inode *inode,
> > -             struct file *file)
> > +static ssize_t _dpu_plane_danger_write(struct file *file,
> > +                 const char __user *user_buf, size_t count, loff_t *ppos)
> >  {
> > -     return single_open(file, _dpu_debugfs_show_regset32,
> > inode->i_private);
> > -}
> > +     struct dpu_kms *kms = file->private_data;
> > +     int disable_panic;
> > +     int ret;
> >
> > -static const struct file_operations dpu_fops_regset32 = {
> > -     .open =         dpu_debugfs_open_regset32,
> > -     .read =         seq_read,
> > -     .llseek =       seq_lseek,
> > -     .release =      single_release,
> > -};
> > +     ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
> > +     if (ret)
> > +             return ret;
> >
> > -void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset,
> > -             uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)
> > -{
> > -     if (regset) {
> > -             regset->offset = offset;
> > -             regset->blk_len = length;
> > -             regset->dpu_kms = dpu_kms;
> > +     if (disable_panic) {
> > +             /* Disable panic signal for all active pipes */
> > +             DPU_DEBUG("Disabling danger:\n");
> > +             _dpu_plane_set_danger_state(kms, false);
> > +             kms->has_danger_ctrl = false;
> > +     } else {
> > +             /* Enable panic signal for all active pipes */
> > +             DPU_DEBUG("Enabling danger:\n");
> > +             kms->has_danger_ctrl = true;
> > +             _dpu_plane_set_danger_state(kms, true);
> >       }
> > +
> > +     return count;
> >  }
> >
> > -void dpu_debugfs_create_regset32(const char *name, umode_t mode,
> > -             void *parent, struct dpu_debugfs_regset32 *regset)
> > +static const struct file_operations dpu_plane_danger_enable = {
> > +     .open = simple_open,
> > +     .read = _dpu_plane_danger_read,
> > +     .write = _dpu_plane_danger_write,
> > +};
> > +
> > +static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
> > +             struct dentry *parent)
> >  {
> > -     if (!name || !regset || !regset->dpu_kms || !regset->blk_len)
> > -             return;
> > +     struct dentry *entry = debugfs_create_dir("danger", parent);
> >
> > -     /* make sure offset is a multiple of 4 */
> > -     regset->offset = round_down(regset->offset, 4);
> > +     debugfs_create_file("danger_status", 0600, entry,
> > +                     dpu_kms, &dpu_debugfs_danger_stats_fops);
> > +     debugfs_create_file("safe_status", 0600, entry,
> > +                     dpu_kms, &dpu_debugfs_safe_stats_fops);
> > +     debugfs_create_file("disable_danger", 0600, entry,
> > +                     dpu_kms, &dpu_plane_danger_enable);
> >
> > -     debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32);
> >  }
> >
> >  static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor
> > *minor)
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> > index 323a6bce9e64..ab65c817eb42 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> > @@ -166,75 +166,6 @@ struct dpu_global_state
> >  struct dpu_global_state
> >       *__must_check dpu_kms_get_global_state(struct drm_atomic_state *s);
> >
> > -/**
> > - * Debugfs functions - extra helper functions for debugfs support
> > - *
> > - * Main debugfs documentation is located at,
> > - *
> > - * Documentation/filesystems/debugfs.rst
> > - *
> > - * @dpu_debugfs_setup_regset32: Initialize data for
> > dpu_debugfs_create_regset32
> > - * @dpu_debugfs_create_regset32: Create 32-bit register dump file
> > - * @dpu_debugfs_get_root: Get root dentry for DPU_KMS's debugfs node
> > - */
> > -
> > -/**
> > - * Companion structure for dpu_debugfs_create_regset32. Do not
> > initialize the
> > - * members of this structure explicitly; use
> > dpu_debugfs_setup_regset32 instead.
> > - */
> > -struct dpu_debugfs_regset32 {
> > -     uint32_t offset;
> > -     uint32_t blk_len;
> > -     struct dpu_kms *dpu_kms;
> > -};
> > -
> > -/**
> > - * dpu_debugfs_setup_regset32 - Initialize register block definition
> > for debugfs
> > - * This function is meant to initialize dpu_debugfs_regset32
> > structures for use
> > - * with dpu_debugfs_create_regset32.
> > - * @regset: opaque register definition structure
> > - * @offset: sub-block offset
> > - * @length: sub-block length, in bytes
> > - * @dpu_kms: pointer to dpu kms structure
> > - */
> > -void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset,
> > -             uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms);
> > -
> > -/**
> > - * dpu_debugfs_create_regset32 - Create register read back file for
> > debugfs
> > - *
> > - * This function is almost identical to the standard
> > debugfs_create_regset32()
> > - * function, with the main difference being that a list of register
> > - * names/offsets do not need to be provided. The 'read' function
> > simply outputs
> > - * sequential register values over a specified range.
> > - *
> > - * Similar to the related debugfs_create_regset32 API, the structure
> > pointed to
> > - * by regset needs to persist for the lifetime of the created file.
> > The calling
> > - * code is responsible for initialization/management of this
> > structure.
> > - *
> > - * The structure pointed to by regset is meant to be opaque. Please
> > use
> > - * dpu_debugfs_setup_regset32 to initialize it.
> > - *
> > - * @name:   File name within debugfs
> > - * @mode:   File mode within debugfs
> > - * @parent: Parent directory entry within debugfs, can be NULL
> > - * @regset: Pointer to persistent register block definition
> > - */
> > -void dpu_debugfs_create_regset32(const char *name, umode_t mode,
> > -             void *parent, struct dpu_debugfs_regset32 *regset);
> > -
> > -/**
> > - * dpu_debugfs_get_root - Return root directory entry for KMS's
> > debugfs
> > - *
> > - * The return value should be passed as the 'parent' argument to
> > subsequent
> > - * debugfs create calls.
> > - *
> > - * @dpu_kms: Pointer to DPU's KMS structure
> > - *
> > - * Return: dentry pointer for DPU's debugfs location
> > - */
> > -void *dpu_debugfs_get_root(struct dpu_kms *dpu_kms);
> > -
> >  /**
> >   * DPU info management functions
> >   * These functions/definitions allow for building up a 'dpu_info'
> > structure
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > index d8018e664925..42bcde1ddd0f 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > @@ -108,13 +108,6 @@ struct dpu_plane {
> >       bool is_virtual;
> >       struct list_head mplane_list;
> >       struct dpu_mdss_cfg *catalog;
> > -
> > -     /* debugfs related stuff */
> > -     struct dentry *debugfs_root;
> > -     struct dpu_debugfs_regset32 debugfs_src;
> > -     struct dpu_debugfs_regset32 debugfs_scaler;
> > -     struct dpu_debugfs_regset32 debugfs_csc;
> > -     bool debugfs_default_scale;
> >  };
> >
> >  static const uint64_t supported_format_modifiers[] = {
> > @@ -1343,7 +1336,7 @@ static void dpu_plane_reset(struct drm_plane
> > *plane)
> >  }
> >
> >  #ifdef CONFIG_DEBUG_FS
> > -static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool
> > enable)
> > +void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool
> > enable)
> >  {
> >       struct dpu_plane *pdpu = to_dpu_plane(plane);
> >       struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
> > @@ -1355,168 +1348,8 @@ static void
> > dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
> >       _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
> >       pm_runtime_put_sync(&dpu_kms->pdev->dev);
> >  }
> > -
> > -static ssize_t _dpu_plane_danger_read(struct file *file,
> > -                     char __user *buff, size_t count, loff_t *ppos)
> > -{
> > -     struct dpu_kms *kms = file->private_data;
> > -     int len;
> > -     char buf[40];
> > -
> > -     len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
> > -
> > -     return simple_read_from_buffer(buff, count, ppos, buf, len);
> > -}
> > -
> > -static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool
> > enable)
> > -{
> > -     struct drm_plane *plane;
> > -
> > -     drm_for_each_plane(plane, kms->dev) {
> > -             if (plane->fb && plane->state) {
> > -                     dpu_plane_danger_signal_ctrl(plane, enable);
> > -                     DPU_DEBUG("plane:%d img:%dx%d ",
> > -                             plane->base.id, plane->fb->width,
> > -                             plane->fb->height);
> > -                     DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
> > -                             plane->state->src_x >> 16,
> > -                             plane->state->src_y >> 16,
> > -                             plane->state->src_w >> 16,
> > -                             plane->state->src_h >> 16,
> > -                             plane->state->crtc_x, plane->state->crtc_y,
> > -                             plane->state->crtc_w, plane->state->crtc_h);
> > -             } else {
> > -                     DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
> > -             }
> > -     }
> > -}
> > -
> > -static ssize_t _dpu_plane_danger_write(struct file *file,
> > -                 const char __user *user_buf, size_t count, loff_t *ppos)
> > -{
> > -     struct dpu_kms *kms = file->private_data;
> > -     int disable_panic;
> > -     int ret;
> > -
> > -     ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
> > -     if (ret)
> > -             return ret;
> > -
> > -     if (disable_panic) {
> > -             /* Disable panic signal for all active pipes */
> > -             DPU_DEBUG("Disabling danger:\n");
> > -             _dpu_plane_set_danger_state(kms, false);
> > -             kms->has_danger_ctrl = false;
> > -     } else {
> > -             /* Enable panic signal for all active pipes */
> > -             DPU_DEBUG("Enabling danger:\n");
> > -             kms->has_danger_ctrl = true;
> > -             _dpu_plane_set_danger_state(kms, true);
> > -     }
> > -
> > -     return count;
> > -}
> > -
> > -static const struct file_operations dpu_plane_danger_enable = {
> > -     .open = simple_open,
> > -     .read = _dpu_plane_danger_read,
> > -     .write = _dpu_plane_danger_write,
> > -};
> > -
> > -static int _dpu_plane_init_debugfs(struct drm_plane *plane)
> > -{
> > -     struct dpu_plane *pdpu = to_dpu_plane(plane);
> > -     struct dpu_kms *kms = _dpu_plane_get_kms(plane);
> > -     const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap;
> > -     const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
> > -
> > -     /* create overall sub-directory for the pipe */
> > -     pdpu->debugfs_root =
> > -             debugfs_create_dir(plane->name,
> > -                             plane->dev->primary->debugfs_root);
> > -
> > -     /* don't error check these */
> > -     debugfs_create_xul("features", 0600,
> > -                     pdpu->debugfs_root, (unsigned long
> > *)&pdpu->pipe_hw->cap->features);
> > -
> > -     /* add register dump support */
> > -     dpu_debugfs_setup_regset32(&pdpu->debugfs_src,
> > -                     sblk->src_blk.base + cfg->base,
> > -                     sblk->src_blk.len,
> > -                     kms);
> > -     dpu_debugfs_create_regset32("src_blk", 0400,
> > -                     pdpu->debugfs_root, &pdpu->debugfs_src);
> > -
> > -     if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
> > -                     cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) ||
> > -                     cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) ||
> > -                     cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) {
> > -             dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler,
> > -                             sblk->scaler_blk.base + cfg->base,
> > -                             sblk->scaler_blk.len,
> > -                             kms);
> > -             dpu_debugfs_create_regset32("scaler_blk", 0400,
> > -                             pdpu->debugfs_root,
> > -                             &pdpu->debugfs_scaler);
> > -             debugfs_create_bool("default_scaling",
> > -                             0600,
> > -                             pdpu->debugfs_root,
> > -                             &pdpu->debugfs_default_scale);
> > -     }
> > -
> > -     if (cfg->features & BIT(DPU_SSPP_CSC) ||
> > -                     cfg->features & BIT(DPU_SSPP_CSC_10BIT)) {
> > -             dpu_debugfs_setup_regset32(&pdpu->debugfs_csc,
> > -                             sblk->csc_blk.base + cfg->base,
> > -                             sblk->csc_blk.len,
> > -                             kms);
> > -             dpu_debugfs_create_regset32("csc_blk", 0400,
> > -                             pdpu->debugfs_root, &pdpu->debugfs_csc);
> > -     }
> > -
> > -     debugfs_create_u32("xin_id",
> > -                     0400,
> > -                     pdpu->debugfs_root,
> > -                     (u32 *) &cfg->xin_id);
> > -     debugfs_create_u32("clk_ctrl",
> > -                     0400,
> > -                     pdpu->debugfs_root,
> > -                     (u32 *) &cfg->clk_ctrl);
> > -     debugfs_create_x32("creq_vblank",
> > -                     0600,
> > -                     pdpu->debugfs_root,
> > -                     (u32 *) &sblk->creq_vblank);
> > -     debugfs_create_x32("danger_vblank",
> > -                     0600,
> > -                     pdpu->debugfs_root,
> > -                     (u32 *) &sblk->danger_vblank);
> > -
> > -     debugfs_create_file("disable_danger",
> > -                     0600,
> > -                     pdpu->debugfs_root,
> > -                     kms, &dpu_plane_danger_enable);
> > -
> > -     return 0;
> > -}
> > -#else
> > -static int _dpu_plane_init_debugfs(struct drm_plane *plane)
> > -{
> > -     return 0;
> > -}
> >  #endif
> >
> > -static int dpu_plane_late_register(struct drm_plane *plane)
> > -{
> > -     return _dpu_plane_init_debugfs(plane);
> > -}
> > -
> > -static void dpu_plane_early_unregister(struct drm_plane *plane)
> > -{
> > -     struct dpu_plane *pdpu = to_dpu_plane(plane);
> > -
> > -     debugfs_remove_recursive(pdpu->debugfs_root);
> > -}
> > -
> >  static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
> >               uint32_t format, uint64_t modifier)
> >  {
> > @@ -1541,8 +1374,6 @@ static const struct drm_plane_funcs
> > dpu_plane_funcs = {
> >               .reset = dpu_plane_reset,
> >               .atomic_duplicate_state = dpu_plane_duplicate_state,
> >               .atomic_destroy_state = dpu_plane_destroy_state,
> > -             .late_register = dpu_plane_late_register,
> > -             .early_unregister = dpu_plane_early_unregister,
> >               .format_mod_supported = dpu_plane_format_mod_supported,
> >  };
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> > index 1ee5ca5fcdf7..9d51dad5c6a5 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> > @@ -126,4 +126,10 @@ void dpu_plane_clear_multirect(const struct
> > drm_plane_state *drm_state);
> >  int dpu_plane_color_fill(struct drm_plane *plane,
> >               uint32_t color, uint32_t alpha);
> >
> > +#ifdef CONFIG_DEBUG_FS
> > +void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool
> > enable);
> > +#else
> > +static inline void dpu_plane_danger_signal_ctrl(struct drm_plane
> > *plane, bool enable) {}
> > +#endif
> > +
> >  #endif /* _DPU_PLANE_H_ */



-- 
With best wishes
Dmitry

Re: [Freedreno] [PATCH 11/11] drm/msm/dpu: rip out debugfs support from dpu_plane

[Rob Clark]

On Fri, Oct 22, 2021 at 4:35 AM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> Hi,
>
> On Fri, 22 Oct 2021 at 02:53, <abhinavk@codeaurora.org> wrote:
> >
> > On 2021-09-30 07:00, Dmitry Baryshkov wrote:
> > > In preparations of virtualizing the dpu_plane rip out debugfs support
> > > from dpu_plane (as it is mostly used to expose plane's pipe registers).
> > > Also move disable_danger file to danger/ debugfs subdir where it
> > > belongs.
> > >
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >
> > I am yet to review the second part of the virtual plane series to
> > understand why this removal
> > is necessary so I might be missing something.
>
> See below
>
> >
> > The plane's debugfs holds useful information to check a few things
> > rightaway.
> >
> > So if there is some misconfiguration or corruption in addition to the
> > plane state,
> > this is good to check.
> >
> > localhost /sys/kernel/debug/dri/1/plane35 # cat src_blk
> > [4000] 03000556 00000000 00000000 03000556
> > [4010] 00000000 00414000 00000000 0040e000
> > [4020] 00000000 00001600 00000080 00000000
> > [4030] 800236ff 03010002 80000001 00000000
> > [4040] 00000000 00000030 000c0087 00000707
> > [4050] 00000000 00000000 00000000 00000000
> > [4060] 0000ffff 00000000 00000000 00000001
> > [4070] 00000000 44556677 00112233 00000000
> > [4080] 00000000 00000000 00000000 00000000
> > [4090] 00000000 00000000 00000000 00000000
> > [40a0] 00000000 00414000 00000000 0040e000
> > [40b0] 00000000 00000000 00000000 00000000
> > [40c0] 00000000 00000000 00000000 00000000
> > [40d0] 0003f820 00000000 00000000 00000000
> > [40e0] 0003e2c4 00000000 00000000 00000000
> > [40f0] 000f000f 00010330 02e402e4 00000000
> > [4100] 00000000 00000000 03000556 00000000
> > [4110] 00000000 00000000 03000556 00000000
> > [4120] 00000000 00000000 03000556 00000000
> > [4130] 00000000 0000000f 00000000 0000000f
> > [4140] 00000000 00000000 00000000 00000000
> >
> > So I would like to keep this functionality unless there is some
> > compelling reason
> > to remove this.
>
> Ok, I'll take a look if I can keep it or rework somehow.
> The problem is that if you have the plane is virtual, there is no
> strong plane <-> sspp mapping. Consider wide planes, where you'd have
> two SSPPs per single plane.
>
> I think it would make sense to move src_blk to global namespace (as
> ssppN_src) and then add a file giving plane -> sspp relationship.

+1 for moving to per sspp debugfs files, decoupled from plane..

Also, we should implement atomic_print_state() so that we can see the
plane->sspp mapping in $debugfs/dri/N/state

BR,
-R

> >
> > BTW, are you going to submit the second half as a new series now that
> > most
> > of the first one has been reviewed?
> >
> > > ---
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   | 123 ++++++++--------
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h   |  69 ---------
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 171 +---------------------
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |   6 +
> > >  4 files changed, 69 insertions(+), 300 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > > index ae48f41821cf..fe33273cdf57 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > > @@ -101,84 +101,85 @@ static int dpu_debugfs_safe_stats_show(struct
> > > seq_file *s, void *v)
> > >  }
> > >  DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats);
> > >
> > > -static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
> > > -             struct dentry *parent)
> > > +static ssize_t _dpu_plane_danger_read(struct file *file,
> > > +                     char __user *buff, size_t count, loff_t *ppos)
> > >  {
> > > -     struct dentry *entry = debugfs_create_dir("danger", parent);
> > > +     struct dpu_kms *kms = file->private_data;
> > > +     int len;
> > > +     char buf[40];
> > >
> > > -     debugfs_create_file("danger_status", 0600, entry,
> > > -                     dpu_kms, &dpu_debugfs_danger_stats_fops);
> > > -     debugfs_create_file("safe_status", 0600, entry,
> > > -                     dpu_kms, &dpu_debugfs_safe_stats_fops);
> > > +     len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
> > > +
> > > +     return simple_read_from_buffer(buff, count, ppos, buf, len);
> > >  }
> > >
> > > -static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
> > > +static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool
> > > enable)
> > >  {
> > > -     struct dpu_debugfs_regset32 *regset = s->private;
> > > -     struct dpu_kms *dpu_kms = regset->dpu_kms;
> > > -     void __iomem *base;
> > > -     uint32_t i, addr;
> > > -
> > > -     if (!dpu_kms->mmio)
> > > -             return 0;
> > > -
> > > -     base = dpu_kms->mmio + regset->offset;
> > > -
> > > -     /* insert padding spaces, if needed */
> > > -     if (regset->offset & 0xF) {
> > > -             seq_printf(s, "[%x]", regset->offset & ~0xF);
> > > -             for (i = 0; i < (regset->offset & 0xF); i += 4)
> > > -                     seq_puts(s, "         ");
> > > -     }
> > > -
> > > -     pm_runtime_get_sync(&dpu_kms->pdev->dev);
> > > -
> > > -     /* main register output */
> > > -     for (i = 0; i < regset->blk_len; i += 4) {
> > > -             addr = regset->offset + i;
> > > -             if ((addr & 0xF) == 0x0)
> > > -                     seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
> > > -             seq_printf(s, " %08x", readl_relaxed(base + i));
> > > +     struct drm_plane *plane;
> > > +
> > > +     drm_for_each_plane(plane, kms->dev) {
> > > +             if (plane->fb && plane->state) {
> > > +                     dpu_plane_danger_signal_ctrl(plane, enable);
> > > +                     DPU_DEBUG("plane:%d img:%dx%d ",
> > > +                             plane->base.id, plane->fb->width,
> > > +                             plane->fb->height);
> > > +                     DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
> > > +                             plane->state->src_x >> 16,
> > > +                             plane->state->src_y >> 16,
> > > +                             plane->state->src_w >> 16,
> > > +                             plane->state->src_h >> 16,
> > > +                             plane->state->crtc_x, plane->state->crtc_y,
> > > +                             plane->state->crtc_w, plane->state->crtc_h);
> > > +             } else {
> > > +                     DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
> > > +             }
> > >       }
> > > -     seq_puts(s, "\n");
> > > -     pm_runtime_put_sync(&dpu_kms->pdev->dev);
> > > -
> > > -     return 0;
> > >  }
> > >
> > > -static int dpu_debugfs_open_regset32(struct inode *inode,
> > > -             struct file *file)
> > > +static ssize_t _dpu_plane_danger_write(struct file *file,
> > > +                 const char __user *user_buf, size_t count, loff_t *ppos)
> > >  {
> > > -     return single_open(file, _dpu_debugfs_show_regset32,
> > > inode->i_private);
> > > -}
> > > +     struct dpu_kms *kms = file->private_data;
> > > +     int disable_panic;
> > > +     int ret;
> > >
> > > -static const struct file_operations dpu_fops_regset32 = {
> > > -     .open =         dpu_debugfs_open_regset32,
> > > -     .read =         seq_read,
> > > -     .llseek =       seq_lseek,
> > > -     .release =      single_release,
> > > -};
> > > +     ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
> > > +     if (ret)
> > > +             return ret;
> > >
> > > -void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset,
> > > -             uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)
> > > -{
> > > -     if (regset) {
> > > -             regset->offset = offset;
> > > -             regset->blk_len = length;
> > > -             regset->dpu_kms = dpu_kms;
> > > +     if (disable_panic) {
> > > +             /* Disable panic signal for all active pipes */
> > > +             DPU_DEBUG("Disabling danger:\n");
> > > +             _dpu_plane_set_danger_state(kms, false);
> > > +             kms->has_danger_ctrl = false;
> > > +     } else {
> > > +             /* Enable panic signal for all active pipes */
> > > +             DPU_DEBUG("Enabling danger:\n");
> > > +             kms->has_danger_ctrl = true;
> > > +             _dpu_plane_set_danger_state(kms, true);
> > >       }
> > > +
> > > +     return count;
> > >  }
> > >
> > > -void dpu_debugfs_create_regset32(const char *name, umode_t mode,
> > > -             void *parent, struct dpu_debugfs_regset32 *regset)
> > > +static const struct file_operations dpu_plane_danger_enable = {
> > > +     .open = simple_open,
> > > +     .read = _dpu_plane_danger_read,
> > > +     .write = _dpu_plane_danger_write,
> > > +};
> > > +
> > > +static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
> > > +             struct dentry *parent)
> > >  {
> > > -     if (!name || !regset || !regset->dpu_kms || !regset->blk_len)
> > > -             return;
> > > +     struct dentry *entry = debugfs_create_dir("danger", parent);
> > >
> > > -     /* make sure offset is a multiple of 4 */
> > > -     regset->offset = round_down(regset->offset, 4);
> > > +     debugfs_create_file("danger_status", 0600, entry,
> > > +                     dpu_kms, &dpu_debugfs_danger_stats_fops);
> > > +     debugfs_create_file("safe_status", 0600, entry,
> > > +                     dpu_kms, &dpu_debugfs_safe_stats_fops);
> > > +     debugfs_create_file("disable_danger", 0600, entry,
> > > +                     dpu_kms, &dpu_plane_danger_enable);
> > >
> > > -     debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32);
> > >  }
> > >
> > >  static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor
> > > *minor)
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> > > index 323a6bce9e64..ab65c817eb42 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> > > @@ -166,75 +166,6 @@ struct dpu_global_state
> > >  struct dpu_global_state
> > >       *__must_check dpu_kms_get_global_state(struct drm_atomic_state *s);
> > >
> > > -/**
> > > - * Debugfs functions - extra helper functions for debugfs support
> > > - *
> > > - * Main debugfs documentation is located at,
> > > - *
> > > - * Documentation/filesystems/debugfs.rst
> > > - *
> > > - * @dpu_debugfs_setup_regset32: Initialize data for
> > > dpu_debugfs_create_regset32
> > > - * @dpu_debugfs_create_regset32: Create 32-bit register dump file
> > > - * @dpu_debugfs_get_root: Get root dentry for DPU_KMS's debugfs node
> > > - */
> > > -
> > > -/**
> > > - * Companion structure for dpu_debugfs_create_regset32. Do not
> > > initialize the
> > > - * members of this structure explicitly; use
> > > dpu_debugfs_setup_regset32 instead.
> > > - */
> > > -struct dpu_debugfs_regset32 {
> > > -     uint32_t offset;
> > > -     uint32_t blk_len;
> > > -     struct dpu_kms *dpu_kms;
> > > -};
> > > -
> > > -/**
> > > - * dpu_debugfs_setup_regset32 - Initialize register block definition
> > > for debugfs
> > > - * This function is meant to initialize dpu_debugfs_regset32
> > > structures for use
> > > - * with dpu_debugfs_create_regset32.
> > > - * @regset: opaque register definition structure
> > > - * @offset: sub-block offset
> > > - * @length: sub-block length, in bytes
> > > - * @dpu_kms: pointer to dpu kms structure
> > > - */
> > > -void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset,
> > > -             uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms);
> > > -
> > > -/**
> > > - * dpu_debugfs_create_regset32 - Create register read back file for
> > > debugfs
> > > - *
> > > - * This function is almost identical to the standard
> > > debugfs_create_regset32()
> > > - * function, with the main difference being that a list of register
> > > - * names/offsets do not need to be provided. The 'read' function
> > > simply outputs
> > > - * sequential register values over a specified range.
> > > - *
> > > - * Similar to the related debugfs_create_regset32 API, the structure
> > > pointed to
> > > - * by regset needs to persist for the lifetime of the created file.
> > > The calling
> > > - * code is responsible for initialization/management of this
> > > structure.
> > > - *
> > > - * The structure pointed to by regset is meant to be opaque. Please
> > > use
> > > - * dpu_debugfs_setup_regset32 to initialize it.
> > > - *
> > > - * @name:   File name within debugfs
> > > - * @mode:   File mode within debugfs
> > > - * @parent: Parent directory entry within debugfs, can be NULL
> > > - * @regset: Pointer to persistent register block definition
> > > - */
> > > -void dpu_debugfs_create_regset32(const char *name, umode_t mode,
> > > -             void *parent, struct dpu_debugfs_regset32 *regset);
> > > -
> > > -/**
> > > - * dpu_debugfs_get_root - Return root directory entry for KMS's
> > > debugfs
> > > - *
> > > - * The return value should be passed as the 'parent' argument to
> > > subsequent
> > > - * debugfs create calls.
> > > - *
> > > - * @dpu_kms: Pointer to DPU's KMS structure
> > > - *
> > > - * Return: dentry pointer for DPU's debugfs location
> > > - */
> > > -void *dpu_debugfs_get_root(struct dpu_kms *dpu_kms);
> > > -
> > >  /**
> > >   * DPU info management functions
> > >   * These functions/definitions allow for building up a 'dpu_info'
> > > structure
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > > index d8018e664925..42bcde1ddd0f 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > > @@ -108,13 +108,6 @@ struct dpu_plane {
> > >       bool is_virtual;
> > >       struct list_head mplane_list;
> > >       struct dpu_mdss_cfg *catalog;
> > > -
> > > -     /* debugfs related stuff */
> > > -     struct dentry *debugfs_root;
> > > -     struct dpu_debugfs_regset32 debugfs_src;
> > > -     struct dpu_debugfs_regset32 debugfs_scaler;
> > > -     struct dpu_debugfs_regset32 debugfs_csc;
> > > -     bool debugfs_default_scale;
> > >  };
> > >
> > >  static const uint64_t supported_format_modifiers[] = {
> > > @@ -1343,7 +1336,7 @@ static void dpu_plane_reset(struct drm_plane
> > > *plane)
> > >  }
> > >
> > >  #ifdef CONFIG_DEBUG_FS
> > > -static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool
> > > enable)
> > > +void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool
> > > enable)
> > >  {
> > >       struct dpu_plane *pdpu = to_dpu_plane(plane);
> > >       struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
> > > @@ -1355,168 +1348,8 @@ static void
> > > dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
> > >       _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL);
> > >       pm_runtime_put_sync(&dpu_kms->pdev->dev);
> > >  }
> > > -
> > > -static ssize_t _dpu_plane_danger_read(struct file *file,
> > > -                     char __user *buff, size_t count, loff_t *ppos)
> > > -{
> > > -     struct dpu_kms *kms = file->private_data;
> > > -     int len;
> > > -     char buf[40];
> > > -
> > > -     len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
> > > -
> > > -     return simple_read_from_buffer(buff, count, ppos, buf, len);
> > > -}
> > > -
> > > -static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool
> > > enable)
> > > -{
> > > -     struct drm_plane *plane;
> > > -
> > > -     drm_for_each_plane(plane, kms->dev) {
> > > -             if (plane->fb && plane->state) {
> > > -                     dpu_plane_danger_signal_ctrl(plane, enable);
> > > -                     DPU_DEBUG("plane:%d img:%dx%d ",
> > > -                             plane->base.id, plane->fb->width,
> > > -                             plane->fb->height);
> > > -                     DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
> > > -                             plane->state->src_x >> 16,
> > > -                             plane->state->src_y >> 16,
> > > -                             plane->state->src_w >> 16,
> > > -                             plane->state->src_h >> 16,
> > > -                             plane->state->crtc_x, plane->state->crtc_y,
> > > -                             plane->state->crtc_w, plane->state->crtc_h);
> > > -             } else {
> > > -                     DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
> > > -             }
> > > -     }
> > > -}
> > > -
> > > -static ssize_t _dpu_plane_danger_write(struct file *file,
> > > -                 const char __user *user_buf, size_t count, loff_t *ppos)
> > > -{
> > > -     struct dpu_kms *kms = file->private_data;
> > > -     int disable_panic;
> > > -     int ret;
> > > -
> > > -     ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
> > > -     if (ret)
> > > -             return ret;
> > > -
> > > -     if (disable_panic) {
> > > -             /* Disable panic signal for all active pipes */
> > > -             DPU_DEBUG("Disabling danger:\n");
> > > -             _dpu_plane_set_danger_state(kms, false);
> > > -             kms->has_danger_ctrl = false;
> > > -     } else {
> > > -             /* Enable panic signal for all active pipes */
> > > -             DPU_DEBUG("Enabling danger:\n");
> > > -             kms->has_danger_ctrl = true;
> > > -             _dpu_plane_set_danger_state(kms, true);
> > > -     }
> > > -
> > > -     return count;
> > > -}
> > > -
> > > -static const struct file_operations dpu_plane_danger_enable = {
> > > -     .open = simple_open,
> > > -     .read = _dpu_plane_danger_read,
> > > -     .write = _dpu_plane_danger_write,
> > > -};
> > > -
> > > -static int _dpu_plane_init_debugfs(struct drm_plane *plane)
> > > -{
> > > -     struct dpu_plane *pdpu = to_dpu_plane(plane);
> > > -     struct dpu_kms *kms = _dpu_plane_get_kms(plane);
> > > -     const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap;
> > > -     const struct dpu_sspp_sub_blks *sblk = cfg->sblk;
> > > -
> > > -     /* create overall sub-directory for the pipe */
> > > -     pdpu->debugfs_root =
> > > -             debugfs_create_dir(plane->name,
> > > -                             plane->dev->primary->debugfs_root);
> > > -
> > > -     /* don't error check these */
> > > -     debugfs_create_xul("features", 0600,
> > > -                     pdpu->debugfs_root, (unsigned long
> > > *)&pdpu->pipe_hw->cap->features);
> > > -
> > > -     /* add register dump support */
> > > -     dpu_debugfs_setup_regset32(&pdpu->debugfs_src,
> > > -                     sblk->src_blk.base + cfg->base,
> > > -                     sblk->src_blk.len,
> > > -                     kms);
> > > -     dpu_debugfs_create_regset32("src_blk", 0400,
> > > -                     pdpu->debugfs_root, &pdpu->debugfs_src);
> > > -
> > > -     if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
> > > -                     cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) ||
> > > -                     cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) ||
> > > -                     cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) {
> > > -             dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler,
> > > -                             sblk->scaler_blk.base + cfg->base,
> > > -                             sblk->scaler_blk.len,
> > > -                             kms);
> > > -             dpu_debugfs_create_regset32("scaler_blk", 0400,
> > > -                             pdpu->debugfs_root,
> > > -                             &pdpu->debugfs_scaler);
> > > -             debugfs_create_bool("default_scaling",
> > > -                             0600,
> > > -                             pdpu->debugfs_root,
> > > -                             &pdpu->debugfs_default_scale);
> > > -     }
> > > -
> > > -     if (cfg->features & BIT(DPU_SSPP_CSC) ||
> > > -                     cfg->features & BIT(DPU_SSPP_CSC_10BIT)) {
> > > -             dpu_debugfs_setup_regset32(&pdpu->debugfs_csc,
> > > -                             sblk->csc_blk.base + cfg->base,
> > > -                             sblk->csc_blk.len,
> > > -                             kms);
> > > -             dpu_debugfs_create_regset32("csc_blk", 0400,
> > > -                             pdpu->debugfs_root, &pdpu->debugfs_csc);
> > > -     }
> > > -
> > > -     debugfs_create_u32("xin_id",
> > > -                     0400,
> > > -                     pdpu->debugfs_root,
> > > -                     (u32 *) &cfg->xin_id);
> > > -     debugfs_create_u32("clk_ctrl",
> > > -                     0400,
> > > -                     pdpu->debugfs_root,
> > > -                     (u32 *) &cfg->clk_ctrl);
> > > -     debugfs_create_x32("creq_vblank",
> > > -                     0600,
> > > -                     pdpu->debugfs_root,
> > > -                     (u32 *) &sblk->creq_vblank);
> > > -     debugfs_create_x32("danger_vblank",
> > > -                     0600,
> > > -                     pdpu->debugfs_root,
> > > -                     (u32 *) &sblk->danger_vblank);
> > > -
> > > -     debugfs_create_file("disable_danger",
> > > -                     0600,
> > > -                     pdpu->debugfs_root,
> > > -                     kms, &dpu_plane_danger_enable);
> > > -
> > > -     return 0;
> > > -}
> > > -#else
> > > -static int _dpu_plane_init_debugfs(struct drm_plane *plane)
> > > -{
> > > -     return 0;
> > > -}
> > >  #endif
> > >
> > > -static int dpu_plane_late_register(struct drm_plane *plane)
> > > -{
> > > -     return _dpu_plane_init_debugfs(plane);
> > > -}
> > > -
> > > -static void dpu_plane_early_unregister(struct drm_plane *plane)
> > > -{
> > > -     struct dpu_plane *pdpu = to_dpu_plane(plane);
> > > -
> > > -     debugfs_remove_recursive(pdpu->debugfs_root);
> > > -}
> > > -
> > >  static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
> > >               uint32_t format, uint64_t modifier)
> > >  {
> > > @@ -1541,8 +1374,6 @@ static const struct drm_plane_funcs
> > > dpu_plane_funcs = {
> > >               .reset = dpu_plane_reset,
> > >               .atomic_duplicate_state = dpu_plane_duplicate_state,
> > >               .atomic_destroy_state = dpu_plane_destroy_state,
> > > -             .late_register = dpu_plane_late_register,
> > > -             .early_unregister = dpu_plane_early_unregister,
> > >               .format_mod_supported = dpu_plane_format_mod_supported,
> > >  };
> > >
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> > > index 1ee5ca5fcdf7..9d51dad5c6a5 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> > > @@ -126,4 +126,10 @@ void dpu_plane_clear_multirect(const struct
> > > drm_plane_state *drm_state);
> > >  int dpu_plane_color_fill(struct drm_plane *plane,
> > >               uint32_t color, uint32_t alpha);
> > >
> > > +#ifdef CONFIG_DEBUG_FS
> > > +void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool
> > > enable);
> > > +#else
> > > +static inline void dpu_plane_danger_signal_ctrl(struct drm_plane
> > > *plane, bool enable) {}
> > > +#endif
> > > +
> > >  #endif /* _DPU_PLANE_H_ */
>
>
>
> --
> With best wishes
> Dmitry