From: Vinod Koul <vkoul@kernel.org>
To: Rob Clark <robdclark@gmail.com>
Cc: linux-arm-msm@vger.kernel.org,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Vinod Koul <vkoul@kernel.org>, David Airlie <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
Jonathan Marek <jonathan@marek.ca>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Abhinav Kumar <abhinavk@codeaurora.org>,
Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
Sumit Semwal <sumit.semwal@linaro.org>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org
Subject: [PATCH v2 07/11] drm/msm/disp/dpu1: Add DSC support in hw_ctl
Date: Thu, 7 Oct 2021 12:38:56 +0530 [thread overview]
Message-ID: <20211007070900.456044-8-vkoul@kernel.org> (raw)
In-Reply-To: <20211007070900.456044-1-vkoul@kernel.org>
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
Changes since
v1:
- Move this patch from 6 to 7 due to dependency on 6th one
- Use DSC indices for programming DSC registers and program only on non
null indices
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 3c79bd9c2fe5..8ea9d8dce3f7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -25,6 +25,8 @@
#define CTL_MERGE_3D_ACTIVE 0x0E4
#define CTL_INTF_ACTIVE 0x0F4
#define CTL_MERGE_3D_FLUSH 0x100
+#define CTL_DSC_ACTIVE 0x0E8
+#define CTL_DSC_FLUSH 0x104
#define CTL_INTF_FLUSH 0x110
#define CTL_INTF_MASTER 0x134
#define CTL_FETCH_PIPE_ACTIVE 0x0FC
@@ -34,6 +36,7 @@
#define DPU_REG_RESET_TIMEOUT_US 2000
#define MERGE_3D_IDX 23
+#define DSC_IDX 22
#define INTF_IDX 31
#define CTL_INVALID_BIT 0xffff
@@ -120,7 +123,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
static void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
{
-
if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
ctx->pending_merge_3d_flush_mask);
@@ -128,7 +130,6 @@ static void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,
ctx->pending_intf_flush_mask);
- DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
}
static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
@@ -498,6 +499,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
u32 intf_active = 0;
u32 mode_sel = 0;
+ if (cfg->dsc)
+ DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);
+
if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
mode_sel |= BIT(17);
@@ -509,6 +513,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
if (cfg->merge_3d)
DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
BIT(cfg->merge_3d - MERGE_3D_0));
+ if (cfg->dsc) {
+ DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask | BIT(DSC_IDX));
+ DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
+ }
}
static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
--
2.31.1
next prev parent reply other threads:[~2021-10-07 7:09 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-07 7:08 [PATCH v2 00/11] drm/msm: Add Display Stream Compression Support Vinod Koul
2021-10-07 7:08 ` [PATCH v2 01/11] drm/msm/dsi: add support for dsc data Vinod Koul
2021-10-25 14:43 ` Dmitry Baryshkov
2021-10-07 7:08 ` [PATCH v2 02/11] drm/msm/disp/dpu1: Add support for DSC Vinod Koul
2021-10-14 14:40 ` Dmitry Baryshkov
2021-10-19 14:07 ` Vinod Koul
2021-10-07 7:08 ` [PATCH v2 03/11] drm/msm/disp/dpu1: Add support for DSC in pingpong block Vinod Koul
2021-10-14 13:30 ` Dmitry Baryshkov
2021-10-07 7:08 ` [PATCH v2 04/11] drm/msm/disp/dpu1: Add DSC support in RM Vinod Koul
2021-10-14 14:11 ` Dmitry Baryshkov
2021-10-19 15:30 ` Vinod Koul
2021-10-19 15:52 ` Dmitry Baryshkov
2021-10-19 16:25 ` Vinod Koul
2021-10-07 7:08 ` [PATCH v2 05/11] drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog Vinod Koul
2021-10-14 13:33 ` Dmitry Baryshkov
2021-10-07 7:08 ` [PATCH v2 06/11] drm/msm/disp/dpu1: Don't use DSC with mode_3d Vinod Koul
2021-10-14 13:41 ` Dmitry Baryshkov
2021-10-14 13:50 ` Dmitry Baryshkov
2021-10-20 6:57 ` Vinod Koul
2021-10-25 14:40 ` Dmitry Baryshkov
2021-10-25 16:10 ` Vinod Koul
2021-10-25 18:33 ` Dmitry Baryshkov
2021-10-07 7:08 ` Vinod Koul [this message]
2021-10-14 14:06 ` [PATCH v2 07/11] drm/msm/disp/dpu1: Add DSC support in hw_ctl Dmitry Baryshkov
2021-10-20 9:19 ` Vinod Koul
2021-10-07 7:08 ` [PATCH v2 08/11] drm/msm/disp/dpu1: Add support for DSC in encoder Vinod Koul
2021-10-25 14:44 ` Dmitry Baryshkov
2021-10-07 7:08 ` [PATCH v2 09/11] drm/msm/disp/dpu1: Add support for DSC in topology Vinod Koul
2021-10-14 14:13 ` Dmitry Baryshkov
2021-10-25 14:37 ` Dmitry Baryshkov
2021-10-25 16:11 ` Vinod Koul
2021-10-07 7:08 ` [PATCH v2 10/11] drm/msm/dsi: Add support for DSC configuration Vinod Koul
2021-10-14 23:18 ` Dmitry Baryshkov
2021-10-20 11:53 ` Vinod Koul
2021-10-07 7:09 ` [PATCH v2 11/11] drm/msm/dsi: Pass DSC params to drm_panel Vinod Koul
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