From: devi priya <quic_devipriy@quicinc.com>
To: <agross@kernel.org>, <andersson@kernel.org>,
<konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <linus.walleij@linaro.org>,
<catalin.marinas@arm.com>, <will@kernel.org>,
<p.zabel@pengutronix.de>, <shawnguo@kernel.org>, <arnd@arndb.de>,
<marcel.ziswiler@toradex.com>, <dmitry.baryshkov@linaro.org>,
<nfraprado@collabora.com>, <broonie@kernel.org>,
<tdas@codeaurora.org>, <linux-arm-msm@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: <quic_srichara@quicinc.com>, <quic_gokulsri@quicinc.com>,
<quic_sjaganat@quicinc.com>, <quic_kathirav@quicinc.com>,
<quic_arajkuma@quicinc.com>, <quic_anusha@quicinc.com>,
<quic_poovendh@quicinc.com>
Subject: [PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings
Date: Tue, 10 Jan 2023 17:43:12 +0530 [thread overview]
Message-ID: <20230110121316.24892-4-quic_devipriy@quicinc.com> (raw)
In-Reply-To: <20230110121316.24892-1-quic_devipriy@quicinc.com>
Add device tree binding documentation details for ipq9574
pinctrl driver
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
.../bindings/pinctrl/qcom,ipq9574-tlmm.yaml | 129 ++++++++++++++++++
1 file changed, 129 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
new file mode 100644
index 000000000000..f9cb457bc18d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. IPQ9574 TLMM block
+
+maintainers:
+ - Anusha <quic_anusha@quicinc.com>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ IPQ9574 platform.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,ipq9574-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts: true
+ interrupt-controller: true
+ "#interrupt-cells": true
+ gpio-controller: true
+ gpio-reserved-ranges: true
+ "#gpio-cells": true
+ gpio-ranges: true
+ wakeup-parent: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-ipq9574-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-ipq9574-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-ipq9574-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
+ - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
+ sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
+ qdsd_data3 ]
+ minItems: 1
+ maxItems: 8
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
+ audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart,
+ blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
+ blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
+ blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
+ cri_trng1, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
+ gcc_plltest, gcc_tlmm, mac00, mac01, mac10, mac11, mdc,
+ mdio, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk,
+ pcie2_wake, pcie3_clk, pcie3_wake, prng_rosc0, prng_rosc1,
+ prng_rosc2, prng_rosc3, pta1_0, pta1_1, pta1_2, pta20, pta21,
+ pwm00, pwm01, pwm02, pwm03, pwm04, pwm10, pwm11, pwm12, pwm13,
+ pwm14, pwm20, pwm21, pwm22, pwm23, pwm24, pwm30, pwm31, pwm32,
+ pwm33, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
+ qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
+ qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
+ qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
+ dss_tracedata_b, qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
+ rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
+ wci20, wci21, wsa_swrm, audio_pdm0 ]
+
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ drive-strength: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+
+ additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq9574-tlmm";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 65>;
+
+ uart2-state {
+ pins = "gpio34", "gpio35";
+ function = "blsp2_uart";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+ };
--
2.17.1
next prev parent reply other threads:[~2023-01-10 12:17 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-10 12:13 [PATCH 0/7] Add minimal boot support for IPQ9574 devi priya
2023-01-10 12:13 ` [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset devi priya
2023-01-10 13:29 ` Rob Herring
2023-01-13 12:24 ` Devi Priya
2023-01-11 9:36 ` Krzysztof Kozlowski
2023-01-13 13:08 ` Devi Priya
2023-01-11 9:46 ` Krzysztof Kozlowski
2023-01-13 13:10 ` Devi Priya
2023-01-10 12:13 ` devi priya [this message]
2023-01-11 9:39 ` [PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings Krzysztof Kozlowski
2023-01-13 13:24 ` Devi Priya
2023-01-13 14:16 ` Krzysztof Kozlowski
2023-01-13 14:30 ` Devi Priya
2023-01-10 12:13 ` [PATCH 4/7] pinctrl: qcom: Add IPQ9574 pinctrl driver devi priya
2023-01-11 9:46 ` Krzysztof Kozlowski
2023-01-13 13:25 ` Devi Priya
2023-01-12 11:50 ` Kathiravan Thirumoorthy
2023-01-10 12:13 ` [PATCH 5/7] dt-bindings: qcom: Add ipq9574 bindings devi priya
2023-01-11 9:39 ` Krzysztof Kozlowski
2023-01-13 13:26 ` Devi Priya
2023-01-10 12:13 ` [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support devi priya
2023-01-10 12:50 ` Konrad Dybcio
2023-01-24 6:16 ` Devi Priya
2023-01-11 9:44 ` Krzysztof Kozlowski
2023-01-11 9:48 ` Krzysztof Kozlowski
2023-01-13 13:31 ` Devi Priya
2023-01-11 14:52 ` Kathiravan Thirumoorthy
2023-01-13 13:34 ` Devi Priya
2023-01-13 13:29 ` Devi Priya
2023-01-13 14:20 ` Krzysztof Kozlowski
2023-01-24 7:19 ` Devi Priya
2023-01-24 8:36 ` Krzysztof Kozlowski
2023-01-24 9:46 ` Konrad Dybcio
2023-01-24 13:22 ` Devi Priya
2023-01-11 9:45 ` Krzysztof Kozlowski
2023-01-13 13:36 ` Devi Priya
2023-01-13 13:49 ` Marc Zyngier
2023-01-13 13:52 ` Devi Priya
2023-01-10 12:13 ` [PATCH 7/7] arm64: defconfig: Enable IPQ9574 SoC base configs devi priya
2023-01-11 14:48 ` Kathiravan Thirumoorthy
2023-01-11 15:03 ` Krzysztof Kozlowski
2023-01-13 13:27 ` Devi Priya
[not found] ` <20230110121316.24892-3-quic_devipriy@quicinc.com>
2023-01-10 12:37 ` [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574 Konrad Dybcio
2023-01-13 13:21 ` Devi Priya
2023-01-13 14:09 ` Konrad Dybcio
2023-01-24 7:27 ` Devi Priya
2023-01-24 9:53 ` Konrad Dybcio
2023-01-24 13:50 ` Devi Priya
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