From: Andrew Halaney <ahalaney@redhat.com>
To: linux-kernel@vger.kernel.org
Cc: agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
sboyd@kernel.org, richardcochran@gmail.com,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, netdev@vger.kernel.org,
bmasney@redhat.com, echanude@redhat.com, ncai@quicinc.com,
jsuraj@qti.qualcomm.com, hisunil@quicinc.com,
Andrew Halaney <ahalaney@redhat.com>
Subject: [PATCH v5 1/3] clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
Date: Thu, 13 Apr 2023 14:15:39 -0500 [thread overview]
Message-ID: <20230413191541.1073027-2-ahalaney@redhat.com> (raw)
In-Reply-To: <20230413191541.1073027-1-ahalaney@redhat.com>
Add the EMAC GDSCs to allow the EMAC hardware to be enabled.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
---
Changes since v4:
* Add Tested-by (Brian)
Changes since v3:
* None
Changes since v2:
* Add Konrad's Reviewed-by
Changes since v1:
* Add Stephen's Acked-by
* Explicitly tested on x13s laptop with no noticeable side effect (Konrad)
drivers/clk/qcom/gcc-sc8280xp.c | 18 ++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-sc8280xp.h | 2 ++
2 files changed, 20 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c
index b3198784e1c3..04a99dbaa57e 100644
--- a/drivers/clk/qcom/gcc-sc8280xp.c
+++ b/drivers/clk/qcom/gcc-sc8280xp.c
@@ -6873,6 +6873,22 @@ static struct gdsc usb30_sec_gdsc = {
.pwrsts = PWRSTS_RET_ON,
};
+static struct gdsc emac_0_gdsc = {
+ .gdscr = 0xaa004,
+ .pd = {
+ .name = "emac_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc emac_1_gdsc = {
+ .gdscr = 0xba004,
+ .pd = {
+ .name = "emac_1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *gcc_sc8280xp_clocks[] = {
[GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie0_tunnel_axi_clk.clkr,
[GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie1_tunnel_axi_clk.clkr,
@@ -7351,6 +7367,8 @@ static struct gdsc *gcc_sc8280xp_gdscs[] = {
[USB30_MP_GDSC] = &usb30_mp_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
+ [EMAC_0_GDSC] = &emac_0_gdsc,
+ [EMAC_1_GDSC] = &emac_1_gdsc,
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h
index cb2fb638825c..721105ea4fad 100644
--- a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h
+++ b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h
@@ -492,5 +492,7 @@
#define USB30_MP_GDSC 9
#define USB30_PRIM_GDSC 10
#define USB30_SEC_GDSC 11
+#define EMAC_0_GDSC 12
+#define EMAC_1_GDSC 13
#endif
--
2.39.2
next prev parent reply other threads:[~2023-04-13 19:17 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-13 19:15 [PATCH v5 0/3] Add EMAC3 support for sa8540p-ride (devicetree/clk bits) Andrew Halaney
2023-04-13 19:15 ` Andrew Halaney [this message]
2023-04-13 19:15 ` [PATCH v5 2/3] arm64: dts: qcom: sc8280xp: Add ethernet nodes Andrew Halaney
2023-04-13 19:15 ` [PATCH v5 3/3] arm64: dts: qcom: sa8540p-ride: " Andrew Halaney
2023-04-13 20:47 ` Stephen Boyd
2023-04-13 21:01 ` Andrew Halaney
2023-04-13 22:05 ` Stephen Boyd
2023-04-14 14:58 ` Andrew Halaney
2023-04-24 14:42 ` Andrew Halaney
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