[PATCH v2 0/9] CPU enable method based SMP/hotplug + MSM conversion

[PATCH v2 0/9] CPU enable method based SMP/hotplug + MSM conversion

[Stephen Boyd]

This is a rework of patches sent a months back by Rohit[1].
The goal of these patches is to add support for SMP and (basic)
hotplug on MSM based SoCs. To get there, we add support for a
generic way to hook in SMP/hotplug support code based on DT. To
show how it's used, we convert the MSM8660 SMP support code over
to the new method. After that we add support for the rest of the
upstream MSM SoCs (note these patches are piled high on top of
Rohit's patches to add 8074 support to MSM[2] and my follow ups[3,4],
but this should only matter to the MSM maintainers).

This is one of the last items of code that still requires us to have
a mach directory and a machine descriptor. We should be able to move
the hotplug/smp code out of mach directories if this approach is
accepted.

Changes since v1:
 * Added pointers from cpu nodes to saw and acc nodes
 * Squashed nr_cpus removal into reorganization patch
 * Reworked bindings/documentation
 * Rebased onto v3.13-rc4

[1] https://lkml.org/lkml/2013/8/1/770
[2] https://lkml.org/lkml/2013/10/17/520
[3] https://lkml.org/lkml/2013/10/18/406
[4] http://lkml.org/lkml/2013/10/28/501
 

Rohit Vaswani (6):
  devicetree: bindings: Document Krait/Scorpion cpus and enable-method
  ARM: msm: Remove pen_release usage
  ARM: msm: Re-organize platsmp to make it extensible
  ARM: msm: Add SMP support for KPSSv1
  ARM: msm: Add SMP support for KPSSv2
  ARM: dts: msm: Add nodes necessary for SMP boot

Stephen Boyd (3):
  devicetree: bindings: Document qcom,kpss-acc
  devicetree: bindings: Document qcom,saw2 node
  ARM: Introduce CPU_METHOD_OF_DECLARE() for cpu hotplug/smp

 Documentation/devicetree/bindings/arm/cpus.txt     |  25 +-
 .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  |  30 ++
 .../devicetree/bindings/arm/msm/qcom,saw2.txt      |  35 ++
 arch/arm/boot/dts/qcom-msm8660-surf.dts            |  24 ++
 arch/arm/boot/dts/qcom-msm8960-cdp.dts             |  52 +++
 arch/arm/boot/dts/qcom-msm8974.dtsi                |  69 ++++
 arch/arm/include/asm/smp.h                         |   9 +
 arch/arm/kernel/devtree.c                          |  40 +++
 arch/arm/mach-msm/Makefile                         |   2 +-
 arch/arm/mach-msm/board-dt.c                       |  14 -
 arch/arm/mach-msm/common.h                         |   1 -
 arch/arm/mach-msm/headsmp.S                        |  39 ---
 arch/arm/mach-msm/hotplug.c                        |  31 +-
 arch/arm/mach-msm/platsmp.c                        | 371 ++++++++++++++++-----
 arch/arm/mach-msm/scm-boot.h                       |   8 +-
 include/asm-generic/vmlinux.lds.h                  |  10 +
 16 files changed, 595 insertions(+), 165 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
 delete mode 100644 arch/arm/mach-msm/headsmp.S

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[PATCH v2 1/9] devicetree: bindings: Document Krait/Scorpion cpus and enable-method

[Stephen Boyd]

From: Rohit Vaswani <rvaswani@codeaurora.org>

Scorpion and Krait don't use the spin-table enable-method.
Instead they rely on mmio register accesses to enable power and
clocks to bring CPUs out of reset. Document their enable-methods.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
[sboyd: Split off into separate patch, renamed methods to
match compatible nodes]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 Documentation/devicetree/bindings/arm/cpus.txt | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 9130435..333f4ae 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -180,7 +180,11 @@ nodes to be present and contain the properties described below.
 			  be one of:
 			     "spin-table"
 			     "psci"
-			# On ARM 32-bit systems this property is optional.
+			# On ARM 32-bit systems this property is optional and
+			  can be one of:
+			    "qcom,gcc-msm8660"
+			    "qcom,kpss-acc-v1"
+			    "qcom,kpss-acc-v2"
 
 	- cpu-release-addr
 		Usage: required for systems that have an "enable-method"
@@ -191,6 +195,21 @@ nodes to be present and contain the properties described below.
 			  property identifying a 64-bit zero-initialised
 			  memory location.
 
+	- qcom,saw
+		Usage: required for systems that have an "enable-method"
+		       property value of "qcom,kpss-acc-v1" or
+		       "qcom,kpss-acc-v2"
+		Value type: <phandle>
+		Definition: Specifies the SAW[1] node associated with this CPU.
+
+	- qcom,acc
+		Usage: required for systems that have an "enable-method"
+		       property value of "qcom,kpss-acc-v1" or
+		       "qcom,kpss-acc-v2"
+		Value type: <phandle>
+		Definition: Specifies the ACC[2] node associated with this CPU.
+
+
 Example 1 (dual-cluster big.LITTLE system 32-bit):
 
 	cpus {
@@ -382,3 +401,7 @@ cpus {
 		cpu-release-addr = <0 0x20000000>;
 	};
 };
+
+--
+[1] arm/msm/qcom,saw2.txt
+[2] arm/msm/qcom,kpss-acc.txt
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[PATCH v2 2/9] devicetree: bindings: Document qcom,kpss-acc

[Stephen Boyd]

The kpss acc binding describes the clock, reset, and power domain
controller for a Krait CPU.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
new file mode 100644
index 0000000..1333db9
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
@@ -0,0 +1,30 @@
+Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
+
+The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
+There is one ACC register region per CPU within the KPSS remapped region as
+well as an alias register region that remaps accesses to the ACC associated
+with the CPU accessing the region.
+
+PROPERTIES
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: should be one of:
+			"qcom,kpss-acc-v1"
+			"qcom,kpss-acc-v2"
+
+- reg:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: the first element specifies the base address and size of
+		    the register region. An optional second element specifies
+		    the base address and size of the alias register region.
+
+Example:
+
+	clock-controller@2088000 {
+		compatible = "qcom,kpss-acc-v2";
+		reg = <0x02088000 0x1000>,
+		      <0x02008000 0x1000>;
+	};
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[PATCH v2 3/9] devicetree: bindings: Document qcom,saw2 node

[Stephen Boyd]

The saw2 binding describes the SPM/AVS wrapper hardware used to
control the regulator supplying voltage to the Krait CPUs.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 .../devicetree/bindings/arm/msm/qcom,saw2.txt      | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
new file mode 100644
index 0000000..1505fb8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
@@ -0,0 +1,35 @@
+SPM AVS Wrapper 2 (SAW2)
+
+The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
+Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
+micro-controller that transitions a piece of hardware (like a processor or
+subsystem) into and out of low power modes via a direct connection to
+the PMIC. It can also be wired up to interact with other processors in the
+system, notifying them when a low power state is entered or exited.
+
+PROPERTIES
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: shall contain "qcom,saw2". A more specific value should be
+		    one of:
+			 "qcom,saw2-v1"
+			 "qcom,saw2-v1.1"
+			 "qcom,saw2-v2"
+			 "qcom,saw2-v2.1"
+
+- reg:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: the first element specifies the base address and size of
+		    the register region. An optional second element specifies
+		    the base address and size of the alias register region.
+
+
+Example:
+
+	regulator@2099000 {
+		compatible = "qcom,saw2";
+		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+	};
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[PATCH v2 4/9] ARM: Introduce CPU_METHOD_OF_DECLARE() for cpu hotplug/smp

[Stephen Boyd]

The goal of multi-platform kernels is to remove the need for mach
directories and machine descriptors. To further that goal,
introduce CPU_METHOD_OF_DECLARE() to allow cpu hotplug/smp
support to be separated from the machine descriptors.
Implementers should specify an enable-method property in their
cpus node and then implement a matching set of smp_ops in their
hotplug/smp code, wiring it up with the CPU_METHOD_OF_DECLARE()
macro. When the kernel is compiled we'll collect all the
enable-method smp_ops into one section for use at boot.

At boot time we'll look for an enable-method in each cpu node and
try to match that against all known CPU enable methods in the
kernel. If there are no enable-methods in the cpu nodes we
fallback to the cpus node and try to use any enable-method found
there. If that doesn't work we fall back to the old way of using
the machine descriptor.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/include/asm/smp.h        |  9 +++++++++
 arch/arm/kernel/devtree.c         | 40 +++++++++++++++++++++++++++++++++++++++
 include/asm-generic/vmlinux.lds.h | 10 ++++++++++
 3 files changed, 59 insertions(+)

diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 22a3b9b..772435b 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -114,6 +114,15 @@ struct smp_operations {
 #endif
 };
 
+struct of_cpu_method {
+	const char *method;
+	struct smp_operations *ops;
+};
+
+#define CPU_METHOD_OF_DECLARE(name, _method, _ops)			\
+	static const struct of_cpu_method __cpu_method_of_table_##name	\
+		__used __section(__cpu_method_of_table)			\
+		= { .method = _method, .ops = _ops }
 /*
  * set platform specific SMP operations
  */
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 739c3df..91cc3f8 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -18,6 +18,7 @@
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/smp.h>
 
 #include <asm/cputype.h>
 #include <asm/setup.h>
@@ -63,6 +64,34 @@ void __init arm_dt_memblock_reserve(void)
 	}
 }
 
+#ifdef CONFIG_SMP
+extern struct of_cpu_method __cpu_method_of_table_begin[];
+extern struct of_cpu_method __cpu_method_of_table_end[];
+
+static int __init set_smp_ops_by_method(struct device_node *node)
+{
+	const char *method;
+	struct of_cpu_method *m = __cpu_method_of_table_begin;
+
+	if (of_property_read_string(node, "enable-method", &method))
+		return 0;
+
+	for (; m < __cpu_method_of_table_end; m++)
+		if (!strcmp(m->method, method)) {
+			smp_set_ops(m->ops);
+			return 1;
+		}
+
+	return 0;
+}
+#else
+static inline int set_smp_ops_by_method(struct device_node *node)
+{
+	return 1;
+}
+#endif
+
+
 /*
  * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
  * and builds the cpu logical map array containing MPIDR values related to
@@ -79,6 +108,7 @@ void __init arm_dt_init_cpu_maps(void)
 	 * read as 0.
 	 */
 	struct device_node *cpu, *cpus;
+	int found_method = 0;
 	u32 i, j, cpuidx = 1;
 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
@@ -150,8 +180,18 @@ void __init arm_dt_init_cpu_maps(void)
 		}
 
 		tmp_map[i] = hwid;
+
+		if (!found_method)
+			found_method = set_smp_ops_by_method(cpu);
 	}
 
+	/*
+	 * Fallback to an enable-method in the cpus node if nothing found in
+	 * a cpu node.
+	 */
+	if (!found_method)
+		set_smp_ops_by_method(cpus);
+
 	if (!bootcpu_valid) {
 		pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n");
 		return;
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index bc2121f..bd02ca7 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -167,6 +167,15 @@
 #define CLK_OF_TABLES()
 #endif
 
+#ifdef CONFIG_SMP
+#define CPU_METHOD_OF_TABLES() . = ALIGN(8);				    \
+			   VMLINUX_SYMBOL(__cpu_method_of_table_begin) = .; \
+			   *(__cpu_method_of_table)			    \
+			   VMLINUX_SYMBOL(__cpu_method_of_table_end) = .;
+#else
+#define CPU_METHOD_OF_TABLES()
+#endif
+
 #define KERNEL_DTB()							\
 	STRUCT_ALIGN();							\
 	VMLINUX_SYMBOL(__dtb_start) = .;				\
@@ -491,6 +500,7 @@
 	MEM_DISCARD(init.rodata)					\
 	CLK_OF_TABLES()							\
 	CLKSRC_OF_TABLES()						\
+	CPU_METHOD_OF_TABLES()						\
 	KERNEL_DTB()							\
 	IRQCHIP_OF_MATCH_TABLE()
 
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[PATCH v2 5/9] ARM: msm: Remove pen_release usage

[Stephen Boyd]

From: Rohit Vaswani <rvaswani@codeaurora.org>

pen_release is no longer required as the synchronization
is now managed by generic arm code.
This is done as suggested in https://lkml.org/lkml/2013/6/4/184

Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/mach-msm/Makefile  |  2 +-
 arch/arm/mach-msm/headsmp.S | 39 ---------------------------------------
 arch/arm/mach-msm/hotplug.c | 31 ++++---------------------------
 arch/arm/mach-msm/platsmp.c | 35 +++--------------------------------
 4 files changed, 8 insertions(+), 99 deletions(-)
 delete mode 100644 arch/arm/mach-msm/headsmp.S

diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 7ed4c1b..15562cf 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -19,7 +19,7 @@ obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
 CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
 
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_SMP) += headsmp.o platsmp.o
+obj-$(CONFIG_SMP) += platsmp.o
 
 obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
 obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S
deleted file mode 100644
index 6c62c3f..0000000
--- a/arch/arm/mach-msm/headsmp.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/arch/arm/mach-realview/headsmp.S
- *
- *  Copyright (c) 2003 ARM Limited
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-/*
- * MSM specific entry point for secondary CPUs.  This provides
- * a "holding pen" into which all secondary cores are held until we're
- * ready for them to initialise.
- */
-ENTRY(msm_secondary_startup)
-	mrc	p15, 0, r0, c0, c0, 5
-	and	r0, r0, #15
-	adr	r4, 1f
-	ldmia	r4, {r5, r6}
-	sub	r4, r4, r5
-	add	r6, r6, r4
-pen:	ldr	r7, [r6]
-	cmp	r7, r0
-	bne	pen
-
-	/*
-	 * we've been released from the holding pen: secondary_stack
-	 * should now contain the SVC stack for this core
-	 */
-	b	secondary_startup
-ENDPROC(msm_secondary_startup)
-
-	.align
-1:	.long	.
-	.long	pen_release
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
index 326a872..cea80fc 100644
--- a/arch/arm/mach-msm/hotplug.c
+++ b/arch/arm/mach-msm/hotplug.c
@@ -24,33 +24,10 @@ static inline void cpu_leave_lowpower(void)
 
 static inline void platform_do_lowpower(unsigned int cpu)
 {
-	/* Just enter wfi for now. TODO: Properly shut off the cpu. */
-	for (;;) {
-		/*
-		 * here's the WFI
-		 */
-		asm("wfi"
-		    :
-		    :
-		    : "memory", "cc");
-
-		if (pen_release == cpu_logical_map(cpu)) {
-			/*
-			 * OK, proper wakeup, we're done
-			 */
-			break;
-		}
-
-		/*
-		 * getting here, means that we have come out of WFI without
-		 * having been woken up - this shouldn't happen
-		 *
-		 * The trouble is, letting people know about this is not really
-		 * possible, since we are currently running incoherently, and
-		 * therefore cannot safely call printk() or anything else
-		 */
-		pr_debug("CPU%u: spurious wakeup call\n", cpu);
-	}
+	asm("wfi"
+	    :
+	    :
+	    : "memory", "cc");
 }
 
 /*
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 3f06edc..5b481db 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -28,7 +28,7 @@
 #define SCSS_CPU1CORE_RESET 0xD80
 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
 
-extern void msm_secondary_startup(void);
+extern void secondary_startup(void);
 
 static DEFINE_SPINLOCK(boot_lock);
 
@@ -41,13 +41,6 @@ static inline int get_core_count(void)
 static void msm_secondary_init(unsigned int cpu)
 {
 	/*
-	 * let the primary processor know we're out of the
-	 * pen, then head off into the C entry point
-	 */
-	pen_release = -1;
-	smp_wmb();
-
-	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
@@ -57,7 +50,7 @@ static void msm_secondary_init(unsigned int cpu)
 static void prepare_cold_cpu(unsigned int cpu)
 {
 	int ret;
-	ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
+	ret = scm_set_boot_addr(virt_to_phys(secondary_startup),
 				SCM_FLAG_COLDBOOT_CPU1);
 	if (ret == 0) {
 		void __iomem *sc1_base_ptr;
@@ -75,7 +68,6 @@ static void prepare_cold_cpu(unsigned int cpu)
 
 static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-	unsigned long timeout;
 	static int cold_boot_done;
 
 	/* Only need to bring cpu out of reset this way once */
@@ -91,40 +83,19 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	spin_lock(&boot_lock);
 
 	/*
-	 * The secondary processor is waiting to be released from
-	 * the holding pen - release it, then wait for it to flag
-	 * that it has been released by resetting pen_release.
-	 *
-	 * Note that "pen_release" is the hardware CPU ID, whereas
-	 * "cpu" is Linux's internal ID.
-	 */
-	pen_release = cpu_logical_map(cpu);
-	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
-
-	/*
 	 * Send the secondary CPU a soft interrupt, thereby causing
 	 * the boot monitor to read the system wide flags register,
 	 * and branch to the address found there.
 	 */
 	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 
-	timeout = jiffies + (1 * HZ);
-	while (time_before(jiffies, timeout)) {
-		smp_rmb();
-		if (pen_release == -1)
-			break;
-
-		udelay(10);
-	}
-
 	/*
 	 * now the secondary core is starting up let it run its
 	 * calibrations, then wait for it to finish
 	 */
 	spin_unlock(&boot_lock);
 
-	return pen_release != -1 ? -ENOSYS : 0;
+	return 0;
 }
 
 /*
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[PATCH v2 6/9] ARM: msm: Re-organize platsmp to make it extensible

[Stephen Boyd]

From: Rohit Vaswani <rvaswani@codeaurora.org>

This makes it easy to add SMP support for new devices by keying
on a device node for the release sequence. We add the
enable-method property for the cpus property to specify that we
want to use the gcc-msm8660 release sequence (which is going to
look for the global clock controller device node to map some
Scorpion specific power and control registers). We also remove
the nr_cpus detection code as that is done generically in the DT
CPU detection code.

Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
[sboyd: Port to CPU_METHOD_OF_DECLARE]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/mach-msm/board-dt.c |  14 ------
 arch/arm/mach-msm/common.h   |   1 -
 arch/arm/mach-msm/platsmp.c  | 117 ++++++++++++++++++++++++-------------------
 3 files changed, 65 insertions(+), 67 deletions(-)

diff --git a/arch/arm/mach-msm/board-dt.c b/arch/arm/mach-msm/board-dt.c
index 1f11d93..1e3af2b 100644
--- a/arch/arm/mach-msm/board-dt.c
+++ b/arch/arm/mach-msm/board-dt.c
@@ -11,31 +11,17 @@
  */
 
 #include <linux/init.h>
-#include <linux/of.h>
-#include <linux/of_platform.h>
 
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
 
 static const char * const msm_dt_match[] __initconst = {
 	"qcom,msm8660-fluid",
 	"qcom,msm8660-surf",
 	"qcom,msm8960-cdp",
-	NULL
-};
-
-static const char * const apq8074_dt_match[] __initconst = {
 	"qcom,apq8074-dragonboard",
 	NULL
 };
 
 DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
-	.smp = smp_ops(msm_smp_ops),
 	.dt_compat = msm_dt_match,
 MACHINE_END
-
-DT_MACHINE_START(APQ_DT, "Qualcomm MSM (Flattened Device Tree)")
-	.dt_compat = apq8074_dt_match,
-MACHINE_END
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index 33c7725..1513f2c 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -23,7 +23,6 @@ extern void msm_map_qsd8x50_io(void);
 extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
 					  unsigned int mtype, void *caller);
 
-extern struct smp_operations msm_smp_ops;
 extern void msm_cpu_die(unsigned int cpu);
 
 struct msm_mmc_platform_data;
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 5b481db..11c6239 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -13,6 +13,8 @@
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/jiffies.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 
@@ -24,20 +26,14 @@
 #include "scm-boot.h"
 #include "common.h"
 
-#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
-#define SCSS_CPU1CORE_RESET 0xD80
-#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
+#define VDD_SC1_ARRAY_CLAMP_GFS_CTL	0x35a0
+#define SCSS_CPU1CORE_RESET		0x2d80
+#define SCSS_DBG_STATUS_CORE_PWRDUP	0x2e64
 
 extern void secondary_startup(void);
 
 static DEFINE_SPINLOCK(boot_lock);
 
-static inline int get_core_count(void)
-{
-	/* 1 + the PART[1:0] field of MIDR */
-	return ((read_cpuid_id() >> 4) & 3) + 1;
-}
-
 static void msm_secondary_init(unsigned int cpu)
 {
 	/*
@@ -47,33 +43,41 @@ static void msm_secondary_init(unsigned int cpu)
 	spin_unlock(&boot_lock);
 }
 
-static void prepare_cold_cpu(unsigned int cpu)
+static int scss_release_secondary(unsigned int cpu)
 {
-	int ret;
-	ret = scm_set_boot_addr(virt_to_phys(secondary_startup),
-				SCM_FLAG_COLDBOOT_CPU1);
-	if (ret == 0) {
-		void __iomem *sc1_base_ptr;
-		sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
-		if (sc1_base_ptr) {
-			writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
-			writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
-			writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
-			iounmap(sc1_base_ptr);
-		}
-	} else
-		printk(KERN_DEBUG "Failed to set secondary core boot "
-				  "address\n");
+	struct device_node *node;
+	void __iomem *base;
+
+	node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660");
+	if (!node) {
+		pr_err("%s: can't find node\n", __func__);
+		return -ENXIO;
+	}
+
+	base = of_iomap(node, 0);
+	of_node_put(node);
+	if (!base)
+		return -ENOMEM;
+
+	writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
+	writel_relaxed(0, base + SCSS_CPU1CORE_RESET);
+	writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP);
+	mb();
+	iounmap(base);
+
+	return 0;
 }
 
-static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static DEFINE_PER_CPU(int, cold_boot_done);
+
+static int msm_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
 {
-	static int cold_boot_done;
+	int ret = 0;
 
-	/* Only need to bring cpu out of reset this way once */
-	if (cold_boot_done == false) {
-		prepare_cold_cpu(cpu);
-		cold_boot_done = true;
+	if (!per_cpu(cold_boot_done, cpu)) {
+		ret = func(cpu);
+		if (!ret)
+			per_cpu(cold_boot_done, cpu) = true;
 	}
 
 	/*
@@ -95,39 +99,48 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 */
 	spin_unlock(&boot_lock);
 
-	return 0;
+	return ret;
 }
 
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system. The msm8x60
- * does not support the ARM SCU, so just set the possible cpu mask to
- * NR_CPUS.
- */
-static void __init msm_smp_init_cpus(void)
+static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-	unsigned int i, ncores = get_core_count();
-
-	if (ncores > nr_cpu_ids) {
-		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
-			ncores, nr_cpu_ids);
-		ncores = nr_cpu_ids;
-	}
-
-	for (i = 0; i < ncores; i++)
-		set_cpu_possible(i, true);
+	return msm_boot_secondary(cpu, scss_release_secondary);
 }
 
 static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
 {
+	int cpu, map;
+	unsigned int flags = 0;
+	static const int cold_boot_flags[] = {
+		0,
+		SCM_FLAG_COLDBOOT_CPU1,
+	};
+
+	for_each_present_cpu(cpu) {
+		map = cpu_logical_map(cpu);
+		if (WARN_ON(map >= ARRAY_SIZE(cold_boot_flags))) {
+			set_cpu_present(cpu, false);
+			continue;
+		}
+		flags |= cold_boot_flags[map];
+	}
+
+	if (scm_set_boot_addr(virt_to_phys(secondary_startup), flags)) {
+		for_each_present_cpu(cpu) {
+			if (cpu == smp_processor_id())
+				continue;
+			set_cpu_present(cpu, false);
+		}
+		pr_warn("Failed to set CPU boot address, disabling SMP\n");
+	}
 }
 
-struct smp_operations msm_smp_ops __initdata = {
-	.smp_init_cpus		= msm_smp_init_cpus,
+static struct smp_operations msm_smp_8660_ops __initdata = {
 	.smp_prepare_cpus	= msm_smp_prepare_cpus,
 	.smp_secondary_init	= msm_secondary_init,
-	.smp_boot_secondary	= msm_boot_secondary,
+	.smp_boot_secondary	= msm8660_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_die		= msm_cpu_die,
 #endif
 };
+CPU_METHOD_OF_DECLARE(msm_smp, "qcom,gcc-msm8660", &msm_smp_8660_ops);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[PATCH v2 7/9] ARM: msm: Add SMP support for KPSSv1

[Stephen Boyd]

From: Rohit Vaswani <rvaswani@codeaurora.org>

Implement support for the Krait CPU release sequence when the
CPUs are part of the first version of the krait processor
subsystem.

Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/mach-msm/platsmp.c  | 106 +++++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/scm-boot.h |   8 ++--
 2 files changed, 111 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 11c6239..4b13cd8 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -30,6 +30,16 @@
 #define SCSS_CPU1CORE_RESET		0x2d80
 #define SCSS_DBG_STATUS_CORE_PWRDUP	0x2e64
 
+#define APCS_CPU_PWR_CTL	0x04
+#define PLL_CLAMP		BIT(8)
+#define CORE_PWRD_UP		BIT(7)
+#define COREPOR_RST		BIT(5)
+#define CORE_RST		BIT(4)
+#define L2DT_SLP		BIT(3)
+#define CLAMP			BIT(0)
+
+#define APCS_SAW2_VCTL		0x14
+
 extern void secondary_startup(void);
 
 static DEFINE_SPINLOCK(boot_lock);
@@ -68,6 +78,85 @@ static int scss_release_secondary(unsigned int cpu)
 	return 0;
 }
 
+static int kpssv1_release_secondary(unsigned int cpu)
+{
+	int ret = 0;
+	void __iomem *reg, *saw_reg;
+	struct device_node *cpu_node, *acc_node, *saw_node;
+	u32 val;
+
+	cpu_node = of_get_cpu_node(cpu, NULL);
+	if (!cpu_node)
+		return -ENODEV;
+
+	acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
+	if (!acc_node) {
+		ret = -ENODEV;
+		goto out_acc;
+	}
+
+	saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
+	if (!saw_node) {
+		ret = -ENODEV;
+		goto out_saw;
+	}
+
+	reg = of_iomap(acc_node, 0);
+	if (!reg) {
+		ret = -ENOMEM;
+		goto out_acc_map;
+	}
+
+	saw_reg = of_iomap(saw_node, 0);
+	if (!saw_reg) {
+		ret = -ENOMEM;
+		goto out_saw_map;
+	}
+
+	/* Turn on CPU rail */
+	writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
+	mb();
+	udelay(512);
+
+	/* Krait bring-up sequence */
+	val = PLL_CLAMP | L2DT_SLP | CLAMP;
+	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+	val &= ~L2DT_SLP;
+	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+	mb();
+	ndelay(300);
+
+	val |= COREPOR_RST;
+	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+	mb();
+	udelay(2);
+
+	val &= ~CLAMP;
+	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+	mb();
+	udelay(2);
+
+	val &= ~COREPOR_RST;
+	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+	mb();
+	udelay(100);
+
+	val |= CORE_PWRD_UP;
+	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+	mb();
+
+	iounmap(saw_reg);
+out_saw_map:
+	iounmap(reg);
+out_acc_map:
+	of_node_put(saw_node);
+out_saw:
+	of_node_put(acc_node);
+out_acc:
+	of_node_put(cpu_node);
+	return ret;
+}
+
 static DEFINE_PER_CPU(int, cold_boot_done);
 
 static int msm_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
@@ -107,6 +196,11 @@ static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	return msm_boot_secondary(cpu, scss_release_secondary);
 }
 
+static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	return msm_boot_secondary(cpu, kpssv1_release_secondary);
+}
+
 static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
 {
 	int cpu, map;
@@ -114,6 +208,8 @@ static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
 	static const int cold_boot_flags[] = {
 		0,
 		SCM_FLAG_COLDBOOT_CPU1,
+		SCM_FLAG_COLDBOOT_CPU2,
+		SCM_FLAG_COLDBOOT_CPU3,
 	};
 
 	for_each_present_cpu(cpu) {
@@ -144,3 +240,13 @@ static struct smp_operations msm_smp_8660_ops __initdata = {
 #endif
 };
 CPU_METHOD_OF_DECLARE(msm_smp, "qcom,gcc-msm8660", &msm_smp_8660_ops);
+
+static struct smp_operations msm_smp_kpssv1_ops __initdata = {
+	.smp_prepare_cpus	= msm_smp_prepare_cpus,
+	.smp_secondary_init	= msm_secondary_init,
+	.smp_boot_secondary	= kpssv1_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_die		= msm_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(msm_smp_kpssv1, "qcom,kpss-acc-v1", &msm_smp_kpssv1_ops);
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-msm/scm-boot.h
index 7be32ff..6aabb24 100644
--- a/arch/arm/mach-msm/scm-boot.h
+++ b/arch/arm/mach-msm/scm-boot.h
@@ -13,9 +13,11 @@
 #define __MACH_SCM_BOOT_H
 
 #define SCM_BOOT_ADDR			0x1
-#define SCM_FLAG_COLDBOOT_CPU1		0x1
-#define SCM_FLAG_WARMBOOT_CPU1		0x2
-#define SCM_FLAG_WARMBOOT_CPU0		0x4
+#define SCM_FLAG_COLDBOOT_CPU1		0x01
+#define SCM_FLAG_COLDBOOT_CPU2		0x08
+#define SCM_FLAG_COLDBOOT_CPU3		0x20
+#define SCM_FLAG_WARMBOOT_CPU0		0x04
+#define SCM_FLAG_WARMBOOT_CPU1		0x02
 
 int scm_set_boot_addr(phys_addr_t addr, int flags);
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[PATCH v2 8/9] ARM: msm: Add SMP support for KPSSv2

[Stephen Boyd]

From: Rohit Vaswani <rvaswani@codeaurora.org>

Implement support for the Krait CPU release sequence when the
CPUs are part of the second version of the Krait processor
subsystem.

Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/mach-msm/platsmp.c | 123 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 123 insertions(+)

diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 4b13cd8..f07ad9d 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -38,7 +38,15 @@
 #define L2DT_SLP		BIT(3)
 #define CLAMP			BIT(0)
 
+#define APC_PWR_GATE_CTL	0x14
+#define BHS_CNT_SHIFT		24
+#define LDO_PWR_DWN_SHIFT	16
+#define LDO_BYP_SHIFT		8
+#define BHS_SEG_SHIFT		1
+#define BHS_EN			BIT(0)
+
 #define APCS_SAW2_VCTL		0x14
+#define APCS_SAW2_2_VCTL	0x1c
 
 extern void secondary_startup(void);
 
@@ -157,6 +165,106 @@ out_acc:
 	return ret;
 }
 
+static int kpssv2_release_secondary(unsigned int cpu)
+{
+	void __iomem *reg;
+	struct device_node *cpu_node, *l2_node, *acc_node, *saw_node;
+	void __iomem *l2_saw_base;
+	unsigned reg_val;
+	int ret;
+
+	cpu_node = of_get_cpu_node(cpu, NULL);
+	if (!cpu_node)
+		return -ENODEV;
+
+	acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
+	if (!acc_node) {
+		ret = -ENODEV;
+		goto out_acc;
+	}
+
+	l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
+	if (!l2_node) {
+		ret = -ENODEV;
+		goto out_l2;
+	}
+
+	saw_node = of_parse_phandle(l2_node, "qcom,saw", 0);
+	if (!saw_node) {
+		ret = -ENODEV;
+		goto out_saw;
+	}
+
+	reg = of_iomap(acc_node, 0);
+	if (!reg) {
+		ret = -ENOMEM;
+		goto out_map;
+	}
+
+	l2_saw_base = of_iomap(saw_node, 0);
+	if (!l2_saw_base) {
+		ret = -ENOMEM;
+		goto out_saw_map;
+	}
+
+	/* Turn on the BHS, turn off LDO Bypass and power down LDO */
+	reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN;
+	writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
+	mb();
+	/* wait for the BHS to settle */
+	udelay(1);
+
+	/* Turn on BHS segments */
+	reg_val |= 0x3f << BHS_SEG_SHIFT;
+	writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
+	mb();
+	 /* wait for the BHS to settle */
+	udelay(1);
+
+	/* Finally turn on the bypass so that BHS supplies power */
+	reg_val |= 0x3f << LDO_BYP_SHIFT;
+	writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
+
+	/* enable max phases */
+	writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL);
+	mb();
+	udelay(50);
+
+	reg_val = COREPOR_RST | CLAMP;
+	writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
+	mb();
+	udelay(2);
+
+	reg_val &= ~CLAMP;
+	writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
+	mb();
+	udelay(2);
+
+	reg_val &= ~COREPOR_RST;
+	writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
+	mb();
+
+	reg_val |= CORE_PWRD_UP;
+	writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
+	mb();
+
+	ret = 0;
+
+	iounmap(l2_saw_base);
+out_saw_map:
+	iounmap(reg);
+out_map:
+	of_node_put(saw_node);
+out_saw:
+	of_node_put(l2_node);
+out_l2:
+	of_node_put(acc_node);
+out_acc:
+	of_node_put(cpu_node);
+
+	return ret;
+}
+
 static DEFINE_PER_CPU(int, cold_boot_done);
 
 static int msm_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
@@ -201,6 +309,11 @@ static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	return msm_boot_secondary(cpu, kpssv1_release_secondary);
 }
 
+static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	return msm_boot_secondary(cpu, kpssv2_release_secondary);
+}
+
 static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
 {
 	int cpu, map;
@@ -250,3 +363,13 @@ static struct smp_operations msm_smp_kpssv1_ops __initdata = {
 #endif
 };
 CPU_METHOD_OF_DECLARE(msm_smp_kpssv1, "qcom,kpss-acc-v1", &msm_smp_kpssv1_ops);
+
+static struct smp_operations msm_smp_kpssv2_ops __initdata = {
+	.smp_prepare_cpus	= msm_smp_prepare_cpus,
+	.smp_secondary_init	= msm_secondary_init,
+	.smp_boot_secondary	= kpssv2_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_die		= msm_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(msm_smp_kpssv2, "qcom,kpss-acc-v2", &msm_smp_kpssv2_ops);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[PATCH v2 9/9] ARM: dts: msm: Add nodes necessary for SMP boot

[Stephen Boyd]

From: Rohit Vaswani <rvaswani@codeaurora.org>

Add the necessary nodes to support SMP on MSM8660, MSM8960, and
MSM8974/APQ8074. While we're here also add in the error
interrupts for the Krait cache error detection.

Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
[sboyd: Split into separate patch, add error interrupts]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/boot/dts/qcom-msm8660-surf.dts | 24 ++++++++++++
 arch/arm/boot/dts/qcom-msm8960-cdp.dts  | 52 +++++++++++++++++++++++++
 arch/arm/boot/dts/qcom-msm8974.dtsi     | 69 +++++++++++++++++++++++++++++++++
 3 files changed, 145 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 20cb9ad..c72325e 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -9,6 +9,30 @@
 	compatible = "qcom,msm8660-surf", "qcom,msm8660";
 	interrupt-parent = <&intc>;
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,scorpion";
+		enable-method = "qcom,gcc-msm8660";
+
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+		};
+	};
+
 	intc: interrupt-controller@2080000 {
 		compatible = "qcom,msm-8660-qgic";
 		interrupt-controller;
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index d5b1318..bb20f94 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -9,6 +9,36 @@
 	compatible = "qcom,msm8960-cdp", "qcom,msm8960";
 	interrupt-parent = <&intc>;
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <1 14 0x304>;
+		compatible = "qcom,krait";
+		enable-method = "qcom,kpss-acc-v1";
+
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			next-level-cache = <&L2>;
+			qcom,acc = <&acc0>;
+			qcom,saw = <&saw0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			reg = <1>;
+			next-level-cache = <&L2>;
+			qcom,acc = <&acc1>;
+			qcom,saw = <&saw1>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			interrupts = <0 2 0x4>;
+		};
+	};
+
 	intc: interrupt-controller@2000000 {
 		compatible = "qcom,msm-qgic2";
 		interrupt-controller;
@@ -53,6 +83,28 @@
 		#reset-cells = <1>;
 	};
 
+	acc0: clock-controller@2088000 {
+		compatible = "qcom,kpss-acc-v1";
+		reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+	};
+
+	acc1: clock-controller@2098000 {
+		compatible = "qcom,kpss-acc-v1";
+		reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+	};
+
+	saw0: regulator@2089000 {
+		compatible = "qcom,saw2";
+		reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+		regulator;
+	};
+
+	saw1: regulator@2099000 {
+		compatible = "qcom,saw2";
+		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+		regulator;
+	};
+
 	serial@16440000 {
 		compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 		reg = <0x16440000 0x1000>,
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 9fa57d7..22555f6 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -9,6 +9,49 @@
 	compatible = "qcom,msm8974";
 	interrupt-parent = <&intc>;
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <1 9 0xf04>;
+		compatible = "qcom,krait";
+		enable-method = "qcom,kpss-acc-v2";
+
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			next-level-cache = <&L2>;
+			qcom,acc = <&acc0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			reg = <1>;
+			next-level-cache = <&L2>;
+			qcom,acc = <&acc1>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			reg = <2>;
+			next-level-cache = <&L2>;
+			qcom,acc = <&acc2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			reg = <3>;
+			next-level-cache = <&L2>;
+			qcom,acc = <&acc3>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			interrupts = <0 2 0x4>;
+			qcom,saw = <&saw_l2>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <1 2 0xf08>,
@@ -91,6 +134,32 @@
 			};
 		};
 
+		saw_l2: regulator@f9012000 {
+			compatible = "qcom,saw2";
+			reg = <0xf9012000 0x1000>;
+			regulator;
+		};
+
+		acc0: clock-controller@f9088000 {
+			compatible = "qcom,kpss-acc-v2";
+			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
+		};
+
+		acc1: clock-controller@f9098000 {
+			compatible = "qcom,kpss-acc-v2";
+			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
+		};
+
+		acc2: clock-controller@f90a8000 {
+			compatible = "qcom,kpss-acc-v2";
+			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
+		};
+
+		acc3: clock-controller@f90b8000 {
+			compatible = "qcom,kpss-acc-v2";
+			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
+		};
+
 		restart@fc4ab000 {
 			compatible = "qcom,pshold";
 			reg = <0xfc4ab000 0x4>;
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Re: [PATCH v2 0/9] CPU enable method based SMP/hotplug + MSM conversion

[Stephen Boyd]

Ping? Can anyone take a look at the generic ARM and DT binding patches
and provide acks/reviews? I'd like to send this through arm-soc via the
MSM tree if possible.

On 12/23/13 16:39, Stephen Boyd wrote:
> This is a rework of patches sent a months back by Rohit[1].
> The goal of these patches is to add support for SMP and (basic)
> hotplug on MSM based SoCs. To get there, we add support for a
> generic way to hook in SMP/hotplug support code based on DT. To
> show how it's used, we convert the MSM8660 SMP support code over
> to the new method. After that we add support for the rest of the
> upstream MSM SoCs (note these patches are piled high on top of
> Rohit's patches to add 8074 support to MSM[2] and my follow ups[3,4],
> but this should only matter to the MSM maintainers).
>
> This is one of the last items of code that still requires us to have
> a mach directory and a machine descriptor. We should be able to move
> the hotplug/smp code out of mach directories if this approach is
> accepted.
>
> Changes since v1:
>  * Added pointers from cpu nodes to saw and acc nodes
>  * Squashed nr_cpus removal into reorganization patch
>  * Reworked bindings/documentation
>  * Rebased onto v3.13-rc4
>
> [1] https://lkml.org/lkml/2013/8/1/770
> [2] https://lkml.org/lkml/2013/10/17/520
> [3] https://lkml.org/lkml/2013/10/18/406
> [4] http://lkml.org/lkml/2013/10/28/501
>  
>
> Rohit Vaswani (6):
>   devicetree: bindings: Document Krait/Scorpion cpus and enable-method
>   ARM: msm: Remove pen_release usage
>   ARM: msm: Re-organize platsmp to make it extensible
>   ARM: msm: Add SMP support for KPSSv1
>   ARM: msm: Add SMP support for KPSSv2
>   ARM: dts: msm: Add nodes necessary for SMP boot
>
> Stephen Boyd (3):
>   devicetree: bindings: Document qcom,kpss-acc
>   devicetree: bindings: Document qcom,saw2 node
>   ARM: Introduce CPU_METHOD_OF_DECLARE() for cpu hotplug/smp
>
>  Documentation/devicetree/bindings/arm/cpus.txt     |  25 +-
>  .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  |  30 ++
>  .../devicetree/bindings/arm/msm/qcom,saw2.txt      |  35 ++
>  arch/arm/boot/dts/qcom-msm8660-surf.dts            |  24 ++
>  arch/arm/boot/dts/qcom-msm8960-cdp.dts             |  52 +++
>  arch/arm/boot/dts/qcom-msm8974.dtsi                |  69 ++++
>  arch/arm/include/asm/smp.h                         |   9 +
>  arch/arm/kernel/devtree.c                          |  40 +++
>  arch/arm/mach-msm/Makefile                         |   2 +-
>  arch/arm/mach-msm/board-dt.c                       |  14 -
>  arch/arm/mach-msm/common.h                         |   1 -
>  arch/arm/mach-msm/headsmp.S                        |  39 ---
>  arch/arm/mach-msm/hotplug.c                        |  31 +-
>  arch/arm/mach-msm/platsmp.c                        | 371 ++++++++++++++++-----
>  arch/arm/mach-msm/scm-boot.h                       |   8 +-
>  include/asm-generic/vmlinux.lds.h                  |  10 +
>  16 files changed, 595 insertions(+), 165 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
>  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
>  delete mode 100644 arch/arm/mach-msm/headsmp.S
>


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Re: [PATCH v2 1/9] devicetree: bindings: Document Krait/Scorpion cpus and enable-method

[Mark Rutland]

On Tue, Dec 24, 2013 at 12:39:45AM +0000, Stephen Boyd wrote:
> From: Rohit Vaswani <rvaswani-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> 
> Scorpion and Krait don't use the spin-table enable-method.
> Instead they rely on mmio register accesses to enable power and
> clocks to bring CPUs out of reset. Document their enable-methods.
> 
> Cc: <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
> Signed-off-by: Rohit Vaswani <rvaswani-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> [sboyd: Split off into separate patch, renamed methods to
> match compatible nodes]
> Signed-off-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/arm/cpus.txt | 25 ++++++++++++++++++++++++-
>  1 file changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 9130435..333f4ae 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -180,7 +180,11 @@ nodes to be present and contain the properties described below.
>  			  be one of:
>  			     "spin-table"
>  			     "psci"
> -			# On ARM 32-bit systems this property is optional.
> +			# On ARM 32-bit systems this property is optional and
> +			  can be one of:
> +			    "qcom,gcc-msm8660"
> +			    "qcom,kpss-acc-v1"
> +			    "qcom,kpss-acc-v2"

It would be nice to document "psci" here as valid for 32-bit.

Currently the PSCI code doesn't inspect the enable-method and assumes it
if there's a psci node, but KVM tool and others set enable-method to
"psci", and if we change the way the PSCI code probes it will require
enable-method to be set for PSCI to work.

>  
>  	- cpu-release-addr
>  		Usage: required for systems that have an "enable-method"
> @@ -191,6 +195,21 @@ nodes to be present and contain the properties described below.
>  			  property identifying a 64-bit zero-initialised
>  			  memory location.
>  
> +	- qcom,saw
> +		Usage: required for systems that have an "enable-method"
> +		       property value of "qcom,kpss-acc-v1" or
> +		       "qcom,kpss-acc-v2"
> +		Value type: <phandle>
> +		Definition: Specifies the SAW[1] node associated with this CPU.
> +
> +	- qcom,acc
> +		Usage: required for systems that have an "enable-method"
> +		       property value of "qcom,kpss-acc-v1" or
> +		       "qcom,kpss-acc-v2"
> +		Value type: <phandle>
> +		Definition: Specifies the ACC[2] node associated with this CPU.
> +
> +
>  Example 1 (dual-cluster big.LITTLE system 32-bit):

If this is going to get much longer, we should probably have
Documentation/devicetree/bindings/arm/boot/ or similar, but that can be
done later.

Otherwise, this looks fine to me.

Acked-by: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>

Thanks,
Mark.
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Re: [PATCH v2 2/9] devicetree: bindings: Document qcom,kpss-acc

[Mark Rutland]

On Tue, Dec 24, 2013 at 12:39:46AM +0000, Stephen Boyd wrote:
> The kpss acc binding describes the clock, reset, and power domain
> controller for a Krait CPU.
> 
> Cc: <devicetree@vger.kernel.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
>  .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  | 30 ++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
> new file mode 100644
> index 0000000..1333db9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
> @@ -0,0 +1,30 @@
> +Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
> +
> +The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
> +There is one ACC register region per CPU within the KPSS remapped region as
> +well as an alias register region that remaps accesses to the ACC associated
> +with the CPU accessing the region.

Is the mapping of ACC register to a specific processor well-defined? I
assume it's just in order of MPIDR.Aff0.

To maintain our collective sanity in the face of possible future
implementations, do you have an idea as to whether this might need to be
extended in future for multiple clusters / reordered IDs and so on?

I assume we'd just allocate a new compatible string if those get a
little crazy.

> +
> +PROPERTIES
> +
> +- compatible:
> +	Usage: required
> +	Value type: <string>
> +	Definition: should be one of:
> +			"qcom,kpss-acc-v1"
> +			"qcom,kpss-acc-v2"
> +
> +- reg:
> +	Usage: required
> +	Value type: <prop-encoded-array>
> +	Definition: the first element specifies the base address and size of
> +		    the register region. An optional second element specifies
> +		    the base address and size of the alias register region.
> +
> +Example:
> +
> +	clock-controller@2088000 {
> +		compatible = "qcom,kpss-acc-v2";
> +		reg = <0x02088000 0x1000>,
> +		      <0x02008000 0x1000>;
> +	};

Otherwise, this looks fine to me.

Mark.

Re: [PATCH v2 2/9] devicetree: bindings: Document qcom,kpss-acc

[Mark Rutland]

On Wed, Jan 08, 2014 at 02:25:41PM +0000, Mark Rutland wrote:
> On Tue, Dec 24, 2013 at 12:39:46AM +0000, Stephen Boyd wrote:
> > The kpss acc binding describes the clock, reset, and power domain
> > controller for a Krait CPU.
> > 
> > Cc: <devicetree@vger.kernel.org>
> > Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> > ---
> >  .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  | 30 ++++++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
> > new file mode 100644
> > index 0000000..1333db9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
> > @@ -0,0 +1,30 @@
> > +Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
> > +
> > +The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
> > +There is one ACC register region per CPU within the KPSS remapped region as
> > +well as an alias register region that remaps accesses to the ACC associated
> > +with the CPU accessing the region.
> 
> Is the mapping of ACC register to a specific processor well-defined? I
> assume it's just in order of MPIDR.Aff0.
> 
> To maintain our collective sanity in the face of possible future
> implementations, do you have an idea as to whether this might need to be
> extended in future for multiple clusters / reordered IDs and so on?
> 
> I assume we'd just allocate a new compatible string if those get a
> little crazy.

Actually, I'm getting too hung-up on future-proofing. Assuming the
mapping is well-defined for current implementations we can always add an
additional property later if required.

Acked-by: Mark Rutland <mark.rutland@arm.com>

Thanks,
Mark.

Re: [PATCH v2 3/9] devicetree: bindings: Document qcom,saw2 node

[Mark Rutland]

On Tue, Dec 24, 2013 at 12:39:47AM +0000, Stephen Boyd wrote:
> The saw2 binding describes the SPM/AVS wrapper hardware used to
> control the regulator supplying voltage to the Krait CPUs.
> 
> Cc: <devicetree@vger.kernel.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
>  .../devicetree/bindings/arm/msm/qcom,saw2.txt      | 35 ++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
> new file mode 100644
> index 0000000..1505fb8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
> @@ -0,0 +1,35 @@
> +SPM AVS Wrapper 2 (SAW2)
> +
> +The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
> +Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
> +micro-controller that transitions a piece of hardware (like a processor or
> +subsystem) into and out of low power modes via a direct connection to
> +the PMIC. It can also be wired up to interact with other processors in the
> +system, notifying them when a low power state is entered or exited.
> +
> +PROPERTIES
> +
> +- compatible:
> +	Usage: required
> +	Value type: <string>
> +	Definition: shall contain "qcom,saw2". A more specific value should be
> +		    one of:
> +			 "qcom,saw2-v1"
> +			 "qcom,saw2-v1.1"
> +			 "qcom,saw2-v2"
> +			 "qcom,saw2-v2.1"
> +
> +- reg:
> +	Usage: required
> +	Value type: <prop-encoded-array>
> +	Definition: the first element specifies the base address and size of
> +		    the register region. An optional second element specifies
> +		    the base address and size of the alias register region.
> +
> +
> +Example:
> +
> +	regulator@2099000 {
> +		compatible = "qcom,saw2";
> +		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
> +	};

I have the same general worry as with the ACC regarding the implicit
relationship between CPUs and the registers controlling them, but I
assume that's fine for current implementations, and the binding's so
simple there's nothing preventing future extension.

Acked-By: Mark Rutland <mark.rutland@arm.com>

Thanks,
Mark.

Re: [PATCH v2 4/9] ARM: Introduce CPU_METHOD_OF_DECLARE() for cpu hotplug/smp

[Mark Rutland]

On Tue, Dec 24, 2013 at 12:39:48AM +0000, Stephen Boyd wrote:
> The goal of multi-platform kernels is to remove the need for mach
> directories and machine descriptors. To further that goal,
> introduce CPU_METHOD_OF_DECLARE() to allow cpu hotplug/smp
> support to be separated from the machine descriptors.
> Implementers should specify an enable-method property in their
> cpus node and then implement a matching set of smp_ops in their
> hotplug/smp code, wiring it up with the CPU_METHOD_OF_DECLARE()
> macro. When the kernel is compiled we'll collect all the
> enable-method smp_ops into one section for use at boot.
> 
> At boot time we'll look for an enable-method in each cpu node and
> try to match that against all known CPU enable methods in the
> kernel. If there are no enable-methods in the cpu nodes we
> fallback to the cpus node and try to use any enable-method found
> there. If that doesn't work we fall back to the old way of using
> the machine descriptor.

Nice!

> 
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: <devicetree@vger.kernel.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
>  arch/arm/include/asm/smp.h        |  9 +++++++++
>  arch/arm/kernel/devtree.c         | 40 +++++++++++++++++++++++++++++++++++++++
>  include/asm-generic/vmlinux.lds.h | 10 ++++++++++
>  3 files changed, 59 insertions(+)
> 
> diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
> index 22a3b9b..772435b 100644
> --- a/arch/arm/include/asm/smp.h
> +++ b/arch/arm/include/asm/smp.h
> @@ -114,6 +114,15 @@ struct smp_operations {
>  #endif
>  };
>  
> +struct of_cpu_method {
> +	const char *method;
> +	struct smp_operations *ops;
> +};
> +
> +#define CPU_METHOD_OF_DECLARE(name, _method, _ops)			\
> +	static const struct of_cpu_method __cpu_method_of_table_##name	\
> +		__used __section(__cpu_method_of_table)			\
> +		= { .method = _method, .ops = _ops }
>  /*
>   * set platform specific SMP operations
>   */
> diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
> index 739c3df..91cc3f8 100644
> --- a/arch/arm/kernel/devtree.c
> +++ b/arch/arm/kernel/devtree.c
> @@ -18,6 +18,7 @@
>  #include <linux/of_fdt.h>
>  #include <linux/of_irq.h>
>  #include <linux/of_platform.h>
> +#include <linux/smp.h>
>  
>  #include <asm/cputype.h>
>  #include <asm/setup.h>
> @@ -63,6 +64,34 @@ void __init arm_dt_memblock_reserve(void)
>  	}
>  }
>  
> +#ifdef CONFIG_SMP
> +extern struct of_cpu_method __cpu_method_of_table_begin[];
> +extern struct of_cpu_method __cpu_method_of_table_end[];
> +
> +static int __init set_smp_ops_by_method(struct device_node *node)
> +{
> +	const char *method;
> +	struct of_cpu_method *m = __cpu_method_of_table_begin;
> +
> +	if (of_property_read_string(node, "enable-method", &method))
> +		return 0;
> +
> +	for (; m < __cpu_method_of_table_end; m++)
> +		if (!strcmp(m->method, method)) {
> +			smp_set_ops(m->ops);
> +			return 1;
> +		}
> +
> +	return 0;
> +}
> +#else
> +static inline int set_smp_ops_by_method(struct device_node *node)
> +{
> +	return 1;
> +}
> +#endif

I was going to comment that this would look nicer using an error code or
0, rather than 0 or 1, but I see that would make the call sites more
complicated / less legible.

> +
> +
>  /*
>   * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
>   * and builds the cpu logical map array containing MPIDR values related to
> @@ -79,6 +108,7 @@ void __init arm_dt_init_cpu_maps(void)
>  	 * read as 0.
>  	 */
>  	struct device_node *cpu, *cpus;
> +	int found_method = 0;
>  	u32 i, j, cpuidx = 1;
>  	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
>  
> @@ -150,8 +180,18 @@ void __init arm_dt_init_cpu_maps(void)
>  		}
>  
>  		tmp_map[i] = hwid;
> +
> +		if (!found_method)
> +			found_method = set_smp_ops_by_method(cpu);
>  	}
>  
> +	/*
> +	 * Fallback to an enable-method in the cpus node if nothing found in
> +	 * a cpu node.
> +	 */
> +	if (!found_method)
> +		set_smp_ops_by_method(cpus);
> +
>  	if (!bootcpu_valid) {
>  		pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n");
>  		return;
> diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
> index bc2121f..bd02ca7 100644
> --- a/include/asm-generic/vmlinux.lds.h
> +++ b/include/asm-generic/vmlinux.lds.h
> @@ -167,6 +167,15 @@
>  #define CLK_OF_TABLES()
>  #endif
>  
> +#ifdef CONFIG_SMP
> +#define CPU_METHOD_OF_TABLES() . = ALIGN(8);				    \
> +			   VMLINUX_SYMBOL(__cpu_method_of_table_begin) = .; \
> +			   *(__cpu_method_of_table)			    \
> +			   VMLINUX_SYMBOL(__cpu_method_of_table_end) = .;
> +#else
> +#define CPU_METHOD_OF_TABLES()
> +#endif

I suspect we'll use this on arm64 in future, where we might need this
even on UP systems (for PSCI's cpu_suspend method). However, I think
that can change that as and when we require it.

> +
>  #define KERNEL_DTB()							\
>  	STRUCT_ALIGN();							\
>  	VMLINUX_SYMBOL(__dtb_start) = .;				\
> @@ -491,6 +500,7 @@
>  	MEM_DISCARD(init.rodata)					\
>  	CLK_OF_TABLES()							\
>  	CLKSRC_OF_TABLES()						\
> +	CPU_METHOD_OF_TABLES()						\
>  	KERNEL_DTB()							\
>  	IRQCHIP_OF_MATCH_TABLE()

Enthusiastically Acked-by: Mark Rutland <mark.rutland@arm.com>

Cheers,
Mark.

Re: [PATCH v2 0/9] CPU enable method based SMP/hotplug + MSM conversion

[Mark Rutland]

Hi Stephen,

On Mon, Jan 06, 2014 at 10:19:11PM +0000, Stephen Boyd wrote:
> Ping? Can anyone take a look at the generic ARM and DT binding patches
> and provide acks/reviews? I'd like to send this through arm-soc via the
> MSM tree if possible.

Apologies for the delay. It's taking a while to warm up after christmas.

> 
> On 12/23/13 16:39, Stephen Boyd wrote:
> > This is a rework of patches sent a months back by Rohit[1].
> > The goal of these patches is to add support for SMP and (basic)
> > hotplug on MSM based SoCs. To get there, we add support for a
> > generic way to hook in SMP/hotplug support code based on DT. To
> > show how it's used, we convert the MSM8660 SMP support code over
> > to the new method. After that we add support for the rest of the
> > upstream MSM SoCs (note these patches are piled high on top of
> > Rohit's patches to add 8074 support to MSM[2] and my follow ups[3,4],
> > but this should only matter to the MSM maintainers).
> >
> > This is one of the last items of code that still requires us to have
> > a mach directory and a machine descriptor. We should be able to move
> > the hotplug/smp code out of mach directories if this approach is
> > accepted.

Thanks for doing the rework. This looks really good to me now.

I'd gotten myself confused while reading the bindings, but having now
had a look over the dts files my concerns were invalid.

Hopefully we can move more platforms to use enable-methods now :)

Cheers,
Mark.

Re: [PATCH v2 3/9] devicetree: bindings: Document qcom,saw2 node

[Mark Rutland]

On Wed, Jan 08, 2014 at 02:36:26PM +0000, Mark Rutland wrote:
> On Tue, Dec 24, 2013 at 12:39:47AM +0000, Stephen Boyd wrote:
> > The saw2 binding describes the SPM/AVS wrapper hardware used to
> > control the regulator supplying voltage to the Krait CPUs.
> > 
> > Cc: <devicetree@vger.kernel.org>
> > Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> > ---
> >  .../devicetree/bindings/arm/msm/qcom,saw2.txt      | 35 ++++++++++++++++++++++
> >  1 file changed, 35 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
> > new file mode 100644
> > index 0000000..1505fb8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
> > @@ -0,0 +1,35 @@
> > +SPM AVS Wrapper 2 (SAW2)
> > +
> > +The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
> > +Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
> > +micro-controller that transitions a piece of hardware (like a processor or
> > +subsystem) into and out of low power modes via a direct connection to
> > +the PMIC. It can also be wired up to interact with other processors in the
> > +system, notifying them when a low power state is entered or exited.
> > +
> > +PROPERTIES
> > +
> > +- compatible:
> > +	Usage: required
> > +	Value type: <string>
> > +	Definition: shall contain "qcom,saw2". A more specific value should be
> > +		    one of:
> > +			 "qcom,saw2-v1"
> > +			 "qcom,saw2-v1.1"
> > +			 "qcom,saw2-v2"
> > +			 "qcom,saw2-v2.1"
> > +
> > +- reg:
> > +	Usage: required
> > +	Value type: <prop-encoded-array>
> > +	Definition: the first element specifies the base address and size of
> > +		    the register region. An optional second element specifies
> > +		    the base address and size of the alias register region.
> > +
> > +
> > +Example:
> > +
> > +	regulator@2099000 {
> > +		compatible = "qcom,saw2";
> > +		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
> > +	};
> 
> I have the same general worry as with the ACC regarding the implicit
> relationship between CPUs and the registers controlling them, but I
> assume that's fine for current implementations, and the binding's so
> simple there's nothing preventing future extension.

Having looked at the dts files I see each CPU has its own SAW phandle,
so the above comments are irrelevant.

Thanks,
Mark.

Re: [PATCH v2 0/9] CPU enable method based SMP/hotplug + MSM conversion

[Arnd Bergmann]

On Tuesday 24 December 2013, Stephen Boyd wrote:
> This is a rework of patches sent a months back by Rohit[1].
> The goal of these patches is to add support for SMP and (basic)
> hotplug on MSM based SoCs. To get there, we add support for a
> generic way to hook in SMP/hotplug support code based on DT. To
> show how it's used, we convert the MSM8660 SMP support code over
> to the new method. After that we add support for the rest of the
> upstream MSM SoCs (note these patches are piled high on top of
> Rohit's patches to add 8074 support to MSM[2] and my follow ups[3,4],
> but this should only matter to the MSM maintainers).
> 
> This is one of the last items of code that still requires us to have
> a mach directory and a machine descriptor. We should be able to move
> the hotplug/smp code out of mach directories if this approach is
> accepted.

The implementation looks ok to me, but I wonder whether on a global
scale we want to tie it more closely to the cpuidle implementations.
We already have a drivers/cpuidle framework, and while I admit
that I'm not familiar with the code in there, I would assume that
the smp operations and the cpuidle code usually go hand in hand.

	Arnd

Re: [PATCH v2 2/9] devicetree: bindings: Document qcom,kpss-acc

[Stephen Boyd]

On 01/08/14 06:32, Mark Rutland wrote:
> On Wed, Jan 08, 2014 at 02:25:41PM +0000, Mark Rutland wrote:
>> On Tue, Dec 24, 2013 at 12:39:46AM +0000, Stephen Boyd wrote:
>>> The kpss acc binding describes the clock, reset, and power domain
>>> controller for a Krait CPU.
>>>
>>> Cc: <devicetree@vger.kernel.org>
>>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>>> ---
>>>  .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt  | 30 ++++++++++++++++++++++
>>>  1 file changed, 30 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
>>> new file mode 100644
>>> index 0000000..1333db9
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
>>> @@ -0,0 +1,30 @@
>>> +Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
>>> +
>>> +The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
>>> +There is one ACC register region per CPU within the KPSS remapped region as
>>> +well as an alias register region that remaps accesses to the ACC associated
>>> +with the CPU accessing the region.
>> Is the mapping of ACC register to a specific processor well-defined? I
>> assume it's just in order of MPIDR.Aff0.
>>
>> To maintain our collective sanity in the face of possible future
>> implementations, do you have an idea as to whether this might need to be
>> extended in future for multiple clusters / reordered IDs and so on?
>>
>> I assume we'd just allocate a new compatible string if those get a
>> little crazy.
> Actually, I'm getting too hung-up on future-proofing. Assuming the
> mapping is well-defined for current implementations we can always add an
> additional property later if required.
>
> Acked-by: Mark Rutland <mark.rutland@arm.com>
>
>

Thanks Mark. As far as I know it will always be a one to one
relationship. I can't predict the future though so you're suggestion
seems like a good escape plan if needed.

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Re: [PATCH v2 1/9] devicetree: bindings: Document Krait/Scorpion cpus and enable-method

[Stephen Boyd]

On 01/08/14 06:21, Mark Rutland wrote:
> On Tue, Dec 24, 2013 at 12:39:45AM +0000, Stephen Boyd wrote:
>> From: Rohit Vaswani <rvaswani@codeaurora.org>
>>
>> Scorpion and Krait don't use the spin-table enable-method.
>> Instead they rely on mmio register accesses to enable power and
>> clocks to bring CPUs out of reset. Document their enable-methods.
>>
>> Cc: <devicetree@vger.kernel.org>
>> Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
>> [sboyd: Split off into separate patch, renamed methods to
>> match compatible nodes]
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>>  Documentation/devicetree/bindings/arm/cpus.txt | 25 ++++++++++++++++++++++++-
>>  1 file changed, 24 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 9130435..333f4ae 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -180,7 +180,11 @@ nodes to be present and contain the properties described below.
>>  			  be one of:
>>  			     "spin-table"
>>  			     "psci"
>> -			# On ARM 32-bit systems this property is optional.
>> +			# On ARM 32-bit systems this property is optional and
>> +			  can be one of:
>> +			    "qcom,gcc-msm8660"
>> +			    "qcom,kpss-acc-v1"
>> +			    "qcom,kpss-acc-v2"
> It would be nice to document "psci" here as valid for 32-bit.
>
> Currently the PSCI code doesn't inspect the enable-method and assumes it
> if there's a psci node, but KVM tool and others set enable-method to
> "psci", and if we change the way the PSCI code probes it will require
> enable-method to be set for PSCI to work.

Sure. I'll squash it in if I resend, or send a follow-up patch later on.

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Re: [PATCH v2 0/9] CPU enable method based SMP/hotplug + MSM conversion

[Stephen Boyd]

On 01/08/14 13:37, Arnd Bergmann wrote:
> On Tuesday 24 December 2013, Stephen Boyd wrote:
>> This is a rework of patches sent a months back by Rohit[1].
>> The goal of these patches is to add support for SMP and (basic)
>> hotplug on MSM based SoCs. To get there, we add support for a
>> generic way to hook in SMP/hotplug support code based on DT. To
>> show how it's used, we convert the MSM8660 SMP support code over
>> to the new method. After that we add support for the rest of the
>> upstream MSM SoCs (note these patches are piled high on top of
>> Rohit's patches to add 8074 support to MSM[2] and my follow ups[3,4],
>> but this should only matter to the MSM maintainers).
>>
>> This is one of the last items of code that still requires us to have
>> a mach directory and a machine descriptor. We should be able to move
>> the hotplug/smp code out of mach directories if this approach is
>> accepted.
> The implementation looks ok to me, but I wonder whether on a global
> scale we want to tie it more closely to the cpuidle implementations.
> We already have a drivers/cpuidle framework, and while I admit
> that I'm not familiar with the code in there, I would assume that
> the smp operations and the cpuidle code usually go hand in hand.

Sure. Right now the smp ops code is fairly well tied into the arch layer
so it sounds like there is some future work when we move this stuff out
of the mach directory.

Would arm-soc be able to pick these patches up for 3.14? I think
everything is in place for these patches now that Mark has reviewed them.

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Re: [PATCH v2 0/9] CPU enable method based SMP/hotplug + MSM conversion

[Kumar Gala]

On Jan 8, 2014, at 7:50 PM, Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:

> On 01/08/14 13:37, Arnd Bergmann wrote:
>> On Tuesday 24 December 2013, Stephen Boyd wrote:
>>> This is a rework of patches sent a months back by Rohit[1].
>>> The goal of these patches is to add support for SMP and (basic)
>>> hotplug on MSM based SoCs. To get there, we add support for a
>>> generic way to hook in SMP/hotplug support code based on DT. To
>>> show how it's used, we convert the MSM8660 SMP support code over
>>> to the new method. After that we add support for the rest of the
>>> upstream MSM SoCs (note these patches are piled high on top of
>>> Rohit's patches to add 8074 support to MSM[2] and my follow ups[3,4],
>>> but this should only matter to the MSM maintainers).
>>> 
>>> This is one of the last items of code that still requires us to have
>>> a mach directory and a machine descriptor. We should be able to move
>>> the hotplug/smp code out of mach directories if this approach is
>>> accepted.
>> The implementation looks ok to me, but I wonder whether on a global
>> scale we want to tie it more closely to the cpuidle implementations.
>> We already have a drivers/cpuidle framework, and while I admit
>> that I'm not familiar with the code in there, I would assume that
>> the smp operations and the cpuidle code usually go hand in hand.
> 
> Sure. Right now the smp ops code is fairly well tied into the arch layer
> so it sounds like there is some future work when we move this stuff out
> of the mach directory.
> 
> Would arm-soc be able to pick these patches up for 3.14? I think
> everything is in place for these patches now that Mark has reviewed them.

Ping, wondering if arm-soc would pick up:

 ARM: Introduce CPU_METHOD_OF_DECLARE() for cpu hotplug/smp

The other patches are all msm specific so we can handle them through the normal channels.

- k

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[PATCH v2 10/9] ARM: msm: Remove board-dt.c

[Stephen Boyd]

The default machine descriptor satisfies our needs now that the
SMP ops are set based on the enable-method in devicetree and we're
part of the multiplatform kernel. Drop this file.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/mach-msm/Makefile   |  1 -
 arch/arm/mach-msm/board-dt.c | 27 ---------------------------
 2 files changed, 28 deletions(-)
 delete mode 100644 arch/arm/mach-msm/board-dt.c

diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 721f27f50d96..e6b33cca67c2 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -26,6 +26,5 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
-obj-$(CONFIG_ARCH_MSM_DT) += board-dt.o
 obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
diff --git a/arch/arm/mach-msm/board-dt.c b/arch/arm/mach-msm/board-dt.c
deleted file mode 100644
index 1e3af2ba9981..000000000000
--- a/arch/arm/mach-msm/board-dt.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Copyright (c) 2010-2012,2013 The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/init.h>
-
-#include <asm/mach/arch.h>
-
-static const char * const msm_dt_match[] __initconst = {
-	"qcom,msm8660-fluid",
-	"qcom,msm8660-surf",
-	"qcom,msm8960-cdp",
-	"qcom,apq8074-dragonboard",
-	NULL
-};
-
-DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
-	.dt_compat = msm_dt_match,
-MACHINE_END
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