* [PATCH 0/3] phy: qualcomm: support IPQ60xx USB PHY @ 2021-01-27 14:20 Baruch Siach 2021-01-27 14:20 ` [PATCH 1/3] phy: qcom-qusb2: add QUSB2 support for IPQ6018 Baruch Siach ` (3 more replies) 0 siblings, 4 replies; 8+ messages in thread From: Baruch Siach @ 2021-01-27 14:20 UTC (permalink / raw) To: Kishon Vijay Abraham I, Vinod Koul Cc: Baruch Siach, Andy Gross, Bjorn Andersson, Kathiravan T, linux-arm-msm, linux-arm-kernel The short series adds support for USB PHY on IPQ60xx based platforms. Tested on CP01 board. The code is forward-ported from downstream codeaurora kernel at https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/ Baruch Siach (1): dt-bindings: phy: qcom,qusb2: document ipq6018 compatible Kathiravan T (2): phy: qcom-qusb2: add QUSB2 support for IPQ6018 arm64: dts: ipq6018: enable USB2 support .../bindings/phy/qcom,qusb2-phy.yaml | 1 + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 8 ++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qusb2.c | 44 +++++++++++++++++ 4 files changed, 101 insertions(+) -- 2.29.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/3] phy: qcom-qusb2: add QUSB2 support for IPQ6018 2021-01-27 14:20 [PATCH 0/3] phy: qualcomm: support IPQ60xx USB PHY Baruch Siach @ 2021-01-27 14:20 ` Baruch Siach 2021-01-27 14:20 ` [PATCH 2/3] dt-bindings: phy: qcom,qusb2: document ipq6018 compatible Baruch Siach ` (2 subsequent siblings) 3 siblings, 0 replies; 8+ messages in thread From: Baruch Siach @ 2021-01-27 14:20 UTC (permalink / raw) To: Kishon Vijay Abraham I, Vinod Koul Cc: Kathiravan T, Baruch Siach, Andy Gross, Bjorn Andersson, linux-arm-msm, linux-arm-kernel From: Kathiravan T <kathirav@codeaurora.org> Add the phy init sequence for the Super Speed ports found on IPQ6018. Signed-off-by: Kathiravan T <kathirav@codeaurora.org> [baruch: add ipq6018_regs_layout[], drop binding change] Signed-off-by: Baruch Siach <baruch@tkos.co.il> --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index 719e0888ed87..8f1bf7e2186b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -22,6 +22,7 @@ #include <dt-bindings/phy/phy-qcom-qusb2.h> +#define QUSB2PHY_PLL 0x0 #define QUSB2PHY_PLL_TEST 0x04 #define CLK_REF_SEL BIT(7) @@ -135,6 +136,35 @@ enum qusb2phy_reg_layout { QUSB2PHY_INTR_CTRL, }; +static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = { + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F), +}; + +static const unsigned int ipq6018_regs_layout[] = { + [QUSB2PHY_PLL_STATUS] = 0x38, + [QUSB2PHY_PORT_TUNE1] = 0x80, + [QUSB2PHY_PORT_TUNE2] = 0x84, + [QUSB2PHY_PORT_TUNE3] = 0x88, + [QUSB2PHY_PORT_TUNE4] = 0x8C, + [QUSB2PHY_PORT_TUNE5] = 0x90, + [QUSB2PHY_PORT_TEST1] = 0x98, + [QUSB2PHY_PORT_TEST2] = 0x9C, + [QUSB2PHY_PORT_POWERDOWN] = 0xB4, + [QUSB2PHY_INTR_CTRL] = 0xBC, +}; + static const unsigned int msm8996_regs_layout[] = { [QUSB2PHY_PLL_STATUS] = 0x38, [QUSB2PHY_PORT_TUNE1] = 0x80, @@ -275,6 +305,17 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = { .update_tune1_with_efuse = true, }; +static const struct qusb2_phy_cfg ipq6018_phy_cfg = { + .tbl = ipq6018_init_tbl, + .tbl_num = ARRAY_SIZE(ipq6018_init_tbl), + .regs = ipq6018_regs_layout, + + .disable_ctrl = POWER_DOWN, + .mask_core_ready = PLL_LOCKED, + /* autoresume not used */ + .autoresume_en = BIT(0), +}; + static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { .tbl = qusb2_v2_init_tbl, .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), @@ -833,6 +874,9 @@ static const struct phy_ops qusb2_phy_gen_ops = { static const struct of_device_id qusb2_phy_of_match_table[] = { { + .compatible = "qcom,ipq6018-qusb2-phy", + .data = &ipq6018_phy_cfg, + }, { .compatible = "qcom,ipq8074-qusb2-phy", .data = &msm8996_phy_cfg, }, { -- 2.29.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] dt-bindings: phy: qcom,qusb2: document ipq6018 compatible 2021-01-27 14:20 [PATCH 0/3] phy: qualcomm: support IPQ60xx USB PHY Baruch Siach 2021-01-27 14:20 ` [PATCH 1/3] phy: qcom-qusb2: add QUSB2 support for IPQ6018 Baruch Siach @ 2021-01-27 14:20 ` Baruch Siach 2021-01-27 14:20 ` [PATCH 3/3] arm64: dts: ipq6018: enable USB2 support Baruch Siach 2021-02-04 7:50 ` [PATCH 0/3] phy: qualcomm: support IPQ60xx USB PHY Vinod Koul 3 siblings, 0 replies; 8+ messages in thread From: Baruch Siach @ 2021-01-27 14:20 UTC (permalink / raw) To: Kishon Vijay Abraham I, Vinod Koul Cc: Baruch Siach, Andy Gross, Bjorn Andersson, Kathiravan T, linux-arm-msm, linux-arm-kernel This compatible string is for the USB PHY on IPQ60xx systems. Signed-off-by: Baruch Siach <baruch@tkos.co.il> --- Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index 582abbbd8b32..9f9cf07b7d45 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -22,6 +22,7 @@ properties: - qcom,msm8996-qusb2-phy - qcom,msm8998-qusb2-phy - qcom,sdm660-qusb2-phy + - qcom,ipq6018-qusb2-phy - items: - enum: - qcom,sc7180-qusb2-phy -- 2.29.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] arm64: dts: ipq6018: enable USB2 support 2021-01-27 14:20 [PATCH 0/3] phy: qualcomm: support IPQ60xx USB PHY Baruch Siach 2021-01-27 14:20 ` [PATCH 1/3] phy: qcom-qusb2: add QUSB2 support for IPQ6018 Baruch Siach 2021-01-27 14:20 ` [PATCH 2/3] dt-bindings: phy: qcom,qusb2: document ipq6018 compatible Baruch Siach @ 2021-01-27 14:20 ` Baruch Siach 2021-02-05 6:09 ` Kathiravan T 2021-02-04 7:50 ` [PATCH 0/3] phy: qualcomm: support IPQ60xx USB PHY Vinod Koul 3 siblings, 1 reply; 8+ messages in thread From: Baruch Siach @ 2021-01-27 14:20 UTC (permalink / raw) To: Kishon Vijay Abraham I, Vinod Koul Cc: Kathiravan T, Baruch Siach, Andy Gross, Bjorn Andersson, linux-arm-msm, linux-arm-kernel From: Kathiravan T <kathirav@codeaurora.org> Signed-off-by: Kathiravan T <kathirav@codeaurora.org> [baruch: adjust regs address/size; drop binding updates; drop unsupported quirk properties] Signed-off-by: Baruch Siach <baruch@tkos.co.il> --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 8 ++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48 ++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index 99cefe88f6f2..5aec18308712 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -78,3 +78,11 @@ nand@0 { nand-bus-width = <8>; }; }; + +&qusb_phy_1 { + status = "ok"; +}; + +&usb2 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9fa5b028e4f3..d4a3d4e4a7e9 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -524,6 +524,54 @@ qrtr_requests { }; }; + qusb_phy_1: qusb@59000 { + compatible = "qcom,ipq6018-qusb2-phy"; + reg = <0x0 0x059000 0x0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, + <&xo>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; + status = "disabled"; + }; + + usb2: usb2@7000000 { + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + reg = <0x0 0x070F8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_SLEEP_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + clock-names = "master", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <24000000>; + resets = <&gcc GCC_USB1_BCR>; + status = "disabled"; + + dwc_1: dwc3@7000000 { + compatible = "snps,dwc3"; + reg = <0x0 0x7000000 0x0 0xcd00>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_1>; + phy-names = "usb2-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + }; wcss: wcss-smp2p { -- 2.29.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] arm64: dts: ipq6018: enable USB2 support 2021-01-27 14:20 ` [PATCH 3/3] arm64: dts: ipq6018: enable USB2 support Baruch Siach @ 2021-02-05 6:09 ` Kathiravan T 2021-02-07 9:08 ` Baruch Siach 0 siblings, 1 reply; 8+ messages in thread From: Kathiravan T @ 2021-02-05 6:09 UTC (permalink / raw) To: Baruch Siach Cc: Kishon Vijay Abraham I, Vinod Koul, Andy Gross, Bjorn Andersson, linux-arm-msm, linux-arm-kernel On 2021-01-27 19:50, Baruch Siach wrote: > From: Kathiravan T <kathirav@codeaurora.org> > > Signed-off-by: Kathiravan T <kathirav@codeaurora.org> > [baruch: adjust regs address/size; drop binding updates; > drop unsupported quirk properties] > Signed-off-by: Baruch Siach <baruch@tkos.co.il> > --- > arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 8 ++++ > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48 ++++++++++++++++++++ > 2 files changed, 56 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > index 99cefe88f6f2..5aec18308712 100644 > --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > @@ -78,3 +78,11 @@ nand@0 { > nand-bus-width = <8>; > }; > }; > + > +&qusb_phy_1 { > + status = "ok"; > +}; > + > +&usb2 { > + status = "ok"; > +}; > diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi > b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > index 9fa5b028e4f3..d4a3d4e4a7e9 100644 > --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > @@ -524,6 +524,54 @@ qrtr_requests { > }; > }; > > + qusb_phy_1: qusb@59000 { > + compatible = "qcom,ipq6018-qusb2-phy"; > + reg = <0x0 0x059000 0x0 0x180>; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, > + <&xo>; > + clock-names = "cfg_ahb", "ref"; As per the bindings, ref clock should be 19.2MHz where the XO in IPQ60xx is 24MHz. Did the USB enumerated successfully and able to perform read / write operations? Thanks, Kathiravan T. > + > + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; > + status = "disabled"; > + }; > + > + usb2: usb2@7000000 { > + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; > + reg = <0x0 0x070F8800 0x0 0x400>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + clocks = <&gcc GCC_USB1_MASTER_CLK>, > + <&gcc GCC_USB1_SLEEP_CLK>, > + <&gcc GCC_USB1_MOCK_UTMI_CLK>; > + clock-names = "master", > + "sleep", > + "mock_utmi"; > + > + assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, > + <&gcc GCC_USB1_MOCK_UTMI_CLK>; > + assigned-clock-rates = <133330000>, > + <24000000>; > + resets = <&gcc GCC_USB1_BCR>; > + status = "disabled"; > + > + dwc_1: dwc3@7000000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0x7000000 0x0 0xcd00>; > + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&qusb_phy_1>; > + phy-names = "usb2-phy"; > + tx-fifo-resize; > + snps,is-utmi-l1-suspend; > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + dr_mode = "host"; > + }; > + }; > + > }; > > wcss: wcss-smp2p { -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] arm64: dts: ipq6018: enable USB2 support 2021-02-05 6:09 ` Kathiravan T @ 2021-02-07 9:08 ` Baruch Siach 2021-02-08 5:44 ` Kathiravan T 0 siblings, 1 reply; 8+ messages in thread From: Baruch Siach @ 2021-02-07 9:08 UTC (permalink / raw) To: Kathiravan T Cc: Kishon Vijay Abraham I, Vinod Koul, Andy Gross, Bjorn Andersson, linux-arm-msm, linux-arm-kernel, Balaji Prakash J Hi Kathiravan T, Thanks for your review. On Fri, Feb 05 2021, Kathiravan T wrote: > On 2021-01-27 19:50, Baruch Siach wrote: >> From: Kathiravan T <kathirav@codeaurora.org> >> Signed-off-by: Kathiravan T <kathirav@codeaurora.org> >> [baruch: adjust regs address/size; drop binding updates; >> drop unsupported quirk properties] >> Signed-off-by: Baruch Siach <baruch@tkos.co.il> >> --- >> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 8 ++++ >> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48 ++++++++++++++++++++ >> 2 files changed, 56 insertions(+) >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> index 99cefe88f6f2..5aec18308712 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> @@ -78,3 +78,11 @@ nand@0 { >> nand-bus-width = <8>; >> }; >> }; >> + >> +&qusb_phy_1 { >> + status = "ok"; >> +}; >> + >> +&usb2 { >> + status = "ok"; >> +}; >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> b/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> index 9fa5b028e4f3..d4a3d4e4a7e9 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> @@ -524,6 +524,54 @@ qrtr_requests { >> }; >> }; >> + qusb_phy_1: qusb@59000 { >> + compatible = "qcom,ipq6018-qusb2-phy"; >> + reg = <0x0 0x059000 0x0 0x180>; >> + #phy-cells = <0>; >> + >> + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, >> + <&xo>; >> + clock-names = "cfg_ahb", "ref"; > > As per the bindings, ref clock should be 19.2MHz where the XO in IPQ60xx is > 24MHz. Did the USB enumerated successfully and able to perform read / write > operations? I managed to enumerate an Ethernet USB dongle with only this series applied. But then I tested again with USB storage device. That only worked with downstream clock adjust/period patch: https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/commit/?h=fig&id=707d8fa2b481888f4792edc6561e81999301cbcf That patch applies cleanly on top of v5.11-rc4. Is anyone at Codeaurora pushing the dwc3 clock patch upstream? Should I do that? Thanks, baruch -- ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il - ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] arm64: dts: ipq6018: enable USB2 support 2021-02-07 9:08 ` Baruch Siach @ 2021-02-08 5:44 ` Kathiravan T 0 siblings, 0 replies; 8+ messages in thread From: Kathiravan T @ 2021-02-08 5:44 UTC (permalink / raw) To: Baruch Siach Cc: Kishon Vijay Abraham I, Vinod Koul, Andy Gross, Bjorn Andersson, linux-arm-msm, linux-arm-kernel, Balaji Prakash J On 2021-02-07 14:38, Baruch Siach wrote: > Hi Kathiravan T, > > Thanks for your review. > > On Fri, Feb 05 2021, Kathiravan T wrote: >> On 2021-01-27 19:50, Baruch Siach wrote: >>> From: Kathiravan T <kathirav@codeaurora.org> >>> Signed-off-by: Kathiravan T <kathirav@codeaurora.org> >>> [baruch: adjust regs address/size; drop binding updates; >>> drop unsupported quirk properties] >>> Signed-off-by: Baruch Siach <baruch@tkos.co.il> >>> --- >>> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 8 ++++ >>> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48 >>> ++++++++++++++++++++ >>> 2 files changed, 56 insertions(+) >>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >>> b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >>> index 99cefe88f6f2..5aec18308712 100644 >>> --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >>> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >>> @@ -78,3 +78,11 @@ nand@0 { >>> nand-bus-width = <8>; >>> }; >>> }; >>> + >>> +&qusb_phy_1 { >>> + status = "ok"; >>> +}; >>> + >>> +&usb2 { >>> + status = "ok"; >>> +}; >>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi >>> b/arch/arm64/boot/dts/qcom/ipq6018.dtsi >>> index 9fa5b028e4f3..d4a3d4e4a7e9 100644 >>> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi >>> @@ -524,6 +524,54 @@ qrtr_requests { >>> }; >>> }; >>> + qusb_phy_1: qusb@59000 { >>> + compatible = "qcom,ipq6018-qusb2-phy"; >>> + reg = <0x0 0x059000 0x0 0x180>; >>> + #phy-cells = <0>; >>> + >>> + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, >>> + <&xo>; >>> + clock-names = "cfg_ahb", "ref"; >> >> As per the bindings, ref clock should be 19.2MHz where the XO in >> IPQ60xx is >> 24MHz. Did the USB enumerated successfully and able to perform read / >> write >> operations? > > I managed to enumerate an Ethernet USB dongle with only this series > applied. But then I tested again with USB storage device. That only > worked with downstream clock adjust/period patch: > > > https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/commit/?h=fig&id=707d8fa2b481888f4792edc6561e81999301cbcf > > That patch applies cleanly on top of v5.11-rc4. > > Is anyone at Codeaurora pushing the dwc3 clock patch upstream? Should I > do that? Sure, please go ahead. > > Thanks, > baruch -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/3] phy: qualcomm: support IPQ60xx USB PHY 2021-01-27 14:20 [PATCH 0/3] phy: qualcomm: support IPQ60xx USB PHY Baruch Siach ` (2 preceding siblings ...) 2021-01-27 14:20 ` [PATCH 3/3] arm64: dts: ipq6018: enable USB2 support Baruch Siach @ 2021-02-04 7:50 ` Vinod Koul 3 siblings, 0 replies; 8+ messages in thread From: Vinod Koul @ 2021-02-04 7:50 UTC (permalink / raw) To: Baruch Siach Cc: Kishon Vijay Abraham I, Andy Gross, Bjorn Andersson, Kathiravan T, linux-arm-msm, linux-arm-kernel On 27-01-21, 16:20, Baruch Siach wrote: > The short series adds support for USB PHY on IPQ60xx based platforms. Tested > on CP01 board. > > The code is forward-ported from downstream codeaurora kernel at > > https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/ Applied driver and binding patch, thanks DT can be picked by Bjorn -- ~Vinod ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-02-08 5:45 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-01-27 14:20 [PATCH 0/3] phy: qualcomm: support IPQ60xx USB PHY Baruch Siach 2021-01-27 14:20 ` [PATCH 1/3] phy: qcom-qusb2: add QUSB2 support for IPQ6018 Baruch Siach 2021-01-27 14:20 ` [PATCH 2/3] dt-bindings: phy: qcom,qusb2: document ipq6018 compatible Baruch Siach 2021-01-27 14:20 ` [PATCH 3/3] arm64: dts: ipq6018: enable USB2 support Baruch Siach 2021-02-05 6:09 ` Kathiravan T 2021-02-07 9:08 ` Baruch Siach 2021-02-08 5:44 ` Kathiravan T 2021-02-04 7:50 ` [PATCH 0/3] phy: qualcomm: support IPQ60xx USB PHY Vinod Koul
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