[PATCH v2 0/3] arm64: dts: qcom: Add mpss support to QDU1000/QRU1000 SoCs

[PATCH v2 0/3] arm64: dts: qcom: Add mpss support to QDU1000/QRU1000 SoCs

[Melody Olvera]

This adds support for the mpss found in the QDU1000 and QRU1000 SoCs.
It needs an RMB register space to be specified to enable a handshake
with the mpss to late attach the device. The firmware file paths are
also added in the IDP board DTs.

This patch set depends on the bindings from [1].

[1] https://lore.kernel.org/all/20230306231202.12223-1-quic_molvera@quicinc.com/

Changes from v1:
* Removed power domain cells from aoss qmp node
* Renamed firmwares to follow convention

Melody Olvera (3):
  arm64: dts: qcom: qdu1000: Add IPCC, MPSS, AOSS nodes
  arm64: dts: qcom: qdu1000-idp: Enable mpss
  arm64: dts: qcom: qru1000-idp: Enable mpss

 arch/arm64/boot/dts/qcom/qdu1000-idp.dts |   6 ++
 arch/arm64/boot/dts/qcom/qdu1000.dtsi    | 104 +++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/qru1000-idp.dts |   6 ++
 3 files changed, 116 insertions(+)


base-commit: dc837c1a5137a8cf2e9432c1891392b6a66f4d8d
prerequisite-patch-id: ddc43db334e06b6938219e12964a5e943641126d
prerequisite-patch-id: 7c8c18aef7f693eb0749ee9f296bfb59ca202eb7
prerequisite-patch-id: a87ffdabbfee46017956f62034219e6a0cb01724
prerequisite-patch-id: 3a012cc3a5b28208ecf23b2a1b5a0310d15aa4ac
prerequisite-patch-id: ad32654fa37f8c5fb00162d093b577f81a511bd0
prerequisite-patch-id: d699495a3b22bb97c9d114024a82a9fadcc40082
prerequisite-patch-id: def4c2cb2a10130f67cdfb90f9c2de3d3d738f77
-- 
2.25.1

[PATCH v2 1/3] arm64: dts: qcom: qdu1000: Add IPCC, MPSS, AOSS nodes

[Melody Olvera]

Add nodes for IPCC, MPSS, and AOSS drivers. Also update
the scm node to include its interconnect.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qdu1000.dtsi | 104 ++++++++++++++++++++++++++
 1 file changed, 104 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index f234159d2060..6cc96a7c33e8 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
@@ -141,6 +142,7 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
 	firmware {
 		scm {
 			compatible = "qcom,scm-qdu1000", "qcom,scm";
+			interconnects = <&system_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 		};
 	};
 
@@ -326,6 +328,11 @@ q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
 			no-map;
 		};
 
+		mpss_dsm_mem: mpss-dsm@9ec80000 {
+			reg = <0x0 0x9ec80000 0x0 0x880000>;
+			no-map;
+		};
+
 		tenx_mem: tenx@a0000000 {
 			reg = <0x0 0xa0000000 0x0 0x19600000>;
 			no-map;
@@ -347,6 +354,28 @@ ipa_buffer_mem: ipa-buffer@c3200000 {
 		};
 	};
 
+	smp2p-modem {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+		interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+					   IPCC_MPROC_SIGNAL_SMP2P
+					   IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		smp2p_modem_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_modem_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
 	soc: soc@0 {
 		compatible = "simple-bus";
 		#address-cells = <2>;
@@ -367,6 +396,15 @@ gcc: clock-controller@80000 {
 			#power-domain-cells = <1>;
 		};
 
+		ipcc: mailbox@408000 {
+			compatible = "qcom,qdu1000-ipcc", "qcom,ipcc";
+			reg = <0x0 0x408000 0x0 0x1000>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#mbox-cells = <2>;
+		};
+
 		gpi_dma0: dma-controller@900000  {
 			compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
 			reg = <0x0 0x900000 0x0 0x60000>;
@@ -842,6 +880,49 @@ tcsr_mutex: hwlock@1f40000 {
 			#hwlock-cells = <1>;
 		};
 
+		remoteproc_mpss: remoteproc@4080000 {
+			compatible = "qcom,qdu1000-mpss-pas";
+			reg = <0x0 0x4080000 0x0 0x4040>,
+			      <0x0 0x4180000 0x0 0x1000>;
+
+			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready", "handover",
+					  "stop-ack", "shutdown-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd QDU1000_CX>,
+					<&rpmhpd QDU1000_MSS>;
+			power-domain-names = "cx", "mss";
+
+			memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
+
+			interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_modem_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_MPSS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+				label = "modem";
+				qcom,remote-pid = <1>;
+			};
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,qdu1000-pdc", "qcom,pdc";
 			reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
@@ -852,6 +933,29 @@ pdc: interrupt-controller@b220000 {
 			interrupt-controller;
 		};
 
+		aoss_qmp: qmp@c300000 {
+			compatible = "qcom,qdu1000-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0x0 0xc300000 0x0 0x400>;
+			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
+						     IPCC_MPROC_SIGNAL_GLINK_QMP
+						     IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+			#clock-cells = <0>;
+
+			cx_cdev: cx {
+				#cooling-cells = <2>;
+			};
+
+			mx_cdev: mx {
+				#cooling-cells = <2>;
+			};
+
+			ebi_cdev: ebi {
+				#cooling-cells = <2>;
+			};
+		};
+
 		spmi_bus: spmi@c400000 {
 			compatible = "qcom,spmi-pmic-arb";
 			reg = <0x0 0xc400000 0x0 0x3000>,
-- 
2.25.1

[PATCH v2 2/3] arm64: dts: qcom: qdu1000-idp: Enable mpss

[Melody Olvera]

Add MPSS firmware paths for the QDU1000 IDP platform.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
index 9e9fd4b8023e..c012da026a10 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
@@ -448,6 +448,12 @@ &qupv3_id_0 {
 	status = "okay";
 };
 
+&remoteproc_mpss {
+	firmware-name = "qcom/qdu1000/modem.mbn",
+			"qcom/qdu1000/modem_dtb.mbn";
+	status = "okay";
+};
+
 &uart7 {
 	status = "okay";
 };
-- 
2.25.1

[PATCH v2 3/3] arm64: dts: qcom: qru1000-idp: Enable mpss

[Melody Olvera]

Add MPSS firmware paths for the QRU1000 IDP platform.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qru1000-idp.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
index 2cc893ae4d10..e5ba472bf553 100644
--- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
@@ -448,6 +448,12 @@ &qupv3_id_0 {
 	status = "okay";
 };
 
+&remoteproc_mpss {
+	firmware-name = "qcom/qru1000/modem.mbn",
+			"qcom/qru1000/modem_dtb.mbn";
+	status = "okay";
+};
+
 &uart7 {
 	status = "okay";
 };
-- 
2.25.1

Re: [PATCH v2 1/3] arm64: dts: qcom: qdu1000: Add IPCC, MPSS, AOSS nodes

[Konrad Dybcio]

On 7.03.2023 00:17, Melody Olvera wrote:
> Add nodes for IPCC, MPSS, and AOSS drivers. Also update
> the scm node to include its interconnect.
Quite a bit of stuff in a single commit, this could be
separated into:

- scm icc
- aoss+ipcc
- smp2p+mpss

> 
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qdu1000.dtsi | 104 ++++++++++++++++++++++++++
>  1 file changed, 104 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> index f234159d2060..6cc96a7c33e8 100644
> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/dma/qcom-gpi.h>
>  #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
>  #include <dt-bindings/power/qcom-rpmpd.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>  
> @@ -141,6 +142,7 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
>  	firmware {
>  		scm {
>  			compatible = "qcom,scm-qdu1000", "qcom,scm";
> +			interconnects = <&system_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
>  		};
>  	};
>  
> @@ -326,6 +328,11 @@ q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
>  			no-map;
>  		};
>  
> +		mpss_dsm_mem: mpss-dsm@9ec80000 {
> +			reg = <0x0 0x9ec80000 0x0 0x880000>;
> +			no-map;
> +		};
> +
>  		tenx_mem: tenx@a0000000 {
>  			reg = <0x0 0xa0000000 0x0 0x19600000>;
>  			no-map;
> @@ -347,6 +354,28 @@ ipa_buffer_mem: ipa-buffer@c3200000 {
>  		};
>  	};
>  
> +	smp2p-modem {
> +		compatible = "qcom,smp2p";
> +		qcom,smem = <435>, <428>;
> +		interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
> +					   IPCC_MPROC_SIGNAL_SMP2P
> +					   IRQ_TYPE_EDGE_RISING>;
Not sure if thunderfox is acting up again or the indentation here
is not quite right

> +		mboxes = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
> +		qcom,local-pid = <0>;
> +		qcom,remote-pid = <1>;
> +
> +		smp2p_modem_out: master-kernel {
> +			qcom,entry-name = "master-kernel";
> +			#qcom,smem-state-cells = <1>;
> +		};
> +
> +		smp2p_modem_in: slave-kernel {
> +			qcom,entry-name = "slave-kernel";
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +		};
> +	};
> +
>  	soc: soc@0 {
>  		compatible = "simple-bus";
>  		#address-cells = <2>;
> @@ -367,6 +396,15 @@ gcc: clock-controller@80000 {
>  			#power-domain-cells = <1>;
>  		};
>  
> +		ipcc: mailbox@408000 {
> +			compatible = "qcom,qdu1000-ipcc", "qcom,ipcc";
> +			reg = <0x0 0x408000 0x0 0x1000>;
The address part should be padded to 8 hex digits. I'd appreciate it
if you could submit a fixup for the other nodes in this dtsi!

> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			#mbox-cells = <2>;
> +		};
> +
>  		gpi_dma0: dma-controller@900000  {
>  			compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
>  			reg = <0x0 0x900000 0x0 0x60000>;
> @@ -842,6 +880,49 @@ tcsr_mutex: hwlock@1f40000 {
>  			#hwlock-cells = <1>;
>  		};
>  
> +		remoteproc_mpss: remoteproc@4080000 {
> +			compatible = "qcom,qdu1000-mpss-pas";
> +			reg = <0x0 0x4080000 0x0 0x4040>,
The address part should be padded to 8 hex digits

> +			      <0x0 0x4180000 0x0 0x1000>;
No reg-names?

> +
> +			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
> +					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
> +					      <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
> +					      <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
> +					      <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
> +					      <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
> +			interrupt-names = "wdog", "fatal", "ready", "handover",
> +					  "stop-ack", "shutdown-ack";
This could be a vertical list, similar to the interrupts-extended itself

> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>;
> +			clock-names = "xo";
> +
> +			power-domains = <&rpmhpd QDU1000_CX>,
> +					<&rpmhpd QDU1000_MSS>;
> +			power-domain-names = "cx", "mss";
> +
> +			memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
> +
> +			interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
> +
> +			qcom,qmp = <&aoss_qmp>;
> +
> +			qcom,smem-states = <&smp2p_modem_out 0>;
> +			qcom,smem-state-names = "stop";
> +
> +			status = "disabled";
> +
> +			glink-edge {
> +				interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
> +							     IPCC_MPROC_SIGNAL_GLINK_QMP
> +							     IRQ_TYPE_EDGE_RISING>;
> +				mboxes = <&ipcc IPCC_CLIENT_MPSS
> +						IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +				label = "modem";
> +				qcom,remote-pid = <1>;
> +			};
> +		};
> +
>  		pdc: interrupt-controller@b220000 {
>  			compatible = "qcom,qdu1000-pdc", "qcom,pdc";
>  			reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
> @@ -852,6 +933,29 @@ pdc: interrupt-controller@b220000 {
>  			interrupt-controller;
>  		};
>  
> +		aoss_qmp: qmp@c300000 {
> +			compatible = "qcom,qdu1000-aoss-qmp", "qcom,aoss-qmp";
> +			reg = <0x0 0xc300000 0x0 0x400>;
The address part should be padded to 8 hex digits

> +			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
> +						     IPCC_MPROC_SIGNAL_GLINK_QMP
> +						     IRQ_TYPE_EDGE_RISING>;
> +			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> +			#clock-cells = <0>;
> +
> +			cx_cdev: cx {
> +				#cooling-cells = <2>;
> +			};
> +
> +			mx_cdev: mx {
> +				#cooling-cells = <2>;
> +			};
> +
> +			ebi_cdev: ebi {
> +				#cooling-cells = <2>;
> +			};
cx
ebi
mx

would be alphabetical, unless there's some strong ordering required,
not sure


Konrad
> +		};
> +
>  		spmi_bus: spmi@c400000 {
>  			compatible = "qcom,spmi-pmic-arb";
>  			reg = <0x0 0xc400000 0x0 0x3000>,

Re: [PATCH v2 2/3] arm64: dts: qcom: qdu1000-idp: Enable mpss

[Konrad Dybcio]

On 7.03.2023 00:17, Melody Olvera wrote:
> Add MPSS firmware paths for the QDU1000 IDP platform.
> 
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> index 9e9fd4b8023e..c012da026a10 100644
> --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> @@ -448,6 +448,12 @@ &qupv3_id_0 {
>  	status = "okay";
>  };
>  
> +&remoteproc_mpss {
> +	firmware-name = "qcom/qdu1000/modem.mbn",
> +			"qcom/qdu1000/modem_dtb.mbn";
> +	status = "okay";
> +};
> +
>  &uart7 {
>  	status = "okay";
>  };

Re: [PATCH v2 1/3] arm64: dts: qcom: qdu1000: Add IPCC, MPSS, AOSS nodes

[Melody Olvera]

On 3/8/2023 2:23 AM, Konrad Dybcio wrote:
>
> On 7.03.2023 00:17, Melody Olvera wrote:
>> Add nodes for IPCC, MPSS, and AOSS drivers. Also update
>> the scm node to include its interconnect.
> Quite a bit of stuff in a single commit, this could be
> separated into:
>
> - scm icc
> - aoss+ipcc
> - smp2p+mpss

Hmm ok. Will split this patch into a few patches.

>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>>  arch/arm64/boot/dts/qcom/qdu1000.dtsi | 104 ++++++++++++++++++++++++++
>>  1 file changed, 104 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> index f234159d2060..6cc96a7c33e8 100644
>> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> @@ -8,6 +8,7 @@
>>  #include <dt-bindings/dma/qcom-gpi.h>
>>  #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/mailbox/qcom-ipcc.h>
>>  #include <dt-bindings/power/qcom-rpmpd.h>
>>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>>  
>> @@ -141,6 +142,7 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
>>  	firmware {
>>  		scm {
>>  			compatible = "qcom,scm-qdu1000", "qcom,scm";
>> +			interconnects = <&system_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
>>  		};
>>  	};
>>  
>> @@ -326,6 +328,11 @@ q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
>>  			no-map;
>>  		};
>>  
>> +		mpss_dsm_mem: mpss-dsm@9ec80000 {
>> +			reg = <0x0 0x9ec80000 0x0 0x880000>;
>> +			no-map;
>> +		};
>> +
>>  		tenx_mem: tenx@a0000000 {
>>  			reg = <0x0 0xa0000000 0x0 0x19600000>;
>>  			no-map;
>> @@ -347,6 +354,28 @@ ipa_buffer_mem: ipa-buffer@c3200000 {
>>  		};
>>  	};
>>  
>> +	smp2p-modem {
>> +		compatible = "qcom,smp2p";
>> +		qcom,smem = <435>, <428>;
>> +		interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
>> +					   IPCC_MPROC_SIGNAL_SMP2P
>> +					   IRQ_TYPE_EDGE_RISING>;
> Not sure if thunderfox is acting up again or the indentation here
> is not quite right

No you're right; let me fix this.

>
>> +		mboxes = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
>> +		qcom,local-pid = <0>;
>> +		qcom,remote-pid = <1>;
>> +
>> +		smp2p_modem_out: master-kernel {
>> +			qcom,entry-name = "master-kernel";
>> +			#qcom,smem-state-cells = <1>;
>> +		};
>> +
>> +		smp2p_modem_in: slave-kernel {
>> +			qcom,entry-name = "slave-kernel";
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +		};
>> +	};
>> +
>>  	soc: soc@0 {
>>  		compatible = "simple-bus";
>>  		#address-cells = <2>;
>> @@ -367,6 +396,15 @@ gcc: clock-controller@80000 {
>>  			#power-domain-cells = <1>;
>>  		};
>>  
>> +		ipcc: mailbox@408000 {
>> +			compatible = "qcom,qdu1000-ipcc", "qcom,ipcc";
>> +			reg = <0x0 0x408000 0x0 0x1000>;
> The address part should be padded to 8 hex digits. I'd appreciate it
> if you could submit a fixup for the other nodes in this dtsi!

Sure thing. Will fix here and fix up the other nodes later.

>
>> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +			#mbox-cells = <2>;
>> +		};
>> +
>>  		gpi_dma0: dma-controller@900000  {
>>  			compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
>>  			reg = <0x0 0x900000 0x0 0x60000>;
>> @@ -842,6 +880,49 @@ tcsr_mutex: hwlock@1f40000 {
>>  			#hwlock-cells = <1>;
>>  		};
>>  
>> +		remoteproc_mpss: remoteproc@4080000 {
>> +			compatible = "qcom,qdu1000-mpss-pas";
>> +			reg = <0x0 0x4080000 0x0 0x4040>,
> The address part should be padded to 8 hex digits

Got it.

>
>> +			      <0x0 0x4180000 0x0 0x1000>;
> No reg-names?

No; we don't use reg-names in the driver. Lmk if we should be.

>> +
>> +			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
>> +					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
>> +					      <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
>> +					      <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
>> +					      <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
>> +					      <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
>> +			interrupt-names = "wdog", "fatal", "ready", "handover",
>> +					  "stop-ack", "shutdown-ack";
> This could be a vertical list, similar to the interrupts-extended itself

Sure thing.

>
>> +
>> +			clocks = <&rpmhcc RPMH_CXO_CLK>;
>> +			clock-names = "xo";
>> +
>> +			power-domains = <&rpmhpd QDU1000_CX>,
>> +					<&rpmhpd QDU1000_MSS>;
>> +			power-domain-names = "cx", "mss";
>> +
>> +			memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
>> +
>> +			interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
>> +
>> +			qcom,qmp = <&aoss_qmp>;
>> +
>> +			qcom,smem-states = <&smp2p_modem_out 0>;
>> +			qcom,smem-state-names = "stop";
>> +
>> +			status = "disabled";
>> +
>> +			glink-edge {
>> +				interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
>> +							     IPCC_MPROC_SIGNAL_GLINK_QMP
>> +							     IRQ_TYPE_EDGE_RISING>;
>> +				mboxes = <&ipcc IPCC_CLIENT_MPSS
>> +						IPCC_MPROC_SIGNAL_GLINK_QMP>;
>> +				label = "modem";
>> +				qcom,remote-pid = <1>;
>> +			};
>> +		};
>> +
>>  		pdc: interrupt-controller@b220000 {
>>  			compatible = "qcom,qdu1000-pdc", "qcom,pdc";
>>  			reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
>> @@ -852,6 +933,29 @@ pdc: interrupt-controller@b220000 {
>>  			interrupt-controller;
>>  		};
>>  
>> +		aoss_qmp: qmp@c300000 {
>> +			compatible = "qcom,qdu1000-aoss-qmp", "qcom,aoss-qmp";
>> +			reg = <0x0 0xc300000 0x0 0x400>;
> The address part should be padded to 8 hex digits

Got it.

>
>> +			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
>> +						     IPCC_MPROC_SIGNAL_GLINK_QMP
>> +						     IRQ_TYPE_EDGE_RISING>;
>> +			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
>> +
>> +			#clock-cells = <0>;
>> +
>> +			cx_cdev: cx {
>> +				#cooling-cells = <2>;
>> +			};
>> +
>> +			mx_cdev: mx {
>> +				#cooling-cells = <2>;
>> +			};
>> +
>> +			ebi_cdev: ebi {
>> +				#cooling-cells = <2>;
>> +			};
> cx
> ebi
> mx
>
> would be alphabetical, unless there's some strong ordering required,
> not sure

Not to my knowledge. Let me reorder.

Thanks,
Melody
>
>
> Konrad
>> +		};
>> +
>>  		spmi_bus: spmi@c400000 {
>>  			compatible = "qcom,spmi-pmic-arb";
>>  			reg = <0x0 0xc400000 0x0 0x3000>,

Re: [PATCH v2 1/3] arm64: dts: qcom: qdu1000: Add IPCC, MPSS, AOSS nodes

[Konrad Dybcio]

On 13.03.2023 22:25, Melody Olvera wrote:
> 
> 
> On 3/8/2023 2:23 AM, Konrad Dybcio wrote:
>>
>> On 7.03.2023 00:17, Melody Olvera wrote:
>>> Add nodes for IPCC, MPSS, and AOSS drivers. Also update
>>> the scm node to include its interconnect.
>> Quite a bit of stuff in a single commit, this could be
>> separated into:
>>
>> - scm icc
>> - aoss+ipcc
>> - smp2p+mpss
> 
> Hmm ok. Will split this patch into a few patches.
> 
>>
>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>> ---
[...]

>>> +			      <0x0 0x4180000 0x0 0x1000>;
>> No reg-names?
> 
> No; we don't use reg-names in the driver. Lmk if we should be.
> 
qcom_q6v5_mss.c / qcom_q6v5_wcss.c get the 'rmb' region with
[...]_byname and I think it'd scale better if we did the same here,
as one day there may be a weird SoC that'd have an "XYZ" region,
different to "base" and "rmb", which we would need to handle.. somehow..

Konrad

Re: [PATCH v2 1/3] arm64: dts: qcom: qdu1000: Add IPCC, MPSS, AOSS nodes

[Melody Olvera]

On 3/14/2023 3:55 AM, Konrad Dybcio wrote:
>
> On 13.03.2023 22:25, Melody Olvera wrote:
>>
>> On 3/8/2023 2:23 AM, Konrad Dybcio wrote:
>>> On 7.03.2023 00:17, Melody Olvera wrote:
>>>> Add nodes for IPCC, MPSS, and AOSS drivers. Also update
>>>> the scm node to include its interconnect.
>>> Quite a bit of stuff in a single commit, this could be
>>> separated into:
>>>
>>> - scm icc
>>> - aoss+ipcc
>>> - smp2p+mpss
>> Hmm ok. Will split this patch into a few patches.
>>
>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>> ---
> [...]
>
>>>> +			      <0x0 0x4180000 0x0 0x1000>;
>>> No reg-names?
>> No; we don't use reg-names in the driver. Lmk if we should be.
>>
> qcom_q6v5_mss.c / qcom_q6v5_wcss.c get the 'rmb' region with
> [...]_byname and I think it'd scale better if we did the same here,
> as one day there may be a weird SoC that'd have an "XYZ" region,
> different to "base" and "rmb", which we would need to handle.. somehow..

Yeah that's sensible. Will update the driver and this entry.

Thanks,
Melody
>
> Konrad