[PATCH 00/20] Restructure RPM SMD ICC

[PATCH 00/20] Restructure RPM SMD ICC

[Konrad Dybcio]

This series reshuffles things around, moving the management of SMD RPM
bus clocks to the interconnect framework where they belong. This helps
us solve a couple of issues:

1. We can work towards unused clk cleanup of RPMCC without worrying
   about it killing some NoC bus, resulting in the SoC dying.
   Deasserting actually unused RPM clocks (among other things) will
   let us achieve "true SoC-wide power collapse states", also known as
   VDD_LOW and VDD_MIN.

2. We no longer have to keep tons of quirky bus clock ifs in the icc
   driver. You either have a RPM clock and call "rpm set rate" or you
   have a single non-RPM clock (like AHB_CLK_SRC) or you don't have any.

3. There's less overhead - instead of going through layers and layers of
   the CCF, ratesetting comes down to calling max() and sending a single
   RPM message. ICC is very very dynamic so that's a big plus.

The clocks still need to be vaguely described in the clk-smd-rpm driver,
as it gives them an initial kickoff, before actually telling RPM to
enable DVFS scaling.  After RPM receives that command, all clocks that
have not been assigned a rate are considered unused and are shut down
in hardware, leading to the same issue as described in point 1.

We can consider marking them __initconst in the future, but this series
is very fat even without that..

Apart from that, it squashes a couple of bugs that really need fixing..

--- MERGING STRATEGY ---
If Stephen and Georgi agree, it would be best to take all of this through
the qcom tree, as it touches on heavily intertwined components and
introduces compile-time dependencies between icc and clk drivers.

Tested on SM6375 (OOT), MSM8998 (OOT), MSM8996.

MSM8974 conversion to common code and modernization will be handled separately.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (20):
      soc: qcom: smd-rpm: Add QCOM_SMD_RPM_STATE_NUM
      clk: qcom: smd-rpm: Move some RPM resources to the common header
      clk: qcom: smd-rpm: Separate out interconnect bus clocks
      clk: qcom: smd-rpm: Export clock scaling availability
      interconnect: qcom: icc-rpm: Introduce keep_alive
      interconnect: qcom: icc-rpm: Allow negative QoS offset
      interconnect: qcom: Fold smd-rpm.h into icc-rpm.h
      interconnect: qcom: smd-rpm: Add rpmcc handling skeleton code
      interconnect: qcom: Add missing headers in icc-rpm.h
      interconnect: qcom: Define RPM bus clocks
      interconnect: qcom: sdm660: Hook up RPM bus clk definitions
      interconnect: qcom: msm8996: Hook up RPM bus clk definitions
      interconnect: qcom: qcs404: Hook up RPM bus clk definitions
      interconnect: qcom: msm8939: Hook up RPM bus clk definitions
      interconnect: qcom: msm8916: Hook up RPM bus clk definitions
      interconnect: qcom: qcm2290: Hook up RPM bus clk definitions
      interconnect: qcom: icc-rpm: Control bus rpmcc from icc
      interconnect: qcom: icc-rpm: Fix bucket number
      interconnect: qcom: icc-rpm: Set bandwidth on both contexts
      interconnect: qcom: Divide clk rate by src node bus width

 drivers/clk/qcom/clk-smd-rpm.c             | 300 ++++++++++++-----------------
 drivers/interconnect/qcom/Makefile         |   2 +-
 drivers/interconnect/qcom/icc-rpm-clocks.c |  66 +++++++
 drivers/interconnect/qcom/icc-rpm.c        | 183 ++++++++++--------
 drivers/interconnect/qcom/icc-rpm.h        |  55 ++++--
 drivers/interconnect/qcom/msm8916.c        |   4 +-
 drivers/interconnect/qcom/msm8939.c        |   5 +-
 drivers/interconnect/qcom/msm8974.c        |   2 +-
 drivers/interconnect/qcom/msm8996.c        |   9 +-
 drivers/interconnect/qcom/qcm2290.c        |   7 +-
 drivers/interconnect/qcom/qcs404.c         |   4 +-
 drivers/interconnect/qcom/sdm660.c         |   7 +-
 drivers/interconnect/qcom/smd-rpm.c        |  39 +++-
 drivers/interconnect/qcom/smd-rpm.h        |  15 --
 include/linux/soc/qcom/smd-rpm.h           |  22 ++-
 15 files changed, 424 insertions(+), 296 deletions(-)
---
base-commit: 8c33787278ca8db73ad7d23f932c8c39b9f6e543
change-id: 20230526-topic-smd_icc-b8213948a5ed

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@linaro.org>

[PATCH 01/20] soc: qcom: smd-rpm: Add QCOM_SMD_RPM_STATE_NUM

[Konrad Dybcio]

Add a preprocessor define to indicate the number of RPM contexts/states.
While at it, use tabs instead of spaces for the existing entries.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 include/linux/soc/qcom/smd-rpm.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h
index 2990f425fdef..99499e4b080e 100644
--- a/include/linux/soc/qcom/smd-rpm.h
+++ b/include/linux/soc/qcom/smd-rpm.h
@@ -4,8 +4,9 @@
 
 struct qcom_smd_rpm;
 
-#define QCOM_SMD_RPM_ACTIVE_STATE        0
-#define QCOM_SMD_RPM_SLEEP_STATE         1
+#define QCOM_SMD_RPM_ACTIVE_STATE	0
+#define QCOM_SMD_RPM_SLEEP_STATE	1
+#define QCOM_SMD_RPM_STATE_NUM		2
 
 /*
  * Constants used for addressing resources in the RPM.

-- 
2.40.1

[PATCH 02/20] clk: qcom: smd-rpm: Move some RPM resources to the common header

[Konrad Dybcio]

In preparation for handling the bus clocks in the icc driver, carve out
some defines and a struct definition to the common rpm header.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/clk/qcom/clk-smd-rpm.c   | 13 -------------
 include/linux/soc/qcom/smd-rpm.h | 15 +++++++++++++++
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index e4de74b68797..937cb1515968 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -18,13 +18,6 @@
 
 #include <dt-bindings/clock/qcom,rpmcc.h>
 
-#define QCOM_RPM_KEY_SOFTWARE_ENABLE			0x6e657773
-#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY	0x62636370
-#define QCOM_RPM_SMD_KEY_RATE				0x007a484b
-#define QCOM_RPM_SMD_KEY_ENABLE				0x62616e45
-#define QCOM_RPM_SMD_KEY_STATE				0x54415453
-#define QCOM_RPM_SCALING_ENABLE_ID			0x2
-
 #define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active,		      \
 				    type, r_id, key)			      \
 	static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active;	      \
@@ -171,12 +164,6 @@ struct clk_smd_rpm {
 	unsigned long rate;
 };
 
-struct clk_smd_rpm_req {
-	__le32 key;
-	__le32 nbytes;
-	__le32 value;
-};
-
 struct rpm_smd_clk_desc {
 	struct clk_smd_rpm **clks;
 	size_t num_clks;
diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h
index 99499e4b080e..8190878645f9 100644
--- a/include/linux/soc/qcom/smd-rpm.h
+++ b/include/linux/soc/qcom/smd-rpm.h
@@ -2,6 +2,8 @@
 #ifndef __QCOM_SMD_RPM_H__
 #define __QCOM_SMD_RPM_H__
 
+#include <linux/types.h>
+
 struct qcom_smd_rpm;
 
 #define QCOM_SMD_RPM_ACTIVE_STATE	0
@@ -45,6 +47,19 @@ struct qcom_smd_rpm;
 #define QCOM_SMD_RPM_PKA_CLK	0x616b70
 #define QCOM_SMD_RPM_MCFG_CLK	0x6766636d
 
+#define QCOM_RPM_KEY_SOFTWARE_ENABLE			0x6e657773
+#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY	0x62636370
+#define QCOM_RPM_SMD_KEY_RATE				0x007a484b
+#define QCOM_RPM_SMD_KEY_ENABLE				0x62616e45
+#define QCOM_RPM_SMD_KEY_STATE				0x54415453
+#define QCOM_RPM_SCALING_ENABLE_ID			0x2
+
+struct clk_smd_rpm_req {
+	__le32 key;
+	__le32 nbytes;
+	__le32 value;
+};
+
 int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
 		       int state,
 		       u32 resource_type, u32 resource_id,

-- 
2.40.1

[PATCH 03/20] clk: qcom: smd-rpm: Separate out interconnect bus clocks

[Konrad Dybcio]

The interconnect bus clocks are now handled within the ICC framework.
They still however need to get a kickstart *before* we call
clk_smd_rpm_enable_scaling(), or RPM will assume that they should all
be running at 0 kHz and the system will inevitably die.

Separate them out to ensure such a kickstart can still take place.

As a happy accident, the file got smaller:

Total: Before=41951, After=41555, chg -0.94%

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/clk/qcom/clk-smd-rpm.c | 278 +++++++++++++++++------------------------
 1 file changed, 115 insertions(+), 163 deletions(-)

diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index 937cb1515968..b63f946e4520 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -167,6 +167,14 @@ struct clk_smd_rpm {
 struct rpm_smd_clk_desc {
 	struct clk_smd_rpm **clks;
 	size_t num_clks;
+
+	/*
+	 * Interconnect clocks are managed by the icc framework, this driver
+	 * only kickstarts them so that they don't get gated between
+	 * clk_smd_rpm_enable_scaling() and interconnect driver initialization.
+	 */
+	struct clk_smd_rpm **icc_clks;
+	size_t num_icc_clks;
 	bool scaling_before_handover;
 };
 
@@ -498,13 +506,69 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000);
 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000);
 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000);
 
+static struct clk_smd_rpm *bimc_pcnoc_icc_clks[] = {
+	&clk_smd_rpm_bimc_clk,
+	&clk_smd_rpm_bus_0_pcnoc_clk,
+};
+
+static struct clk_smd_rpm *bimc_pcnoc_snoc_icc_clks[] = {
+	&clk_smd_rpm_bimc_clk,
+	&clk_smd_rpm_bus_0_pcnoc_clk,
+	&clk_smd_rpm_bus_1_snoc_clk,
+};
+
+static struct clk_smd_rpm *bimc_pcnoc_snoc_smmnoc_icc_clks[] = {
+	&clk_smd_rpm_bimc_clk,
+	&clk_smd_rpm_bus_0_pcnoc_clk,
+	&clk_smd_rpm_bus_1_snoc_clk,
+	&clk_smd_rpm_bus_2_sysmmnoc_clk,
+};
+
+static struct clk_smd_rpm *bimc_pcnoc_snoc_cnoc_ocmem_icc_clks[] = {
+	&clk_smd_rpm_bimc_clk,
+	&clk_smd_rpm_bus_0_pcnoc_clk,
+	&clk_smd_rpm_bus_1_snoc_clk,
+	&clk_smd_rpm_bus_2_cnoc_clk,
+	&clk_smd_rpm_ocmemgx_clk,
+};
+
+static struct clk_smd_rpm *msm8996_icc_clks[] = {
+	&clk_smd_rpm_bimc_clk,
+	&clk_smd_rpm_branch_aggre1_noc_clk,
+	&clk_smd_rpm_branch_aggre2_noc_clk,
+	&clk_smd_rpm_bus_0_pcnoc_clk,
+	&clk_smd_rpm_bus_1_snoc_clk,
+	&clk_smd_rpm_bus_2_cnoc_clk,
+	&clk_smd_rpm_mmssnoc_axi_rpm_clk,
+};
+
+static struct clk_smd_rpm *msm8998_icc_clks[] = {
+	&clk_smd_rpm_aggre1_noc_clk,
+	&clk_smd_rpm_aggre2_noc_clk,
+	&clk_smd_rpm_bimc_clk,
+	&clk_smd_rpm_bus_1_snoc_clk,
+	&clk_smd_rpm_bus_2_cnoc_clk,
+	&clk_smd_rpm_mmssnoc_axi_rpm_clk,
+};
+
+static struct clk_smd_rpm *sdm660_icc_clks[] = {
+	&clk_smd_rpm_aggre2_noc_clk,
+	&clk_smd_rpm_bimc_clk,
+	&clk_smd_rpm_bus_1_snoc_clk,
+	&clk_smd_rpm_bus_2_cnoc_clk,
+	&clk_smd_rpm_mmssnoc_axi_rpm_clk,
+};
+
+static struct clk_smd_rpm *sm_qnoc_icc_clks[] = {
+	&clk_smd_rpm_bimc_clk,
+	&clk_smd_rpm_bus_1_cnoc_clk,
+	&clk_smd_rpm_mmnrt_clk,
+	&clk_smd_rpm_mmrt_clk,
+	&clk_smd_rpm_qup_clk,
+	&clk_smd_rpm_bus_2_snoc_clk,
+};
+
 static struct clk_smd_rpm *msm8909_clks[] = {
-	[RPM_SMD_PCNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
-	[RPM_SMD_PCNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_SNOC_CLK]		= &clk_smd_rpm_bus_1_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK]		= &clk_smd_rpm_bus_1_snoc_a_clk,
-	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
 	[RPM_SMD_QPIC_CLK]		= &clk_smd_rpm_qpic_clk,
 	[RPM_SMD_QPIC_CLK_A]		= &clk_smd_rpm_qpic_a_clk,
 	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
@@ -530,15 +594,11 @@ static struct clk_smd_rpm *msm8909_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_msm8909 = {
 	.clks = msm8909_clks,
 	.num_clks = ARRAY_SIZE(msm8909_clks),
+	.icc_clks = bimc_pcnoc_snoc_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
 };
 
 static struct clk_smd_rpm *msm8916_clks[] = {
-	[RPM_SMD_PCNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
-	[RPM_SMD_PCNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_SNOC_CLK]		= &clk_smd_rpm_bus_1_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK]		= &clk_smd_rpm_bus_1_snoc_a_clk,
-	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
 	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK]		= &clk_smd_rpm_qdss_a_clk,
 	[RPM_SMD_BB_CLK1]		= &clk_smd_rpm_bb_clk1,
@@ -562,21 +622,15 @@ static struct clk_smd_rpm *msm8916_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
 	.clks = msm8916_clks,
 	.num_clks = ARRAY_SIZE(msm8916_clks),
+	.icc_clks = bimc_pcnoc_snoc_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
 };
 
 static struct clk_smd_rpm *msm8917_clks[] = {
 	[RPM_SMD_XO_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_PNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
-	[RPM_SMD_PNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_SNOC_CLK]		= &clk_smd_rpm_bus_1_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK]		= &clk_smd_rpm_bus_1_snoc_a_clk,
-	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
 	[RPM_SMD_BIMC_GPU_CLK]		= &clk_smd_rpm_bimc_gpu_clk,
 	[RPM_SMD_BIMC_GPU_A_CLK]	= &clk_smd_rpm_bimc_gpu_a_clk,
-	[RPM_SMD_SYSMMNOC_CLK]		= &clk_smd_rpm_bus_2_sysmmnoc_clk,
-	[RPM_SMD_SYSMMNOC_A_CLK]	= &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
 	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK]		= &clk_smd_rpm_qdss_a_clk,
 	[RPM_SMD_BB_CLK1]		= &clk_smd_rpm_bb_clk1,
@@ -596,19 +650,13 @@ static struct clk_smd_rpm *msm8917_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_msm8917 = {
 	.clks = msm8917_clks,
 	.num_clks = ARRAY_SIZE(msm8917_clks),
+	.icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
 };
 
 static struct clk_smd_rpm *msm8936_clks[] = {
 	[RPM_SMD_XO_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_PCNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
-	[RPM_SMD_PCNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_SNOC_CLK]		= &clk_smd_rpm_bus_1_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK]		= &clk_smd_rpm_bus_1_snoc_a_clk,
-	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
-	[RPM_SMD_SYSMMNOC_CLK]		= &clk_smd_rpm_bus_2_sysmmnoc_clk,
-	[RPM_SMD_SYSMMNOC_A_CLK]	= &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
 	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK]		= &clk_smd_rpm_qdss_a_clk,
 	[RPM_SMD_BB_CLK1]		= &clk_smd_rpm_bb_clk1,
@@ -632,25 +680,17 @@ static struct clk_smd_rpm *msm8936_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
 		.clks = msm8936_clks,
 		.num_clks = ARRAY_SIZE(msm8936_clks),
+		.icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
+		.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
 };
 
 static struct clk_smd_rpm *msm8974_clks[] = {
 	[RPM_SMD_XO_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_PNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
-	[RPM_SMD_PNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_SNOC_CLK]		= &clk_smd_rpm_bus_1_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK]		= &clk_smd_rpm_bus_1_snoc_a_clk,
-	[RPM_SMD_CNOC_CLK]		= &clk_smd_rpm_bus_2_cnoc_clk,
-	[RPM_SMD_CNOC_A_CLK]		= &clk_smd_rpm_bus_2_cnoc_a_clk,
 	[RPM_SMD_MMSSNOC_AHB_CLK]	= &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,
 	[RPM_SMD_MMSSNOC_AHB_A_CLK]	= &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,
-	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
 	[RPM_SMD_GFX3D_CLK_SRC]		= &clk_smd_rpm_gfx3d_clk_src,
 	[RPM_SMD_GFX3D_A_CLK_SRC]	= &clk_smd_rpm_gfx3d_a_clk_src,
-	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
-	[RPM_SMD_OCMEMGX_CLK]		= &clk_smd_rpm_ocmemgx_clk,
-	[RPM_SMD_OCMEMGX_A_CLK]		= &clk_smd_rpm_ocmemgx_a_clk,
 	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK]		= &clk_smd_rpm_qdss_a_clk,
 	[RPM_SMD_CXO_D0]		= &clk_smd_rpm_cxo_d0,
@@ -684,20 +724,14 @@ static struct clk_smd_rpm *msm8974_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
 	.clks = msm8974_clks,
 	.num_clks = ARRAY_SIZE(msm8974_clks),
+	.icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
 	.scaling_before_handover = true,
 };
 
 static struct clk_smd_rpm *msm8976_clks[] = {
 	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
-	[RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
-	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
-	[RPM_SMD_SYSMMNOC_CLK]	= &clk_smd_rpm_bus_2_sysmmnoc_clk,
-	[RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
 	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
 	[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
@@ -718,24 +752,15 @@ static struct clk_smd_rpm *msm8976_clks[] = {
 
 static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
 	.clks = msm8976_clks,
-	.num_clks = ARRAY_SIZE(msm8976_clks),
+	.icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
 };
 
 static struct clk_smd_rpm *msm8992_clks[] = {
 	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
-	[RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk,
-	[RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk,
-	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
-	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
-	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
 	[RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
 	[RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
-	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
 	[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
 	[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
 	[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
@@ -777,23 +802,15 @@ static struct clk_smd_rpm *msm8992_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
 	.clks = msm8992_clks,
 	.num_clks = ARRAY_SIZE(msm8992_clks),
+	.icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
 };
 
 static struct clk_smd_rpm *msm8994_clks[] = {
 	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
-	[RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk,
-	[RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk,
-	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
-	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
-	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
 	[RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
 	[RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
-	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
 	[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
 	[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
 	[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
@@ -837,29 +854,17 @@ static struct clk_smd_rpm *msm8994_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
 	.clks = msm8994_clks,
 	.num_clks = ARRAY_SIZE(msm8994_clks),
+	.icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
 };
 
 static struct clk_smd_rpm *msm8996_clks[] = {
 	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
-	[RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
-	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
-	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
-	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
-	[RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk,
-	[RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk,
 	[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
 	[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
 	[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
 	[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
-	[RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_branch_aggre1_noc_clk,
-	[RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_branch_aggre1_noc_a_clk,
-	[RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_branch_aggre2_noc_clk,
-	[RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_branch_aggre2_noc_a_clk,
 	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
 	[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
@@ -891,6 +896,8 @@ static struct clk_smd_rpm *msm8996_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
 	.clks = msm8996_clks,
 	.num_clks = ARRAY_SIZE(msm8996_clks),
+	.icc_clks = msm8996_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(msm8996_icc_clks),
 };
 
 static struct clk_smd_rpm *qcs404_clks[] = {
@@ -919,19 +926,15 @@ static struct clk_smd_rpm *qcs404_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
 	.clks = qcs404_clks,
 	.num_clks = ARRAY_SIZE(qcs404_clks),
+	.icc_clks = bimc_pcnoc_snoc_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
 };
 
 static struct clk_smd_rpm *msm8998_clks[] = {
 	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
 	[RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
 	[RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
-	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
-	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
 	[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
 	[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
 	[RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
@@ -954,12 +957,6 @@ static struct clk_smd_rpm *msm8998_clks[] = {
 	[RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin,
 	[RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin,
 	[RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin,
-	[RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk,
-	[RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk,
-	[RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_aggre1_noc_clk,
-	[RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_aggre1_noc_a_clk,
-	[RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk,
-	[RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk,
 	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
 	[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
@@ -979,27 +976,19 @@ static struct clk_smd_rpm *msm8998_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
 	.clks = msm8998_clks,
 	.num_clks = ARRAY_SIZE(msm8998_clks),
+	.icc_clks = msm8998_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(msm8998_icc_clks),
 };
 
 static struct clk_smd_rpm *sdm660_clks[] = {
 	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
-	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
-	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
 	[RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
 	[RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
-	[RPM_SMD_MMSSNOC_AXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk,
-	[RPM_SMD_MMSSNOC_AXI_CLK_A] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk,
 	[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
 	[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
 	[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
 	[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
-	[RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk,
-	[RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk,
 	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
 	[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
@@ -1025,15 +1014,13 @@ static struct clk_smd_rpm *sdm660_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
 	.clks = sdm660_clks,
 	.num_clks = ARRAY_SIZE(sdm660_clks),
+	.icc_clks = sdm660_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(sdm660_icc_clks),
 };
 
 static struct clk_smd_rpm *mdm9607_clks[] = {
 	[RPM_SMD_XO_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_PCNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
-	[RPM_SMD_PCNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
 	[RPM_SMD_QPIC_CLK]		= &clk_smd_rpm_qpic_clk,
 	[RPM_SMD_QPIC_CLK_A]		= &clk_smd_rpm_qpic_a_clk,
 	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
@@ -1047,21 +1034,15 @@ static struct clk_smd_rpm *mdm9607_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = {
 	.clks = mdm9607_clks,
 	.num_clks = ARRAY_SIZE(mdm9607_clks),
+	.icc_clks = bimc_pcnoc_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_icc_clks),
 };
 
 static struct clk_smd_rpm *msm8953_clks[] = {
 	[RPM_SMD_XO_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_PCNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
-	[RPM_SMD_PCNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
-	[RPM_SMD_SNOC_CLK]		= &clk_smd_rpm_bus_1_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK]		= &clk_smd_rpm_bus_1_snoc_a_clk,
-	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
 	[RPM_SMD_IPA_CLK]		= &clk_smd_rpm_ipa_clk,
 	[RPM_SMD_IPA_A_CLK]		= &clk_smd_rpm_ipa_a_clk,
-	[RPM_SMD_SYSMMNOC_CLK]		= &clk_smd_rpm_bus_2_sysmmnoc_clk,
-	[RPM_SMD_SYSMMNOC_A_CLK]	= &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
 	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK]		= &clk_smd_rpm_qdss_a_clk,
 	[RPM_SMD_BB_CLK1]		= &clk_smd_rpm_bb_clk1,
@@ -1083,23 +1064,19 @@ static struct clk_smd_rpm *msm8953_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_msm8953 = {
 	.clks = msm8953_clks,
 	.num_clks = ARRAY_SIZE(msm8953_clks),
+	.icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
 };
 
 static struct clk_smd_rpm *sm6125_clks[] = {
 	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
-	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
 	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
 	[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
 	[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
 	[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
 	[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
-	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
-	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
 	[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
 	[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
 	[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
@@ -1110,12 +1087,6 @@ static struct clk_smd_rpm *sm6125_clks[] = {
 	[RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
 	[RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,
 	[RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,
-	[RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
-	[RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
-	[RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
-	[RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
-	[RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
-	[RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
 	[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
 	[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
 	[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
@@ -1125,34 +1096,24 @@ static struct clk_smd_rpm *sm6125_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_sm6125 = {
 	.clks = sm6125_clks,
 	.num_clks = ARRAY_SIZE(sm6125_clks),
+	.icc_clks = sm_qnoc_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
 };
 
 /* SM6115 */
 static struct clk_smd_rpm *sm6115_clks[] = {
 	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
-	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
 	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
 	[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
 	[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
 	[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
 	[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
-	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
-	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
 	[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
 	[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
 	[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
 	[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
-	[RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
-	[RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
-	[RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
-	[RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
-	[RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
-	[RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
 	[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
 	[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
 	[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
@@ -1166,27 +1127,17 @@ static struct clk_smd_rpm *sm6115_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
 	.clks = sm6115_clks,
 	.num_clks = ARRAY_SIZE(sm6115_clks),
+	.icc_clks = sm_qnoc_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
 };
 
 static struct clk_smd_rpm *sm6375_clks[] = {
 	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
-	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
 	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
-	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
-	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
 	[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
 	[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
-	[RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
-	[RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
-	[RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
-	[RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
-	[RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
-	[RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
 	[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
 	[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
 	[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
@@ -1203,31 +1154,21 @@ static struct clk_smd_rpm *sm6375_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_sm6375 = {
 	.clks = sm6375_clks,
 	.num_clks = ARRAY_SIZE(sm6375_clks),
+	.icc_clks = sm_qnoc_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
 };
 
 static struct clk_smd_rpm *qcm2290_clks[] = {
 	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
 	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
-	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
-	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
-	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
-	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
 	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
 	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
 	[RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
 	[RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
 	[RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3,
 	[RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a,
-	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
-	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
 	[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
 	[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
-	[RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
-	[RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
-	[RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
-	[RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
-	[RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
-	[RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
 	[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
 	[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
 	[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
@@ -1249,6 +1190,8 @@ static struct clk_smd_rpm *qcm2290_clks[] = {
 static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {
 	.clks = qcm2290_clks,
 	.num_clks = ARRAY_SIZE(qcm2290_clks),
+	.icc_clks = sm_qnoc_icc_clks,
+	.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
 };
 
 static const struct of_device_id rpm_smd_clk_match_table[] = {
@@ -1324,6 +1267,15 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
 			goto err;
 	}
 
+	for (i = 0; i < desc->num_icc_clks; i++) {
+		if (!desc->icc_clks[i])
+			continue;
+
+		ret = clk_smd_rpm_handoff(desc->icc_clks[i]);
+		if (ret)
+			goto err;
+	}
+
 	if (!desc->scaling_before_handover) {
 		ret = clk_smd_rpm_enable_scaling();
 		if (ret)

-- 
2.40.1

[PATCH 04/20] clk: qcom: smd-rpm: Export clock scaling availability

[Konrad Dybcio]

Before we issue a call to RPM through clk_smd_rpm_enable_scaling() the
clock rate requests will not be commited in hardware. This poses a
race threat since we're accessing the bus clocks directly from within
the interconnect framework.

Add a marker to indicate that we're good to go with sending new requests
and export it so that it can be referenced from icc.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/clk/qcom/clk-smd-rpm.c   | 9 +++++++++
 include/linux/soc/qcom/smd-rpm.h | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index b63f946e4520..f8f5977408e0 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -151,6 +151,7 @@
 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
 
 static struct qcom_smd_rpm *rpmcc_smd_rpm;
+static bool smd_rpm_clk_scaling;
 
 struct clk_smd_rpm {
 	const int rpm_res_type;
@@ -393,6 +394,12 @@ static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
 	return r->rate;
 }
 
+bool qcom_smd_rpm_scaling_available(void)
+{
+	return smd_rpm_clk_scaling;
+}
+EXPORT_SYMBOL_GPL(qcom_smd_rpm_scaling_available);
+
 static int clk_smd_rpm_enable_scaling(void)
 {
 	int ret;
@@ -418,6 +425,8 @@ static int clk_smd_rpm_enable_scaling(void)
 		return ret;
 	}
 
+	smd_rpm_clk_scaling = true;
+
 	pr_debug("%s: RPM clock scaling is enabled\n", __func__);
 	return 0;
 }
diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h
index 8190878645f9..420f6c79d535 100644
--- a/include/linux/soc/qcom/smd-rpm.h
+++ b/include/linux/soc/qcom/smd-rpm.h
@@ -65,4 +65,6 @@ int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
 		       u32 resource_type, u32 resource_id,
 		       void *buf, size_t count);
 
+bool qcom_smd_rpm_scaling_available(void);
+
 #endif

-- 
2.40.1

[PATCH 05/20] interconnect: qcom: icc-rpm: Introduce keep_alive

[Konrad Dybcio]

The downstream kernel employs the concept of "keeping the bus alive"
by voting for the minimum (XO/19.2MHz) rate at all times on certain
(well, most) buses. This is a very important thing to have, as if we
either have a lackluster/wrong DT that doesn't specify a (high enough)
vote on a certain bus, we may lose access to the entire bus altogether.
This is very apparent when we only start introducing interconnect
support on a given platform and haven't yet introduced voting on all
peripherals.

The same can happen if we only have a single driver casting a vote on
a certain bus and that driver exits/crashes/suspends.

The keepalive vote is limited to the ACTIVE bucket, as keeping a
permanent vote on the SLEEP one could prevent the platform from properly
entering low power mode states.

Introduce the very same concept, with a slight twist: the vendor
kernel checks whether the rate is zero before setting the minimum
vote, but that's rather silly, as in doing so we're at the mercy
of CCF. Instead, explicitly clamp the rates to always be >= 19.2 MHz
for providers with keep_alive=true.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/icc-rpm.c | 10 ++++++++++
 drivers/interconnect/qcom/icc-rpm.h |  3 +++
 2 files changed, 13 insertions(+)

diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c
index 6acc7686ed38..863e8ba1daa2 100644
--- a/drivers/interconnect/qcom/icc-rpm.c
+++ b/drivers/interconnect/qcom/icc-rpm.c
@@ -50,6 +50,8 @@
 #define NOC_QOS_MODE_FIXED_VAL		0x0
 #define NOC_QOS_MODE_BYPASS_VAL		0x2
 
+#define ICC_BUS_CLK_MIN_RATE		19200000ULL
+
 static int qcom_icc_set_qnoc_qos(struct icc_node *src)
 {
 	struct icc_provider *provider = src->provider;
@@ -380,6 +382,13 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 		do_div(rate, src_qn->buswidth);
 		rate = min_t(u64, rate, LONG_MAX);
 
+		/*
+		 * Downstream checks whether the requested rate is zero, but it makes little sense
+		 * to vote for a value that's below the lower threshold, so let's not do so.
+		 */
+		if (bucket == QCOM_ICC_BUCKET_WAKE && qp->keep_alive)
+			rate = max(ICC_BUS_CLK_MIN_RATE, rate);
+
 		if (qp->bus_clk_rate[i] == rate)
 			continue;
 
@@ -453,6 +462,7 @@ int qnoc_probe(struct platform_device *pdev)
 	for (i = 0; i < qp->num_bus_clks; i++)
 		qp->bus_clks[i].id = bus_clocks[i];
 
+	qp->keep_alive = desc->keep_alive;
 	qp->type = desc->type;
 	qp->qos_offset = desc->qos_offset;
 
diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
index ee705edf19dd..d2c04c400cad 100644
--- a/drivers/interconnect/qcom/icc-rpm.h
+++ b/drivers/interconnect/qcom/icc-rpm.h
@@ -33,6 +33,7 @@ enum qcom_icc_type {
  * @bus_clk_rate: bus clock rate in Hz
  * @bus_clks: the clk_bulk_data table of bus clocks
  * @intf_clks: a clk_bulk_data array of interface clocks
+ * @keep_alive: whether to always keep a minimum vote on the bus clocks
  * @is_on: whether the bus is powered on
  */
 struct qcom_icc_provider {
@@ -45,6 +46,7 @@ struct qcom_icc_provider {
 	u64 bus_clk_rate[NUM_BUS_CLKS];
 	struct clk_bulk_data bus_clks[NUM_BUS_CLKS];
 	struct clk_bulk_data *intf_clks;
+	bool keep_alive;
 	bool is_on;
 };
 
@@ -102,6 +104,7 @@ struct qcom_icc_desc {
 	const char * const *bus_clocks;
 	const char * const *intf_clocks;
 	size_t num_intf_clocks;
+	bool keep_alive;
 	bool no_clk_scaling;
 	enum qcom_icc_type type;
 	const struct regmap_config *regmap_cfg;

-- 
2.40.1

[PATCH 06/20] interconnect: qcom: icc-rpm: Allow negative QoS offset

[Konrad Dybcio]

In some very very very very unfortunate cases, the correct offset of
the QoS registers will be.. negative. One such case is MSM8998, where
The DDR BWMON occupies what-would-be-the-BIMC-base which we usually
take into account with the register calculation, making the actual
BIMC node start at what-would-be-the-BIMC-base+0x300.

In order to keep the calculation code sane, the simplest - however
ugly it may be - solution is to allow the offset to be negative.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/icc-rpm.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
index d2c04c400cad..ba840a436cc0 100644
--- a/drivers/interconnect/qcom/icc-rpm.h
+++ b/drivers/interconnect/qcom/icc-rpm.h
@@ -29,10 +29,10 @@ enum qcom_icc_type {
  * @num_intf_clks: the total number of intf_clks clk_bulk_data entries
  * @type: the ICC provider type
  * @regmap: regmap for QoS registers read/write access
- * @qos_offset: offset to QoS registers
  * @bus_clk_rate: bus clock rate in Hz
  * @bus_clks: the clk_bulk_data table of bus clocks
  * @intf_clks: a clk_bulk_data array of interface clocks
+ * @qos_offset: offset to QoS registers
  * @keep_alive: whether to always keep a minimum vote on the bus clocks
  * @is_on: whether the bus is powered on
  */
@@ -42,7 +42,7 @@ struct qcom_icc_provider {
 	int num_intf_clks;
 	enum qcom_icc_type type;
 	struct regmap *regmap;
-	unsigned int qos_offset;
+	int qos_offset;
 	u64 bus_clk_rate[NUM_BUS_CLKS];
 	struct clk_bulk_data bus_clks[NUM_BUS_CLKS];
 	struct clk_bulk_data *intf_clks;
@@ -108,7 +108,7 @@ struct qcom_icc_desc {
 	bool no_clk_scaling;
 	enum qcom_icc_type type;
 	const struct regmap_config *regmap_cfg;
-	unsigned int qos_offset;
+	int qos_offset;
 };
 
 /* Valid for all bus types */

-- 
2.40.1

[PATCH 07/20] interconnect: qcom: Fold smd-rpm.h into icc-rpm.h

[Konrad Dybcio]

smd-rpm.h is not very useful as-is and both files are always included
anyway.. Combine them.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/icc-rpm.c |  1 -
 drivers/interconnect/qcom/icc-rpm.h |  5 +++++
 drivers/interconnect/qcom/msm8916.c |  1 -
 drivers/interconnect/qcom/msm8939.c |  1 -
 drivers/interconnect/qcom/msm8974.c |  2 +-
 drivers/interconnect/qcom/msm8996.c |  1 -
 drivers/interconnect/qcom/qcm2290.c |  1 -
 drivers/interconnect/qcom/qcs404.c  |  1 -
 drivers/interconnect/qcom/sdm660.c  |  1 -
 drivers/interconnect/qcom/smd-rpm.c |  2 +-
 drivers/interconnect/qcom/smd-rpm.h | 15 ---------------
 11 files changed, 7 insertions(+), 24 deletions(-)

diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c
index 863e8ba1daa2..b8ecf9538ab9 100644
--- a/drivers/interconnect/qcom/icc-rpm.c
+++ b/drivers/interconnect/qcom/icc-rpm.c
@@ -14,7 +14,6 @@
 #include <linux/regmap.h>
 #include <linux/slab.h>
 
-#include "smd-rpm.h"
 #include "icc-common.h"
 #include "icc-rpm.h"
 
diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
index ba840a436cc0..9b4ea4e39b9f 100644
--- a/drivers/interconnect/qcom/icc-rpm.h
+++ b/drivers/interconnect/qcom/icc-rpm.h
@@ -6,6 +6,8 @@
 #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
 #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
 
+#include <linux/soc/qcom/smd-rpm.h>
+
 #include <dt-bindings/interconnect/qcom,icc.h>
 
 #define RPM_BUS_MASTER_REQ	0x73616d62
@@ -121,4 +123,7 @@ enum qos_mode {
 int qnoc_probe(struct platform_device *pdev);
 int qnoc_remove(struct platform_device *pdev);
 
+bool qcom_icc_rpm_smd_available(void);
+int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val);
+
 #endif
diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c
index 5c4ba2f37c8e..196b05879896 100644
--- a/drivers/interconnect/qcom/msm8916.c
+++ b/drivers/interconnect/qcom/msm8916.c
@@ -15,7 +15,6 @@
 
 #include <dt-bindings/interconnect/qcom,msm8916.h>
 
-#include "smd-rpm.h"
 #include "icc-rpm.h"
 
 enum {
diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c
index caf0aefad668..639566dce45a 100644
--- a/drivers/interconnect/qcom/msm8939.c
+++ b/drivers/interconnect/qcom/msm8939.c
@@ -16,7 +16,6 @@
 
 #include <dt-bindings/interconnect/qcom,msm8939.h>
 
-#include "smd-rpm.h"
 #include "icc-rpm.h"
 
 enum {
diff --git a/drivers/interconnect/qcom/msm8974.c b/drivers/interconnect/qcom/msm8974.c
index 1828deaca443..968162213d40 100644
--- a/drivers/interconnect/qcom/msm8974.c
+++ b/drivers/interconnect/qcom/msm8974.c
@@ -38,7 +38,7 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include "smd-rpm.h"
+#include "icc-rpm.h"
 
 enum {
 	MSM8974_BIMC_MAS_AMPSS_M0 = 1,
diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c
index 20340fb62fe6..1f7e88a37acd 100644
--- a/drivers/interconnect/qcom/msm8996.c
+++ b/drivers/interconnect/qcom/msm8996.c
@@ -18,7 +18,6 @@
 #include <dt-bindings/interconnect/qcom,msm8996.h>
 
 #include "icc-rpm.h"
-#include "smd-rpm.h"
 #include "msm8996.h"
 
 static const char * const mm_intf_clocks[] = {
diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c
index a29cdb4fac03..cb636e67a5a4 100644
--- a/drivers/interconnect/qcom/qcm2290.c
+++ b/drivers/interconnect/qcom/qcm2290.c
@@ -19,7 +19,6 @@
 #include <linux/slab.h>
 
 #include "icc-rpm.h"
-#include "smd-rpm.h"
 
 enum {
 	QCM2290_MASTER_APPSS_PROC = 1,
diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c
index fae155344332..938283ddd0e3 100644
--- a/drivers/interconnect/qcom/qcs404.c
+++ b/drivers/interconnect/qcom/qcs404.c
@@ -13,7 +13,6 @@
 #include <linux/of_device.h>
 
 
-#include "smd-rpm.h"
 #include "icc-rpm.h"
 
 enum {
diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c
index 7ffaf70d62d3..003fc7d110a7 100644
--- a/drivers/interconnect/qcom/sdm660.c
+++ b/drivers/interconnect/qcom/sdm660.c
@@ -17,7 +17,6 @@
 #include <linux/slab.h>
 
 #include "icc-rpm.h"
-#include "smd-rpm.h"
 
 enum {
 	SDM660_MASTER_IPA = 1,
diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c
index dc8ff8d133a9..b0183262ba66 100644
--- a/drivers/interconnect/qcom/smd-rpm.c
+++ b/drivers/interconnect/qcom/smd-rpm.c
@@ -13,7 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/soc/qcom/smd-rpm.h>
 
-#include "smd-rpm.h"
+#include "icc-rpm.h"
 
 #define RPM_KEY_BW		0x00007762
 
diff --git a/drivers/interconnect/qcom/smd-rpm.h b/drivers/interconnect/qcom/smd-rpm.h
deleted file mode 100644
index ca9d0327b8ac..000000000000
--- a/drivers/interconnect/qcom/smd-rpm.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019, Linaro Ltd.
- * Author: Georgi Djakov <georgi.djakov@linaro.org>
- */
-
-#ifndef __DRIVERS_INTERCONNECT_QCOM_SMD_RPM_H
-#define __DRIVERS_INTERCONNECT_QCOM_SMD_RPM_H
-
-#include <linux/soc/qcom/smd-rpm.h>
-
-bool qcom_icc_rpm_smd_available(void);
-int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val);
-
-#endif

-- 
2.40.1

[PATCH 08/20] interconnect: qcom: smd-rpm: Add rpmcc handling skeleton code

[Konrad Dybcio]

Introduce qcom_icc_rpm_set_bus_rate() in preparation for handling RPM
clock resources within the interconnect framework. This lets us greatly
simplify all of the code handling, as setting the rate comes down to:

u32 rate_khz = max(clk.sleep_rate, clk.active_rate, clk_a.active_rate)
write_to_rpm(clock.description, rate_khz);

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/icc-rpm.h | 15 +++++++++++++++
 drivers/interconnect/qcom/smd-rpm.c | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
index 9b4ea4e39b9f..aec192321411 100644
--- a/drivers/interconnect/qcom/icc-rpm.h
+++ b/drivers/interconnect/qcom/icc-rpm.h
@@ -22,6 +22,18 @@ enum qcom_icc_type {
 	QCOM_ICC_QNOC,
 };
 
+/**
+ * struct rpm_clk_resource - RPM bus clock resource
+ * @resource_type: RPM resource type of the clock resource
+ * @clock_id: index of the clock resource of a specific resource type
+ * @branch: whether the resource represents a branch clock
+*/
+struct rpm_clk_resource {
+	u32 resource_type;
+	u32 clock_id;
+	bool branch;
+};
+
 #define NUM_BUS_CLKS	2
 
 /**
@@ -47,6 +59,7 @@ struct qcom_icc_provider {
 	int qos_offset;
 	u64 bus_clk_rate[NUM_BUS_CLKS];
 	struct clk_bulk_data bus_clks[NUM_BUS_CLKS];
+	const struct rpm_clk_resource *bus_clk_desc;
 	struct clk_bulk_data *intf_clks;
 	bool keep_alive;
 	bool is_on;
@@ -104,6 +117,7 @@ struct qcom_icc_desc {
 	struct qcom_icc_node * const *nodes;
 	size_t num_nodes;
 	const char * const *bus_clocks;
+	const struct rpm_clk_resource *bus_clk_desc;
 	const char * const *intf_clocks;
 	size_t num_intf_clocks;
 	bool keep_alive;
@@ -125,5 +139,6 @@ int qnoc_remove(struct platform_device *pdev);
 
 bool qcom_icc_rpm_smd_available(void);
 int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val);
+int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, u32 active_rate, u32 sleep_rate);
 
 #endif
diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c
index b0183262ba66..6c51e346b326 100644
--- a/drivers/interconnect/qcom/smd-rpm.c
+++ b/drivers/interconnect/qcom/smd-rpm.c
@@ -16,6 +16,7 @@
 #include "icc-rpm.h"
 
 #define RPM_KEY_BW		0x00007762
+#define QCOM_RPM_SMD_KEY_RATE	0x007a484b
 
 static struct qcom_smd_rpm *icc_smd_rpm;
 
@@ -44,6 +45,38 @@ int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val)
 }
 EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_send);
 
+int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, u32 active_rate, u32 sleep_rate)
+{
+	struct clk_smd_rpm_req req = {
+		.key = cpu_to_le32(QCOM_RPM_SMD_KEY_RATE),
+		.nbytes = cpu_to_le32(sizeof(u32)),
+	};
+	int ret;
+
+	/* Branch clocks are only on/off */
+	if (clk->branch) {
+		active_rate = !!active_rate;
+		sleep_rate = !!sleep_rate;
+	}
+
+	req.value = cpu_to_le32(active_rate);
+	ret = qcom_rpm_smd_write(icc_smd_rpm,
+				 QCOM_SMD_RPM_ACTIVE_STATE,
+				 clk->resource_type,
+				 clk->clock_id,
+				 &req, sizeof(req));
+	if (ret)
+		return ret;
+
+	req.value = cpu_to_le32(sleep_rate);
+	return qcom_rpm_smd_write(icc_smd_rpm,
+				  QCOM_SMD_RPM_SLEEP_STATE,
+				  clk->resource_type,
+				  clk->clock_id,
+				  &req, sizeof(req));
+}
+EXPORT_SYMBOL_GPL(qcom_icc_rpm_set_bus_rate);
+
 static int qcom_icc_rpm_smd_remove(struct platform_device *pdev)
 {
 	icc_smd_rpm = NULL;
@@ -60,6 +93,10 @@ static int qcom_icc_rpm_smd_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	/* We need the clock driver to kick things off first to avoid ugly races */
+	if (!qcom_smd_rpm_scaling_available())
+		return -EPROBE_DEFER;
+
 	return 0;
 }
 

-- 
2.40.1

[PATCH 09/20] interconnect: qcom: Add missing headers in icc-rpm.h

[Konrad Dybcio]

Currently the header does not provide all the required dependencies.
Fix it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/icc-rpm.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
index aec192321411..09abdd0c891e 100644
--- a/drivers/interconnect/qcom/icc-rpm.h
+++ b/drivers/interconnect/qcom/icc-rpm.h
@@ -6,6 +6,8 @@
 #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
 #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
 
+#include <linux/platform_device.h>
+#include <linux/interconnect-provider.h>
 #include <linux/soc/qcom/smd-rpm.h>
 
 #include <dt-bindings/interconnect/qcom,icc.h>

-- 
2.40.1

[PATCH 10/20] interconnect: qcom: Define RPM bus clocks

[Konrad Dybcio]

Add the definitions for RPM bus clocks that will be used by many
different platforms.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/Makefile         |  2 +-
 drivers/interconnect/qcom/icc-rpm-clocks.c | 66 ++++++++++++++++++++++++++++++
 drivers/interconnect/qcom/icc-rpm.h        | 13 ++++++
 3 files changed, 80 insertions(+), 1 deletion(-)

diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index ab988926433c..80d9d2da95d1 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -29,7 +29,7 @@ qnoc-sm8250-objs			:= sm8250.o
 qnoc-sm8350-objs			:= sm8350.o
 qnoc-sm8450-objs			:= sm8450.o
 qnoc-sm8550-objs			:= sm8550.o
-icc-smd-rpm-objs			:= smd-rpm.o icc-rpm.o
+icc-smd-rpm-objs			:= smd-rpm.o icc-rpm.o icc-rpm-clocks.o
 
 obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
 obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
diff --git a/drivers/interconnect/qcom/icc-rpm-clocks.c b/drivers/interconnect/qcom/icc-rpm-clocks.c
new file mode 100644
index 000000000000..a195bf32aff4
--- /dev/null
+++ b/drivers/interconnect/qcom/icc-rpm-clocks.c
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Linaro Ltd
+ */
+
+#include <linux/soc/qcom/smd-rpm.h>
+
+#include "icc-rpm.h"
+
+const struct rpm_clk_resource aggre1_clk = {
+	.resource_type = QCOM_SMD_RPM_AGGR_CLK,
+	.clock_id = 1,
+};
+
+const struct rpm_clk_resource aggre2_clk = {
+	.resource_type = QCOM_SMD_RPM_AGGR_CLK,
+	.clock_id = 2,
+};
+
+const struct rpm_clk_resource bimc_clk = {
+	.resource_type = QCOM_SMD_RPM_MEM_CLK,
+	.clock_id = 0,
+};
+
+const struct rpm_clk_resource bus_0_clk = {
+	.resource_type = QCOM_SMD_RPM_BUS_CLK,
+	.clock_id = 0,
+};
+
+const struct rpm_clk_resource bus_1_clk = {
+	.resource_type = QCOM_SMD_RPM_BUS_CLK,
+	.clock_id = 1,
+};
+
+const struct rpm_clk_resource bus_2_clk = {
+	.resource_type = QCOM_SMD_RPM_BUS_CLK,
+	.clock_id = 2,
+};
+
+const struct rpm_clk_resource mmaxi_0_clk = {
+	.resource_type = QCOM_SMD_RPM_MMAXI_CLK,
+	.clock_id = 0,
+};
+
+const struct rpm_clk_resource mmaxi_1_clk = {
+	.resource_type = QCOM_SMD_RPM_MMAXI_CLK,
+	.clock_id = 1,
+};
+
+const struct rpm_clk_resource qup_clk = {
+	.resource_type = QCOM_SMD_RPM_QUP_CLK,
+	.clock_id = 0,
+};
+
+/* Branch clocks */
+const struct rpm_clk_resource aggre1_branch_clk = {
+	.resource_type = QCOM_SMD_RPM_AGGR_CLK,
+	.clock_id = 1,
+	.branch = true,
+};
+
+const struct rpm_clk_resource aggre2_branch_clk = {
+	.resource_type = QCOM_SMD_RPM_AGGR_CLK,
+	.clock_id = 2,
+	.branch = true,
+};
diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
index 09abdd0c891e..e3df066fd94e 100644
--- a/drivers/interconnect/qcom/icc-rpm.h
+++ b/drivers/interconnect/qcom/icc-rpm.h
@@ -136,6 +136,19 @@ enum qos_mode {
 	NOC_QOS_MODE_BYPASS,
 };
 
+extern const struct rpm_clk_resource aggre1_clk;
+extern const struct rpm_clk_resource aggre2_clk;
+extern const struct rpm_clk_resource bimc_clk;
+extern const struct rpm_clk_resource bus_0_clk;
+extern const struct rpm_clk_resource bus_1_clk;
+extern const struct rpm_clk_resource bus_2_clk;
+extern const struct rpm_clk_resource mmaxi_0_clk;
+extern const struct rpm_clk_resource mmaxi_1_clk;
+extern const struct rpm_clk_resource qup_clk;
+
+extern const struct rpm_clk_resource aggre1_branch_clk;
+extern const struct rpm_clk_resource aggre2_branch_clk;
+
 int qnoc_probe(struct platform_device *pdev);
 int qnoc_remove(struct platform_device *pdev);
 

-- 
2.40.1

[PATCH 11/20] interconnect: qcom: sdm660: Hook up RPM bus clk definitions

[Konrad Dybcio]

Assign the necessary definitions to migrate to the new bus clock
handling mechanism.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/sdm660.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c
index 003fc7d110a7..5743ed680e8e 100644
--- a/drivers/interconnect/qcom/sdm660.c
+++ b/drivers/interconnect/qcom/sdm660.c
@@ -1511,6 +1511,7 @@ static const struct qcom_icc_desc sdm660_a2noc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = sdm660_a2noc_nodes,
 	.num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
+	.bus_clk_desc = &aggre2_clk,
 	.intf_clocks = a2noc_intf_clocks,
 	.num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
 	.regmap_cfg = &sdm660_a2noc_regmap_config,
@@ -1539,6 +1540,7 @@ static const struct qcom_icc_desc sdm660_bimc = {
 	.type = QCOM_ICC_BIMC,
 	.nodes = sdm660_bimc_nodes,
 	.num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
+	.bus_clk_desc = &bimc_clk,
 	.regmap_cfg = &sdm660_bimc_regmap_config,
 };
 
@@ -1593,6 +1595,7 @@ static const struct qcom_icc_desc sdm660_cnoc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = sdm660_cnoc_nodes,
 	.num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
+	.bus_clk_desc = &bus_2_clk,
 	.regmap_cfg = &sdm660_cnoc_regmap_config,
 };
 
@@ -1655,6 +1658,7 @@ static const struct qcom_icc_desc sdm660_mnoc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = sdm660_mnoc_nodes,
 	.num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
+	.bus_clk_desc = &mmaxi_0_clk,
 	.intf_clocks = mm_intf_clocks,
 	.num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
 	.regmap_cfg = &sdm660_mnoc_regmap_config,
@@ -1692,6 +1696,7 @@ static const struct qcom_icc_desc sdm660_snoc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = sdm660_snoc_nodes,
 	.num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
+	.bus_clk_desc = &bus_1_clk,
 	.regmap_cfg = &sdm660_snoc_regmap_config,
 };
 

-- 
2.40.1

[PATCH 12/20] interconnect: qcom: msm8996: Hook up RPM bus clk definitions

[Konrad Dybcio]

Assign the necessary definitions to migrate to the new bus clock
handling mechanism.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/msm8996.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c
index 1f7e88a37acd..a596f4035d2e 100644
--- a/drivers/interconnect/qcom/msm8996.c
+++ b/drivers/interconnect/qcom/msm8996.c
@@ -1840,6 +1840,7 @@ static const struct qcom_icc_desc msm8996_a1noc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = a1noc_nodes,
 	.num_nodes = ARRAY_SIZE(a1noc_nodes),
+	.bus_clk_desc = &aggre1_branch_clk,
 	.regmap_cfg = &msm8996_a1noc_regmap_config
 };
 
@@ -1861,6 +1862,7 @@ static const struct qcom_icc_desc msm8996_a2noc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = a2noc_nodes,
 	.num_nodes = ARRAY_SIZE(a2noc_nodes),
+	.bus_clk_desc = &aggre2_branch_clk,
 	.intf_clocks = a2noc_intf_clocks,
 	.num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
 	.regmap_cfg = &msm8996_a2noc_regmap_config
@@ -1889,6 +1891,7 @@ static const struct qcom_icc_desc msm8996_bimc = {
 	.type = QCOM_ICC_BIMC,
 	.nodes = bimc_nodes,
 	.num_nodes = ARRAY_SIZE(bimc_nodes),
+	.bus_clk_desc = &bimc_clk,
 	.regmap_cfg = &msm8996_bimc_regmap_config
 };
 
@@ -1947,6 +1950,7 @@ static const struct qcom_icc_desc msm8996_cnoc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = cnoc_nodes,
 	.num_nodes = ARRAY_SIZE(cnoc_nodes),
+	.bus_clk_desc = &bus_2_clk,
 	.regmap_cfg = &msm8996_cnoc_regmap_config
 };
 
@@ -2000,6 +2004,7 @@ static const struct qcom_icc_desc msm8996_mnoc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = mnoc_nodes,
 	.num_nodes = ARRAY_SIZE(mnoc_nodes),
+	.bus_clk_desc = &mmaxi_0_clk,
 	.intf_clocks = mm_intf_clocks,
 	.num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
 	.regmap_cfg = &msm8996_mnoc_regmap_config
@@ -2038,6 +2043,7 @@ static const struct qcom_icc_desc msm8996_pnoc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = pnoc_nodes,
 	.num_nodes = ARRAY_SIZE(pnoc_nodes),
+	.bus_clk_desc = &bus_0_clk,
 	.regmap_cfg = &msm8996_pnoc_regmap_config
 };
 
@@ -2082,6 +2088,7 @@ static const struct qcom_icc_desc msm8996_snoc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = snoc_nodes,
 	.num_nodes = ARRAY_SIZE(snoc_nodes),
+	.bus_clk_desc = &bus_1_clk,
 	.regmap_cfg = &msm8996_snoc_regmap_config
 };
 

-- 
2.40.1

[PATCH 13/20] interconnect: qcom: qcs404: Hook up RPM bus clk definitions

[Konrad Dybcio]

Assign the necessary definitions to migrate to the new bus clock
handling mechanism.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/qcs404.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c
index 938283ddd0e3..9deb4d81104e 100644
--- a/drivers/interconnect/qcom/qcs404.c
+++ b/drivers/interconnect/qcom/qcs404.c
@@ -984,6 +984,7 @@ static struct qcom_icc_node * const qcs404_bimc_nodes[] = {
 };
 
 static const struct qcom_icc_desc qcs404_bimc = {
+	.bus_clk_desc = &bimc_clk,
 	.nodes = qcs404_bimc_nodes,
 	.num_nodes = ARRAY_SIZE(qcs404_bimc_nodes),
 };
@@ -1038,6 +1039,7 @@ static struct qcom_icc_node * const qcs404_pcnoc_nodes[] = {
 };
 
 static const struct qcom_icc_desc qcs404_pcnoc = {
+	.bus_clk_desc = &bus_0_clk,
 	.nodes = qcs404_pcnoc_nodes,
 	.num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes),
 };
@@ -1066,6 +1068,7 @@ static struct qcom_icc_node * const qcs404_snoc_nodes[] = {
 };
 
 static const struct qcom_icc_desc qcs404_snoc = {
+	.bus_clk_desc = &bus_1_clk,
 	.nodes = qcs404_snoc_nodes,
 	.num_nodes = ARRAY_SIZE(qcs404_snoc_nodes),
 };

-- 
2.40.1

[PATCH 14/20] interconnect: qcom: msm8939: Hook up RPM bus clk definitions

[Konrad Dybcio]

Assign the necessary definitions to migrate to the new bus clock
handling mechanism.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/msm8939.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c
index 639566dce45a..94b11b590a8e 100644
--- a/drivers/interconnect/qcom/msm8939.c
+++ b/drivers/interconnect/qcom/msm8939.c
@@ -1284,6 +1284,7 @@ static const struct qcom_icc_desc msm8939_snoc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = msm8939_snoc_nodes,
 	.num_nodes = ARRAY_SIZE(msm8939_snoc_nodes),
+	.bus_clk_desc = &bus_1_clk,
 	.regmap_cfg = &msm8939_snoc_regmap_config,
 	.qos_offset = 0x7000,
 };
@@ -1304,6 +1305,7 @@ static const struct qcom_icc_desc msm8939_snoc_mm = {
 	.type = QCOM_ICC_NOC,
 	.nodes = msm8939_snoc_mm_nodes,
 	.num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes),
+	.bus_clk_desc = &bus_2_clk,
 	.regmap_cfg = &msm8939_snoc_regmap_config,
 	.qos_offset = 0x7000,
 };
@@ -1332,6 +1334,7 @@ static const struct qcom_icc_desc msm8939_bimc = {
 	.type = QCOM_ICC_BIMC,
 	.nodes = msm8939_bimc_nodes,
 	.num_nodes = ARRAY_SIZE(msm8939_bimc_nodes),
+	.bus_clk_desc = &bimc_clk,
 	.regmap_cfg = &msm8939_bimc_regmap_config,
 	.qos_offset = 0x8000,
 };
@@ -1403,6 +1406,7 @@ static const struct qcom_icc_desc msm8939_pcnoc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = msm8939_pcnoc_nodes,
 	.num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes),
+	.bus_clk_desc = &bus_0_clk,
 	.regmap_cfg = &msm8939_pcnoc_regmap_config,
 	.qos_offset = 0x7000,
 };

-- 
2.40.1

[PATCH 15/20] interconnect: qcom: msm8916: Hook up RPM bus clk definitions

[Konrad Dybcio]

Assign the necessary definitions to migrate to the new bus clock
handling mechanism.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/msm8916.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c
index 196b05879896..be2a190a8b52 100644
--- a/drivers/interconnect/qcom/msm8916.c
+++ b/drivers/interconnect/qcom/msm8916.c
@@ -1231,6 +1231,7 @@ static const struct qcom_icc_desc msm8916_snoc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = msm8916_snoc_nodes,
 	.num_nodes = ARRAY_SIZE(msm8916_snoc_nodes),
+	.bus_clk_desc = &bus_1_clk,
 	.regmap_cfg = &msm8916_snoc_regmap_config,
 	.qos_offset = 0x7000,
 };
@@ -1259,6 +1260,7 @@ static const struct qcom_icc_desc msm8916_bimc = {
 	.type = QCOM_ICC_BIMC,
 	.nodes = msm8916_bimc_nodes,
 	.num_nodes = ARRAY_SIZE(msm8916_bimc_nodes),
+	.bus_clk_desc = &bimc_clk,
 	.regmap_cfg = &msm8916_bimc_regmap_config,
 	.qos_offset = 0x8000,
 };
@@ -1328,6 +1330,7 @@ static const struct qcom_icc_desc msm8916_pcnoc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = msm8916_pcnoc_nodes,
 	.num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes),
+	.bus_clk_desc = &bus_0_clk,
 	.regmap_cfg = &msm8916_pcnoc_regmap_config,
 	.qos_offset = 0x7000,
 };

-- 
2.40.1

[PATCH 16/20] interconnect: qcom: qcm2290: Hook up RPM bus clk definitions

[Konrad Dybcio]

Assign the necessary definitions to migrate to the new bus clock
handling mechanism.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/qcm2290.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c
index cb636e67a5a4..2c7a76fab83c 100644
--- a/drivers/interconnect/qcom/qcm2290.c
+++ b/drivers/interconnect/qcom/qcm2290.c
@@ -1196,6 +1196,7 @@ static const struct qcom_icc_desc qcm2290_bimc = {
 	.type = QCOM_ICC_BIMC,
 	.nodes = qcm2290_bimc_nodes,
 	.num_nodes = ARRAY_SIZE(qcm2290_bimc_nodes),
+	.bus_clk_desc = &bimc_clk,
 	.regmap_cfg = &qcm2290_bimc_regmap_config,
 	/* M_REG_BASE() in vendor msm_bus_bimc_adhoc driver */
 	.qos_offset = 0x8000,
@@ -1251,6 +1252,7 @@ static const struct qcom_icc_desc qcm2290_cnoc = {
 	.type = QCOM_ICC_NOC,
 	.nodes = qcm2290_cnoc_nodes,
 	.num_nodes = ARRAY_SIZE(qcm2290_cnoc_nodes),
+	.bus_clk_desc = &bus_1_clk,
 	.regmap_cfg = &qcm2290_cnoc_regmap_config,
 };
 
@@ -1292,6 +1294,7 @@ static const struct qcom_icc_desc qcm2290_snoc = {
 	.type = QCOM_ICC_QNOC,
 	.nodes = qcm2290_snoc_nodes,
 	.num_nodes = ARRAY_SIZE(qcm2290_snoc_nodes),
+	.bus_clk_desc = &bus_2_clk,
 	.regmap_cfg = &qcm2290_snoc_regmap_config,
 	/* Vendor DT node fab-sys_noc property 'qcom,base-offset' */
 	.qos_offset = 0x15000,
@@ -1306,6 +1309,7 @@ static const struct qcom_icc_desc qcm2290_qup_virt = {
 	.type = QCOM_ICC_QNOC,
 	.nodes = qcm2290_qup_virt_nodes,
 	.num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes),
+	.bus_clk_desc = &qup_clk,
 };
 
 static struct qcom_icc_node * const qcm2290_mmnrt_virt_nodes[] = {
@@ -1319,6 +1323,7 @@ static const struct qcom_icc_desc qcm2290_mmnrt_virt = {
 	.type = QCOM_ICC_QNOC,
 	.nodes = qcm2290_mmnrt_virt_nodes,
 	.num_nodes = ARRAY_SIZE(qcm2290_mmnrt_virt_nodes),
+	.bus_clk_desc = &mmaxi_0_clk,
 	.regmap_cfg = &qcm2290_snoc_regmap_config,
 	.qos_offset = 0x15000,
 };
@@ -1333,6 +1338,7 @@ static const struct qcom_icc_desc qcm2290_mmrt_virt = {
 	.type = QCOM_ICC_QNOC,
 	.nodes = qcm2290_mmrt_virt_nodes,
 	.num_nodes = ARRAY_SIZE(qcm2290_mmrt_virt_nodes),
+	.bus_clk_desc = &mmaxi_1_clk,
 	.regmap_cfg = &qcm2290_snoc_regmap_config,
 	.qos_offset = 0x15000,
 };

-- 
2.40.1

[PATCH 17/20] interconnect: qcom: icc-rpm: Control bus rpmcc from icc

[Konrad Dybcio]

The sole purpose of bus clocks that were previously registered with
rpmcc was to convey the aggregated bandwidth to RPM. There's no good
reason to keep them outside the interconnect framework, as it only
adds to the plentiful complexity.

Add the required code to handle these clocks from within SMD RPM ICC.

RPM-owned bus clocks are no longer considered a thing, but sadly we
have to allow for the existence of HLOS-owned bus clocks, as some
(mostly older) SoCs (ab)use these for bus scaling (e.g. MSM8998 and
&mmcc AHB_CLK_SRC).

This in turn is trivially solved with a single *clk, which is filled
and used iff qp.bus_clk_desc is absent and we have a "bus" clock-names
entry in the DT node.

This change should(tm) be fully compatible with all sorts of old
Device Trees as far as the interconnect functionality goes (modulo
abusing bus clock handles, but that's a mistake in and of itself).

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/icc-rpm.c | 116 +++++++++++++++++++-----------------
 drivers/interconnect/qcom/icc-rpm.h |  13 ++--
 drivers/interconnect/qcom/msm8996.c |   1 -
 drivers/interconnect/qcom/sdm660.c  |   1 -
 4 files changed, 66 insertions(+), 65 deletions(-)

diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c
index b8ecf9538ab9..d08eefd963f4 100644
--- a/drivers/interconnect/qcom/icc-rpm.c
+++ b/drivers/interconnect/qcom/icc-rpm.c
@@ -49,7 +49,7 @@
 #define NOC_QOS_MODE_FIXED_VAL		0x0
 #define NOC_QOS_MODE_BYPASS_VAL		0x2
 
-#define ICC_BUS_CLK_MIN_RATE		19200000ULL
+#define ICC_BUS_CLK_MIN_RATE		19200ULL /* kHz */
 
 static int qcom_icc_set_qnoc_qos(struct icc_node *src)
 {
@@ -338,11 +338,10 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 	struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL;
 	struct icc_provider *provider;
 	u64 sum_bw;
-	u64 rate;
+	u64 active_rate, sleep_rate;
 	u64 agg_avg[QCOM_ICC_NUM_BUCKETS], agg_peak[QCOM_ICC_NUM_BUCKETS];
 	u64 max_agg_avg;
-	int ret, i;
-	int bucket;
+	int ret;
 
 	src_qn = src->data;
 	if (dst)
@@ -364,49 +363,50 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 			return ret;
 	}
 
-	for (i = 0; i < qp->num_bus_clks; i++) {
-		/*
-		 * Use WAKE bucket for active clock, otherwise, use SLEEP bucket
-		 * for other clocks.  If a platform doesn't set interconnect
-		 * path tags, by default use sleep bucket for all clocks.
-		 *
-		 * Note, AMC bucket is not supported yet.
-		 */
-		if (!strcmp(qp->bus_clks[i].id, "bus_a"))
-			bucket = QCOM_ICC_BUCKET_WAKE;
-		else
-			bucket = QCOM_ICC_BUCKET_SLEEP;
-
-		rate = icc_units_to_bps(max(agg_avg[bucket], agg_peak[bucket]));
-		do_div(rate, src_qn->buswidth);
-		rate = min_t(u64, rate, LONG_MAX);
-
-		/*
-		 * Downstream checks whether the requested rate is zero, but it makes little sense
-		 * to vote for a value that's below the lower threshold, so let's not do so.
-		 */
-		if (bucket == QCOM_ICC_BUCKET_WAKE && qp->keep_alive)
-			rate = max(ICC_BUS_CLK_MIN_RATE, rate);
-
-		if (qp->bus_clk_rate[i] == rate)
-			continue;
-
-		ret = clk_set_rate(qp->bus_clks[i].clk, rate);
-		if (ret) {
-			pr_err("%s clk_set_rate error: %d\n",
-			       qp->bus_clks[i].id, ret);
+	/* Some providers don't have a bus clock to scale */
+	if (!qp->bus_clk_desc)
+		return 0;
+
+	/* Intentionally keep the rates in kHz as that's what RPM accepts */
+	active_rate = max(agg_avg[QCOM_SMD_RPM_ACTIVE_STATE],
+			  agg_peak[QCOM_SMD_RPM_ACTIVE_STATE]);
+	do_div(active_rate, src_qn->buswidth);
+
+	sleep_rate = max(agg_avg[QCOM_SMD_RPM_SLEEP_STATE],
+			 agg_peak[QCOM_SMD_RPM_SLEEP_STATE]);
+	do_div(sleep_rate, src_qn->buswidth);
+
+	/*
+	 * Downstream checks whether the requested rate is zero, but it makes little sense
+	 * to vote for a value that's below the lower threshold, so let's not do so.
+	 */
+	if (qp->keep_alive)
+		active_rate = max(ICC_BUS_CLK_MIN_RATE, active_rate);
+
+	/* Some providers have a non-RPM-owned bus clock - convert kHz->Hz for the CCF */
+	if (qp->bus_clk)
+		return clk_set_rate(qp->bus_clk, 1000ULL * max(active_rate, sleep_rate));
+
+	/* RPM only accepts <=INT_MAX rates */
+	active_rate = min_t(u32, active_rate, INT_MAX);
+	sleep_rate = min_t(u32, sleep_rate, INT_MAX);
+
+	if ((active_rate != qp->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE]) ||
+	    (sleep_rate != qp->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE])) {
+		ret = qcom_icc_rpm_set_bus_rate(qp->bus_clk_desc,
+						active_rate,
+						sleep_rate);
+		if (ret)
 			return ret;
-		}
-		qp->bus_clk_rate[i] = rate;
 	}
 
+	/* Cache the rate after we've successfully commited it to RPM */
+	qp->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE] = active_rate;
+	qp->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE] = sleep_rate;
+
 	return 0;
 }
 
-static const char * const bus_clocks[] = {
-	"bus", "bus_a",
-};
-
 int qnoc_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -448,6 +448,18 @@ int qnoc_probe(struct platform_device *pdev)
 	if (!qp->intf_clks)
 		return -ENOMEM;
 
+	if (desc->bus_clk_desc) {
+		qp->bus_clk_desc = devm_kzalloc(dev, sizeof(*qp->bus_clk_desc),
+						GFP_KERNEL);
+		if (!qp->bus_clk_desc)
+			return -ENOMEM;
+
+		qp->bus_clk_desc = desc->bus_clk_desc;
+	} else if (!IS_ERR(devm_clk_get(dev, "bus"))) {
+		/* Some older SoCs may have a single non-RPM-owned bus clock. */
+		qp->bus_clk = devm_clk_get(dev, "bus");
+	}
+
 	data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
 			    GFP_KERNEL);
 	if (!data)
@@ -457,10 +469,6 @@ int qnoc_probe(struct platform_device *pdev)
 	for (i = 0; i < cd_num; i++)
 		qp->intf_clks[i].id = cds[i];
 
-	qp->num_bus_clks = desc->no_clk_scaling ? 0 : NUM_BUS_CLKS;
-	for (i = 0; i < qp->num_bus_clks; i++)
-		qp->bus_clks[i].id = bus_clocks[i];
-
 	qp->keep_alive = desc->keep_alive;
 	qp->type = desc->type;
 	qp->qos_offset = desc->qos_offset;
@@ -490,13 +498,11 @@ int qnoc_probe(struct platform_device *pdev)
 	}
 
 regmap_done:
-	ret = devm_clk_bulk_get(dev, qp->num_bus_clks, qp->bus_clks);
-	if (ret)
-		return ret;
-
-	ret = clk_bulk_prepare_enable(qp->num_bus_clks, qp->bus_clks);
-	if (ret)
-		return ret;
+	if (qp->bus_clk) {
+		ret = clk_prepare_enable(qp->bus_clk);
+		if (ret)
+			return ret;
+	}
 
 	ret = devm_clk_bulk_get(dev, qp->num_intf_clks, qp->intf_clks);
 	if (ret)
@@ -566,7 +572,8 @@ int qnoc_probe(struct platform_device *pdev)
 	icc_provider_deregister(provider);
 err_remove_nodes:
 	icc_nodes_remove(provider);
-	clk_bulk_disable_unprepare(qp->num_bus_clks, qp->bus_clks);
+	if (qp->bus_clk)
+		clk_disable_unprepare(qp->bus_clk);
 
 	return ret;
 }
@@ -578,7 +585,8 @@ int qnoc_remove(struct platform_device *pdev)
 
 	icc_provider_deregister(&qp->provider);
 	icc_nodes_remove(&qp->provider);
-	clk_bulk_disable_unprepare(qp->num_bus_clks, qp->bus_clks);
+	if (qp->bus_clk)
+		clk_disable_unprepare(qp->bus_clk);
 
 	return 0;
 }
diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
index e3df066fd94e..2c8c0399378b 100644
--- a/drivers/interconnect/qcom/icc-rpm.h
+++ b/drivers/interconnect/qcom/icc-rpm.h
@@ -36,32 +36,29 @@ struct rpm_clk_resource {
 	bool branch;
 };
 
-#define NUM_BUS_CLKS	2
-
 /**
  * struct qcom_icc_provider - Qualcomm specific interconnect provider
  * @provider: generic interconnect provider
- * @num_bus_clks: the total number of bus_clks clk_bulk_data entries (0 or 2)
  * @num_intf_clks: the total number of intf_clks clk_bulk_data entries
  * @type: the ICC provider type
  * @regmap: regmap for QoS registers read/write access
  * @bus_clk_rate: bus clock rate in Hz
- * @bus_clks: the clk_bulk_data table of bus clocks
+ * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks
  * @intf_clks: a clk_bulk_data array of interface clocks
+ * @bus_clk: a pointer to a HLOS-owned bus clock
  * @qos_offset: offset to QoS registers
  * @keep_alive: whether to always keep a minimum vote on the bus clocks
  * @is_on: whether the bus is powered on
  */
 struct qcom_icc_provider {
 	struct icc_provider provider;
-	int num_bus_clks;
 	int num_intf_clks;
 	enum qcom_icc_type type;
 	struct regmap *regmap;
 	int qos_offset;
-	u64 bus_clk_rate[NUM_BUS_CLKS];
-	struct clk_bulk_data bus_clks[NUM_BUS_CLKS];
+	u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM];
 	const struct rpm_clk_resource *bus_clk_desc;
+	struct clk *bus_clk;
 	struct clk_bulk_data *intf_clks;
 	bool keep_alive;
 	bool is_on;
@@ -118,12 +115,10 @@ struct qcom_icc_node {
 struct qcom_icc_desc {
 	struct qcom_icc_node * const *nodes;
 	size_t num_nodes;
-	const char * const *bus_clocks;
 	const struct rpm_clk_resource *bus_clk_desc;
 	const char * const *intf_clocks;
 	size_t num_intf_clocks;
 	bool keep_alive;
-	bool no_clk_scaling;
 	enum qcom_icc_type type;
 	const struct regmap_config *regmap_cfg;
 	int qos_offset;
diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c
index a596f4035d2e..8081b3cb1025 100644
--- a/drivers/interconnect/qcom/msm8996.c
+++ b/drivers/interconnect/qcom/msm8996.c
@@ -1818,7 +1818,6 @@ static const struct qcom_icc_desc msm8996_a0noc = {
 	.num_nodes = ARRAY_SIZE(a0noc_nodes),
 	.intf_clocks = a0noc_intf_clocks,
 	.num_intf_clocks = ARRAY_SIZE(a0noc_intf_clocks),
-	.no_clk_scaling = true,
 	.regmap_cfg = &msm8996_a0noc_regmap_config
 };
 
diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c
index 5743ed680e8e..211fa1fa569c 100644
--- a/drivers/interconnect/qcom/sdm660.c
+++ b/drivers/interconnect/qcom/sdm660.c
@@ -1618,7 +1618,6 @@ static const struct qcom_icc_desc sdm660_gnoc = {
 	.nodes = sdm660_gnoc_nodes,
 	.num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
 	.regmap_cfg = &sdm660_gnoc_regmap_config,
-	.no_clk_scaling = true,
 };
 
 static struct qcom_icc_node * const sdm660_mnoc_nodes[] = {

-- 
2.40.1

[PATCH 18/20] interconnect: qcom: icc-rpm: Fix bucket number

[Konrad Dybcio]

SMD RPM only provides two buckets, one each for the active-only and
active-sleep RPM contexts. Use the correct constant to allocate and
operate on them.

Fixes: dcbce7b0a79c ("interconnect: qcom: icc-rpm: Support multiple buckets")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/icc-rpm.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c
index d08eefd963f4..db84bf56bde3 100644
--- a/drivers/interconnect/qcom/icc-rpm.c
+++ b/drivers/interconnect/qcom/icc-rpm.c
@@ -249,7 +249,7 @@ static void qcom_icc_pre_bw_aggregate(struct icc_node *node)
 	size_t i;
 
 	qn = node->data;
-	for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
+	for (i = 0; i < QCOM_SMD_RPM_STATE_NUM; i++) {
 		qn->sum_avg[i] = 0;
 		qn->max_peak[i] = 0;
 	}
@@ -275,7 +275,7 @@ static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
 	if (!tag)
 		tag = QCOM_ICC_TAG_ALWAYS;
 
-	for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
+	for (i = 0; i < QCOM_SMD_RPM_STATE_NUM; i++) {
 		if (tag & BIT(i)) {
 			qn->sum_avg[i] += avg_bw;
 			qn->max_peak[i] = max_t(u32, qn->max_peak[i], peak_bw);
@@ -300,11 +300,11 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider,
 {
 	struct icc_node *node;
 	struct qcom_icc_node *qn;
-	u64 sum_avg[QCOM_ICC_NUM_BUCKETS];
+	u64 sum_avg[QCOM_SMD_RPM_STATE_NUM];
 	int i;
 
 	/* Initialise aggregate values */
-	for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
+	for (i = 0; i < QCOM_SMD_RPM_STATE_NUM; i++) {
 		agg_avg[i] = 0;
 		agg_peak[i] = 0;
 	}
@@ -317,7 +317,7 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider,
 	 */
 	list_for_each_entry(node, &provider->nodes, node_list) {
 		qn = node->data;
-		for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
+		for (i = 0; i < QCOM_SMD_RPM_STATE_NUM; i++) {
 			if (qn->channels)
 				sum_avg[i] = div_u64(qn->sum_avg[i], qn->channels);
 			else
@@ -328,7 +328,7 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider,
 	}
 
 	/* Find maximum values across all buckets */
-	for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++)
+	for (i = 0; i < QCOM_SMD_RPM_STATE_NUM; i++)
 		*max_agg_avg = max_t(u64, *max_agg_avg, agg_avg[i]);
 }
 
@@ -339,7 +339,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 	struct icc_provider *provider;
 	u64 sum_bw;
 	u64 active_rate, sleep_rate;
-	u64 agg_avg[QCOM_ICC_NUM_BUCKETS], agg_peak[QCOM_ICC_NUM_BUCKETS];
+	u64 agg_avg[QCOM_SMD_RPM_STATE_NUM], agg_peak[QCOM_SMD_RPM_STATE_NUM];
 	u64 max_agg_avg;
 	int ret;
 

-- 
2.40.1

[PATCH 19/20] interconnect: qcom: icc-rpm: Set bandwidth on both contexts

[Konrad Dybcio]

Up until now, for some reason we've only been setting bandwidth values
on the active-only context. That pretty much meant that RPM could lift
all votes when entering sleep mode. Or never sleep at all.

That in turn could potentially break things like USB wakeup, as the
connection between APSS and SNoC/PNoC would simply be dead.

Set the values appropriately.

Fixes: 30c8fa3ec61a ("interconnect: qcom: Add MSM8916 interconnect provider driver")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/icc-rpm.c | 54 +++++++++++++++++++------------------
 1 file changed, 28 insertions(+), 26 deletions(-)

diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c
index db84bf56bde3..59be704364bb 100644
--- a/drivers/interconnect/qcom/icc-rpm.c
+++ b/drivers/interconnect/qcom/icc-rpm.c
@@ -205,34 +205,39 @@ static int qcom_icc_qos_set(struct icc_node *node)
 	}
 }
 
-static int qcom_icc_rpm_set(struct qcom_icc_node *qn, u64 sum_bw)
+static int qcom_icc_rpm_set(struct qcom_icc_node *qn, u64 *bw)
 {
-	int ret = 0;
+	int ret, rpm_ctx = 0;
+	u64 bw_bps;
 
 	if (qn->qos.ap_owned)
 		return 0;
 
-	if (qn->mas_rpm_id != -1) {
-		ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
-					    RPM_BUS_MASTER_REQ,
-					    qn->mas_rpm_id,
-					    sum_bw);
-		if (ret) {
-			pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
-			       qn->mas_rpm_id, ret);
-			return ret;
+	for (rpm_ctx = 0; rpm_ctx < QCOM_SMD_RPM_STATE_NUM; rpm_ctx++) {
+		bw_bps = icc_units_to_bps(bw[rpm_ctx]);
+
+		if (qn->mas_rpm_id != -1) {
+			ret = qcom_icc_rpm_smd_send(rpm_ctx,
+						    RPM_BUS_MASTER_REQ,
+						    qn->mas_rpm_id,
+						    bw_bps);
+			if (ret) {
+				pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
+				qn->mas_rpm_id, ret);
+				return ret;
+			}
 		}
-	}
 
-	if (qn->slv_rpm_id != -1) {
-		ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
-					    RPM_BUS_SLAVE_REQ,
-					    qn->slv_rpm_id,
-					    sum_bw);
-		if (ret) {
-			pr_err("qcom_icc_rpm_smd_send slv %d error %d\n",
-			       qn->slv_rpm_id, ret);
-			return ret;
+		if (qn->slv_rpm_id != -1) {
+			ret = qcom_icc_rpm_smd_send(rpm_ctx,
+						    RPM_BUS_SLAVE_REQ,
+						    qn->slv_rpm_id,
+						    bw_bps);
+			if (ret) {
+				pr_err("qcom_icc_rpm_smd_send slv %d error %d\n",
+				qn->slv_rpm_id, ret);
+				return ret;
+			}
 		}
 	}
 
@@ -337,7 +342,6 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 	struct qcom_icc_provider *qp;
 	struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL;
 	struct icc_provider *provider;
-	u64 sum_bw;
 	u64 active_rate, sleep_rate;
 	u64 agg_avg[QCOM_SMD_RPM_STATE_NUM], agg_peak[QCOM_SMD_RPM_STATE_NUM];
 	u64 max_agg_avg;
@@ -351,14 +355,12 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 
 	qcom_icc_bus_aggregate(provider, agg_avg, agg_peak, &max_agg_avg);
 
-	sum_bw = icc_units_to_bps(max_agg_avg);
-
-	ret = qcom_icc_rpm_set(src_qn, sum_bw);
+	ret = qcom_icc_rpm_set(src_qn, agg_avg);
 	if (ret)
 		return ret;
 
 	if (dst_qn) {
-		ret = qcom_icc_rpm_set(dst_qn, sum_bw);
+		ret = qcom_icc_rpm_set(dst_qn, agg_avg);
 		if (ret)
 			return ret;
 	}

-- 
2.40.1

[PATCH 20/20] interconnect: qcom: Divide clk rate by src node bus width

[Konrad Dybcio]

Ever since the introduction of SMD RPM ICC, we've been dividing the
clock rate by the wrong bus width. This has resulted in:

- setting wrong (mostly too low) rates, affecting performance
  - most often /2 or /4
  - things like DDR never hit their full potential
  - the rates were only correct if src bus width == dst bus width
    for all src, dst pairs on a given bus

- Qualcomm using the same wrong logic in their BSP driver in msm-5.x
  that ships in production devices today

- me losing my sanity trying to find this

Resolve it by using dst_qn, if it exists.

Fixes: 5e4e6c4d3ae0 ("interconnect: qcom: Add QCS404 interconnect provider driver")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/icc-rpm.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c
index 59be704364bb..58e2a8b1b7c3 100644
--- a/drivers/interconnect/qcom/icc-rpm.c
+++ b/drivers/interconnect/qcom/icc-rpm.c
@@ -340,7 +340,7 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider,
 static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 {
 	struct qcom_icc_provider *qp;
-	struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL;
+	struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL, *qn = NULL;
 	struct icc_provider *provider;
 	u64 active_rate, sleep_rate;
 	u64 agg_avg[QCOM_SMD_RPM_STATE_NUM], agg_peak[QCOM_SMD_RPM_STATE_NUM];
@@ -353,6 +353,8 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 	provider = src->provider;
 	qp = to_qcom_provider(provider);
 
+	qn = dst_qn ? dst_qn : src_qn;
+
 	qcom_icc_bus_aggregate(provider, agg_avg, agg_peak, &max_agg_avg);
 
 	ret = qcom_icc_rpm_set(src_qn, agg_avg);
@@ -372,11 +374,11 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 	/* Intentionally keep the rates in kHz as that's what RPM accepts */
 	active_rate = max(agg_avg[QCOM_SMD_RPM_ACTIVE_STATE],
 			  agg_peak[QCOM_SMD_RPM_ACTIVE_STATE]);
-	do_div(active_rate, src_qn->buswidth);
+	do_div(active_rate, qn->buswidth);
 
 	sleep_rate = max(agg_avg[QCOM_SMD_RPM_SLEEP_STATE],
 			 agg_peak[QCOM_SMD_RPM_SLEEP_STATE]);
-	do_div(sleep_rate, src_qn->buswidth);
+	do_div(sleep_rate, qn->buswidth);
 
 	/*
 	 * Downstream checks whether the requested rate is zero, but it makes little sense

-- 
2.40.1

Re: [PATCH 20/20] interconnect: qcom: Divide clk rate by src node bus width

[Konrad Dybcio]

Note: the commit title is wrong (src -> dst obviously).
Thanks Stephan for spotting this.

Konrad

On 30.05.2023 12:20, Konrad Dybcio wrote:
> Ever since the introduction of SMD RPM ICC, we've been dividing the
> clock rate by the wrong bus width. This has resulted in:
> 
> - setting wrong (mostly too low) rates, affecting performance
>   - most often /2 or /4
>   - things like DDR never hit their full potential
>   - the rates were only correct if src bus width == dst bus width
>     for all src, dst pairs on a given bus
> 
> - Qualcomm using the same wrong logic in their BSP driver in msm-5.x
>   that ships in production devices today
> 
> - me losing my sanity trying to find this
> 
> Resolve it by using dst_qn, if it exists.
> 
> Fixes: 5e4e6c4d3ae0 ("interconnect: qcom: Add QCS404 interconnect provider driver")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  drivers/interconnect/qcom/icc-rpm.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c
> index 59be704364bb..58e2a8b1b7c3 100644
> --- a/drivers/interconnect/qcom/icc-rpm.c
> +++ b/drivers/interconnect/qcom/icc-rpm.c
> @@ -340,7 +340,7 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider,
>  static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
>  {
>  	struct qcom_icc_provider *qp;
> -	struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL;
> +	struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL, *qn = NULL;
>  	struct icc_provider *provider;
>  	u64 active_rate, sleep_rate;
>  	u64 agg_avg[QCOM_SMD_RPM_STATE_NUM], agg_peak[QCOM_SMD_RPM_STATE_NUM];
> @@ -353,6 +353,8 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
>  	provider = src->provider;
>  	qp = to_qcom_provider(provider);
>  
> +	qn = dst_qn ? dst_qn : src_qn;
> +
>  	qcom_icc_bus_aggregate(provider, agg_avg, agg_peak, &max_agg_avg);
>  
>  	ret = qcom_icc_rpm_set(src_qn, agg_avg);
> @@ -372,11 +374,11 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
>  	/* Intentionally keep the rates in kHz as that's what RPM accepts */
>  	active_rate = max(agg_avg[QCOM_SMD_RPM_ACTIVE_STATE],
>  			  agg_peak[QCOM_SMD_RPM_ACTIVE_STATE]);
> -	do_div(active_rate, src_qn->buswidth);
> +	do_div(active_rate, qn->buswidth);
>  
>  	sleep_rate = max(agg_avg[QCOM_SMD_RPM_SLEEP_STATE],
>  			 agg_peak[QCOM_SMD_RPM_SLEEP_STATE]);
> -	do_div(sleep_rate, src_qn->buswidth);
> +	do_div(sleep_rate, qn->buswidth);
>  
>  	/*
>  	 * Downstream checks whether the requested rate is zero, but it makes little sense
> 

Re: [PATCH 17/20] interconnect: qcom: icc-rpm: Control bus rpmcc from icc

[Konrad Dybcio]

On 30.05.2023 12:20, Konrad Dybcio wrote:
> The sole purpose of bus clocks that were previously registered with
> rpmcc was to convey the aggregated bandwidth to RPM. There's no good
> reason to keep them outside the interconnect framework, as it only
> adds to the plentiful complexity.
> 
> Add the required code to handle these clocks from within SMD RPM ICC.
> 
> RPM-owned bus clocks are no longer considered a thing, but sadly we
> have to allow for the existence of HLOS-owned bus clocks, as some
> (mostly older) SoCs (ab)use these for bus scaling (e.g. MSM8998 and
> &mmcc AHB_CLK_SRC).
> 
> This in turn is trivially solved with a single *clk, which is filled
> and used iff qp.bus_clk_desc is absent and we have a "bus" clock-names
> entry in the DT node.
> 
> This change should(tm) be fully compatible with all sorts of old
> Device Trees as far as the interconnect functionality goes (modulo
> abusing bus clock handles, but that's a mistake in and of itself).
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
[...]

> +	/* Some providers don't have a bus clock to scale */
> +	if (!qp->bus_clk_desc)
if (!qp->bus_clk_desc && !qp->bus_clk)

Konrad
> +		return 0;
> +
> +	/* Intentionally keep the rates in kHz as that's what RPM accepts */
> +	active_rate = max(agg_avg[QCOM_SMD_RPM_ACTIVE_STATE],
> +			  agg_peak[QCOM_SMD_RPM_ACTIVE_STATE]);
> +	do_div(active_rate, src_qn->buswidth);
> +
> +	sleep_rate = max(agg_avg[QCOM_SMD_RPM_SLEEP_STATE],
> +			 agg_peak[QCOM_SMD_RPM_SLEEP_STATE]);
> +	do_div(sleep_rate, src_qn->buswidth);
> +
> +	/*
> +	 * Downstream checks whether the requested rate is zero, but it makes little sense
> +	 * to vote for a value that's below the lower threshold, so let's not do so.
> +	 */
> +	if (qp->keep_alive)
> +		active_rate = max(ICC_BUS_CLK_MIN_RATE, active_rate);
> +
> +	/* Some providers have a non-RPM-owned bus clock - convert kHz->Hz for the CCF */
> +	if (qp->bus_clk)
> +		return clk_set_rate(qp->bus_clk, 1000ULL * max(active_rate, sleep_rate));
> +
> +	/* RPM only accepts <=INT_MAX rates */
> +	active_rate = min_t(u32, active_rate, INT_MAX);
> +	sleep_rate = min_t(u32, sleep_rate, INT_MAX);
> +
> +	if ((active_rate != qp->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE]) ||
> +	    (sleep_rate != qp->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE])) {
> +		ret = qcom_icc_rpm_set_bus_rate(qp->bus_clk_desc,
> +						active_rate,
> +						sleep_rate);
> +		if (ret)
>  			return ret;
> -		}
> -		qp->bus_clk_rate[i] = rate;
>  	}
>  
> +	/* Cache the rate after we've successfully commited it to RPM */
> +	qp->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE] = active_rate;
> +	qp->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE] = sleep_rate;
> +
>  	return 0;
>  }
>  
> -static const char * const bus_clocks[] = {
> -	"bus", "bus_a",
> -};
> -
>  int qnoc_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -448,6 +448,18 @@ int qnoc_probe(struct platform_device *pdev)
>  	if (!qp->intf_clks)
>  		return -ENOMEM;
>  
> +	if (desc->bus_clk_desc) {
> +		qp->bus_clk_desc = devm_kzalloc(dev, sizeof(*qp->bus_clk_desc),
> +						GFP_KERNEL);
> +		if (!qp->bus_clk_desc)
> +			return -ENOMEM;
> +
> +		qp->bus_clk_desc = desc->bus_clk_desc;
> +	} else if (!IS_ERR(devm_clk_get(dev, "bus"))) {
> +		/* Some older SoCs may have a single non-RPM-owned bus clock. */
> +		qp->bus_clk = devm_clk_get(dev, "bus");
> +	}
> +
>  	data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
>  			    GFP_KERNEL);
>  	if (!data)
> @@ -457,10 +469,6 @@ int qnoc_probe(struct platform_device *pdev)
>  	for (i = 0; i < cd_num; i++)
>  		qp->intf_clks[i].id = cds[i];
>  
> -	qp->num_bus_clks = desc->no_clk_scaling ? 0 : NUM_BUS_CLKS;
> -	for (i = 0; i < qp->num_bus_clks; i++)
> -		qp->bus_clks[i].id = bus_clocks[i];
> -
>  	qp->keep_alive = desc->keep_alive;
>  	qp->type = desc->type;
>  	qp->qos_offset = desc->qos_offset;
> @@ -490,13 +498,11 @@ int qnoc_probe(struct platform_device *pdev)
>  	}
>  
>  regmap_done:
> -	ret = devm_clk_bulk_get(dev, qp->num_bus_clks, qp->bus_clks);
> -	if (ret)
> -		return ret;
> -
> -	ret = clk_bulk_prepare_enable(qp->num_bus_clks, qp->bus_clks);
> -	if (ret)
> -		return ret;
> +	if (qp->bus_clk) {
> +		ret = clk_prepare_enable(qp->bus_clk);
> +		if (ret)
> +			return ret;
> +	}
>  
>  	ret = devm_clk_bulk_get(dev, qp->num_intf_clks, qp->intf_clks);
>  	if (ret)
> @@ -566,7 +572,8 @@ int qnoc_probe(struct platform_device *pdev)
>  	icc_provider_deregister(provider);
>  err_remove_nodes:
>  	icc_nodes_remove(provider);
> -	clk_bulk_disable_unprepare(qp->num_bus_clks, qp->bus_clks);
> +	if (qp->bus_clk)
> +		clk_disable_unprepare(qp->bus_clk);
>  
>  	return ret;
>  }
> @@ -578,7 +585,8 @@ int qnoc_remove(struct platform_device *pdev)
>  
>  	icc_provider_deregister(&qp->provider);
>  	icc_nodes_remove(&qp->provider);
> -	clk_bulk_disable_unprepare(qp->num_bus_clks, qp->bus_clks);
> +	if (qp->bus_clk)
> +		clk_disable_unprepare(qp->bus_clk);
>  
>  	return 0;
>  }
> diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
> index e3df066fd94e..2c8c0399378b 100644
> --- a/drivers/interconnect/qcom/icc-rpm.h
> +++ b/drivers/interconnect/qcom/icc-rpm.h
> @@ -36,32 +36,29 @@ struct rpm_clk_resource {
>  	bool branch;
>  };
>  
> -#define NUM_BUS_CLKS	2
> -
>  /**
>   * struct qcom_icc_provider - Qualcomm specific interconnect provider
>   * @provider: generic interconnect provider
> - * @num_bus_clks: the total number of bus_clks clk_bulk_data entries (0 or 2)
>   * @num_intf_clks: the total number of intf_clks clk_bulk_data entries
>   * @type: the ICC provider type
>   * @regmap: regmap for QoS registers read/write access
>   * @bus_clk_rate: bus clock rate in Hz
> - * @bus_clks: the clk_bulk_data table of bus clocks
> + * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks
>   * @intf_clks: a clk_bulk_data array of interface clocks
> + * @bus_clk: a pointer to a HLOS-owned bus clock
>   * @qos_offset: offset to QoS registers
>   * @keep_alive: whether to always keep a minimum vote on the bus clocks
>   * @is_on: whether the bus is powered on
>   */
>  struct qcom_icc_provider {
>  	struct icc_provider provider;
> -	int num_bus_clks;
>  	int num_intf_clks;
>  	enum qcom_icc_type type;
>  	struct regmap *regmap;
>  	int qos_offset;
> -	u64 bus_clk_rate[NUM_BUS_CLKS];
> -	struct clk_bulk_data bus_clks[NUM_BUS_CLKS];
> +	u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM];
>  	const struct rpm_clk_resource *bus_clk_desc;
> +	struct clk *bus_clk;
>  	struct clk_bulk_data *intf_clks;
>  	bool keep_alive;
>  	bool is_on;
> @@ -118,12 +115,10 @@ struct qcom_icc_node {
>  struct qcom_icc_desc {
>  	struct qcom_icc_node * const *nodes;
>  	size_t num_nodes;
> -	const char * const *bus_clocks;
>  	const struct rpm_clk_resource *bus_clk_desc;
>  	const char * const *intf_clocks;
>  	size_t num_intf_clocks;
>  	bool keep_alive;
> -	bool no_clk_scaling;
>  	enum qcom_icc_type type;
>  	const struct regmap_config *regmap_cfg;
>  	int qos_offset;
> diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c
> index a596f4035d2e..8081b3cb1025 100644
> --- a/drivers/interconnect/qcom/msm8996.c
> +++ b/drivers/interconnect/qcom/msm8996.c
> @@ -1818,7 +1818,6 @@ static const struct qcom_icc_desc msm8996_a0noc = {
>  	.num_nodes = ARRAY_SIZE(a0noc_nodes),
>  	.intf_clocks = a0noc_intf_clocks,
>  	.num_intf_clocks = ARRAY_SIZE(a0noc_intf_clocks),
> -	.no_clk_scaling = true,
>  	.regmap_cfg = &msm8996_a0noc_regmap_config
>  };
>  
> diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c
> index 5743ed680e8e..211fa1fa569c 100644
> --- a/drivers/interconnect/qcom/sdm660.c
> +++ b/drivers/interconnect/qcom/sdm660.c
> @@ -1618,7 +1618,6 @@ static const struct qcom_icc_desc sdm660_gnoc = {
>  	.nodes = sdm660_gnoc_nodes,
>  	.num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
>  	.regmap_cfg = &sdm660_gnoc_regmap_config,
> -	.no_clk_scaling = true,
>  };
>  
>  static struct qcom_icc_node * const sdm660_mnoc_nodes[] = {
> 

Re: [PATCH 20/20] interconnect: qcom: Divide clk rate by src node bus width

[Konrad Dybcio]

On 30.05.2023 12:20, Konrad Dybcio wrote:
> Ever since the introduction of SMD RPM ICC, we've been dividing the
> clock rate by the wrong bus width. This has resulted in:
> 
> - setting wrong (mostly too low) rates, affecting performance
>   - most often /2 or /4
>   - things like DDR never hit their full potential
>   - the rates were only correct if src bus width == dst bus width
>     for all src, dst pairs on a given bus
> 
> - Qualcomm using the same wrong logic in their BSP driver in msm-5.x
>   that ships in production devices today
> 
> - me losing my sanity trying to find this
> 
> Resolve it by using dst_qn, if it exists.
> 
> Fixes: 5e4e6c4d3ae0 ("interconnect: qcom: Add QCS404 interconnect provider driver")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
The problem is deeper.

Chatting with Stephan (+CC), we tackled a few issues (that I will send
fixes for in v2):

1. qcom_icc_rpm_set() should take per-node (src_qn->sum_avg, dst_qn->sum_avg)
   and NOT aggregated bw (unless you want ALL of your nodes on a given provider
   to "go very fast")

2. the aggregate bw/clk rate calculation should use the node-specific bus widths
   and not only the bus width of the src/dst node, otherwise the average bw
   values will be utterly meaningless

3. thanks to (1) and (2) qcom_icc_bus_aggregate() can be remodeled to instead
   calculate the clock rates for the two rpm contexts, which we can then max()
   and pass on to the ratesetting call


----8<---- Cutting off Stephan's seal of approval, this is my thinking ----

4. I *think* Qualcomm really made a mistake in their msm-5.4 driver where they
   took most of the logic from the current -next state and should have been
   setting the rate based on the *DST* provider, or at least that's my
   understanding trying to read the "known good" msm-4.19 driver
   (which remembers msm-3.0 lol).. Or maybe we should keep src but ensure there's
   also a final (dst, dst) vote cast:

provider->inter_set = false // current state upstream

setting apps_proc<->slv_bimc_snoc
setting mas_bimc_snoc<->slv_snoc_cnoc
setting mas_snoc_cnoc<->qhs_sdc2


provider->inter_set = true // I don't think there's effectively a difference?

setting apps_proc<->slv_bimc_snoc
setting slv_bimc_snoc<->mas_bimc_snoc
setting mas_bimc_snoc<->slv_snoc_cnoc
setting slv_snoc_cnoc<->mas_snoc_cnoc
setting mas_snoc_cnoc<->qhs_sdc2

all the (mas|slv)_bus1_bus2 are very wide whereas the target nodes are usually
4-, 8- or 16-wide, which without this patch or something equivalent decimates
(or actually 2^n-ates) the calculated rates..

Konrad


>  drivers/interconnect/qcom/icc-rpm.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c
> index 59be704364bb..58e2a8b1b7c3 100644
> --- a/drivers/interconnect/qcom/icc-rpm.c
> +++ b/drivers/interconnect/qcom/icc-rpm.c
> @@ -340,7 +340,7 @@ static void qcom_icc_bus_aggregate(struct icc_provider *provider,
>  static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
>  {
>  	struct qcom_icc_provider *qp;
> -	struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL;
> +	struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL, *qn = NULL;
>  	struct icc_provider *provider;
>  	u64 active_rate, sleep_rate;
>  	u64 agg_avg[QCOM_SMD_RPM_STATE_NUM], agg_peak[QCOM_SMD_RPM_STATE_NUM];
> @@ -353,6 +353,8 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
>  	provider = src->provider;
>  	qp = to_qcom_provider(provider);
>  
> +	qn = dst_qn ? dst_qn : src_qn;
> +
>  	qcom_icc_bus_aggregate(provider, agg_avg, agg_peak, &max_agg_avg);
>  
>  	ret = qcom_icc_rpm_set(src_qn, agg_avg);
> @@ -372,11 +374,11 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
>  	/* Intentionally keep the rates in kHz as that's what RPM accepts */
>  	active_rate = max(agg_avg[QCOM_SMD_RPM_ACTIVE_STATE],
>  			  agg_peak[QCOM_SMD_RPM_ACTIVE_STATE]);
> -	do_div(active_rate, src_qn->buswidth);
> +	do_div(active_rate, qn->buswidth);
>  
>  	sleep_rate = max(agg_avg[QCOM_SMD_RPM_SLEEP_STATE],
>  			 agg_peak[QCOM_SMD_RPM_SLEEP_STATE]);
> -	do_div(sleep_rate, src_qn->buswidth);
> +	do_div(sleep_rate, qn->buswidth);
>  
>  	/*
>  	 * Downstream checks whether the requested rate is zero, but it makes little sense
> 

Re: [PATCH 20/20] interconnect: qcom: Divide clk rate by src node bus width

[Stephan Gerhold]

On Tue, May 30, 2023 at 06:32:04PM +0200, Konrad Dybcio wrote:
> On 30.05.2023 12:20, Konrad Dybcio wrote:
> > Ever since the introduction of SMD RPM ICC, we've been dividing the
> > clock rate by the wrong bus width. This has resulted in:
> > 
> > - setting wrong (mostly too low) rates, affecting performance
> >   - most often /2 or /4
> >   - things like DDR never hit their full potential
> >   - the rates were only correct if src bus width == dst bus width
> >     for all src, dst pairs on a given bus
> > 
> > - Qualcomm using the same wrong logic in their BSP driver in msm-5.x
> >   that ships in production devices today
> > 
> > - me losing my sanity trying to find this
> > 
> > Resolve it by using dst_qn, if it exists.
> > 
> > Fixes: 5e4e6c4d3ae0 ("interconnect: qcom: Add QCS404 interconnect provider driver")
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> > ---
> The problem is deeper.
> 
> Chatting with Stephan (+CC), we tackled a few issues (that I will send
> fixes for in v2):
> 
> 1. qcom_icc_rpm_set() should take per-node (src_qn->sum_avg, dst_qn->sum_avg)
>    and NOT aggregated bw (unless you want ALL of your nodes on a given provider
>    to "go very fast")
> 
> 2. the aggregate bw/clk rate calculation should use the node-specific bus widths
>    and not only the bus width of the src/dst node, otherwise the average bw
>    values will be utterly meaningless
> 

The peak bandwidth / clock rate is wrong as well if you have two paths
with different buswidths on the same bus/NoC. (If someone is interested
in details I can post my specific example I had in the chat, it shows
this more clearly.)

> 3. thanks to (1) and (2) qcom_icc_bus_aggregate() can be remodeled to instead
>    calculate the clock rates for the two rpm contexts, which we can then max()
>    and pass on to the ratesetting call
> 

Sounds good.

> 
> ----8<---- Cutting off Stephan's seal of approval, this is my thinking ----
> 
> 4. I *think* Qualcomm really made a mistake in their msm-5.4 driver where they
>    took most of the logic from the current -next state and should have been
>    setting the rate based on the *DST* provider, or at least that's my
>    understanding trying to read the "known good" msm-4.19 driver
>    (which remembers msm-3.0 lol).. Or maybe we should keep src but ensure there's
>    also a final (dst, dst) vote cast:
> 
> provider->inter_set = false // current state upstream
> 
> setting apps_proc<->slv_bimc_snoc
> setting mas_bimc_snoc<->slv_snoc_cnoc
> setting mas_snoc_cnoc<->qhs_sdc2
> 
> 
> provider->inter_set = true // I don't think there's effectively a difference?
> 
> setting apps_proc<->slv_bimc_snoc
> setting slv_bimc_snoc<->mas_bimc_snoc
> setting mas_bimc_snoc<->slv_snoc_cnoc
> setting slv_snoc_cnoc<->mas_snoc_cnoc
> setting mas_snoc_cnoc<->qhs_sdc2
> 

I think with our proposed changes above it does no longer matter if a
node is passed as "src" or "dst". This means in your example above you
just waste additional time setting the bandwidth twice for
slv_bimc_snoc, mas_bimc_snoc, slv_snoc_cnoc and mas_snoc_cnoc.
The final outcome is the same with or without "inter_set".

Thanks,
Stephan

Re: [PATCH 01/20] soc: qcom: smd-rpm: Add QCOM_SMD_RPM_STATE_NUM

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> Add a preprocessor define to indicate the number of RPM contexts/states.
> While at it, use tabs instead of spaces for the existing entries.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   include/linux/soc/qcom/smd-rpm.h | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h
> index 2990f425fdef..99499e4b080e 100644
> --- a/include/linux/soc/qcom/smd-rpm.h
> +++ b/include/linux/soc/qcom/smd-rpm.h
> @@ -4,8 +4,9 @@
>   
>   struct qcom_smd_rpm;
>   
> -#define QCOM_SMD_RPM_ACTIVE_STATE        0
> -#define QCOM_SMD_RPM_SLEEP_STATE         1
> +#define QCOM_SMD_RPM_ACTIVE_STATE	0
> +#define QCOM_SMD_RPM_SLEEP_STATE	1

This is what we usually try to abstain from: ident changes + functional 
changes. I'd say, leave spaces as is and just add the new entry.

> +#define QCOM_SMD_RPM_STATE_NUM		2
>   
>   /*
>    * Constants used for addressing resources in the RPM.
> 

-- 
With best wishes
Dmitry

Re: [PATCH 02/20] clk: qcom: smd-rpm: Move some RPM resources to the common header

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> In preparation for handling the bus clocks in the icc driver, carve out
> some defines and a struct definition to the common rpm header.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/clk/qcom/clk-smd-rpm.c   | 13 -------------
>   include/linux/soc/qcom/smd-rpm.h | 15 +++++++++++++++
>   2 files changed, 15 insertions(+), 13 deletions(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 05/20] interconnect: qcom: icc-rpm: Introduce keep_alive

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> The downstream kernel employs the concept of "keeping the bus alive"
> by voting for the minimum (XO/19.2MHz) rate at all times on certain
> (well, most) buses.
> This is a very important thing to have, as if we
> either have a lackluster/wrong DT that doesn't specify a (high enough)
> vote on a certain bus, we may lose access to the entire bus altogether.
> This is very apparent when we only start introducing interconnect
> support on a given platform and haven't yet introduced voting on all
> peripherals.
> 
> The same can happen if we only have a single driver casting a vote on
> a certain bus and that driver exits/crashes/suspends.
> 
> The keepalive vote is limited to the ACTIVE bucket, as keeping a
> permanent vote on the SLEEP one could prevent the platform from properly
> entering low power mode states.
> 
> Introduce the very same concept, with a slight twist: the vendor
> kernel checks whether the rate is zero before setting the minimum
> vote, but that's rather silly, as in doing so we're at the mercy
> of CCF. Instead, explicitly clamp the rates to always be >= 19.2 MHz
> for providers with keep_alive=true.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/icc-rpm.c | 10 ++++++++++
>   drivers/interconnect/qcom/icc-rpm.h |  3 +++
>   2 files changed, 13 insertions(+)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 06/20] interconnect: qcom: icc-rpm: Allow negative QoS offset

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> In some very very very very unfortunate cases, the correct offset of
> the QoS registers will be.. negative. One such case is MSM8998, where
> The DDR BWMON occupies what-would-be-the-BIMC-base which we usually
> take into account with the register calculation, making the actual
> BIMC node start at what-would-be-the-BIMC-base+0x300.

Can we turn one of devices into a child of another device? This way we 
won't have to cope with negative offsets.

> 
> In order to keep the calculation code sane, the simplest - however
> ugly it may be - solution is to allow the offset to be negative.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/icc-rpm.h | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
> index d2c04c400cad..ba840a436cc0 100644
> --- a/drivers/interconnect/qcom/icc-rpm.h
> +++ b/drivers/interconnect/qcom/icc-rpm.h
> @@ -29,10 +29,10 @@ enum qcom_icc_type {
>    * @num_intf_clks: the total number of intf_clks clk_bulk_data entries
>    * @type: the ICC provider type
>    * @regmap: regmap for QoS registers read/write access
> - * @qos_offset: offset to QoS registers
>    * @bus_clk_rate: bus clock rate in Hz
>    * @bus_clks: the clk_bulk_data table of bus clocks
>    * @intf_clks: a clk_bulk_data array of interface clocks
> + * @qos_offset: offset to QoS registers

This can be kept in place.

>    * @keep_alive: whether to always keep a minimum vote on the bus clocks
>    * @is_on: whether the bus is powered on
>    */
> @@ -42,7 +42,7 @@ struct qcom_icc_provider {
>   	int num_intf_clks;
>   	enum qcom_icc_type type;
>   	struct regmap *regmap;
> -	unsigned int qos_offset;
> +	int qos_offset;
>   	u64 bus_clk_rate[NUM_BUS_CLKS];
>   	struct clk_bulk_data bus_clks[NUM_BUS_CLKS];
>   	struct clk_bulk_data *intf_clks;
> @@ -108,7 +108,7 @@ struct qcom_icc_desc {
>   	bool no_clk_scaling;
>   	enum qcom_icc_type type;
>   	const struct regmap_config *regmap_cfg;
> -	unsigned int qos_offset;
> +	int qos_offset;
>   };
>   
>   /* Valid for all bus types */
> 

-- 
With best wishes
Dmitry

Re: [PATCH 07/20] interconnect: qcom: Fold smd-rpm.h into icc-rpm.h

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> smd-rpm.h is not very useful as-is and both files are always included
> anyway.. Combine them.

If we ever add interconnect driver for non-SMD RPM platforms (like 
MSM8960/APQ8064), we can just ignore the smd part.

> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/icc-rpm.c |  1 -
>   drivers/interconnect/qcom/icc-rpm.h |  5 +++++
>   drivers/interconnect/qcom/msm8916.c |  1 -
>   drivers/interconnect/qcom/msm8939.c |  1 -
>   drivers/interconnect/qcom/msm8974.c |  2 +-
>   drivers/interconnect/qcom/msm8996.c |  1 -
>   drivers/interconnect/qcom/qcm2290.c |  1 -
>   drivers/interconnect/qcom/qcs404.c  |  1 -
>   drivers/interconnect/qcom/sdm660.c  |  1 -
>   drivers/interconnect/qcom/smd-rpm.c |  2 +-
>   drivers/interconnect/qcom/smd-rpm.h | 15 ---------------
>   11 files changed, 7 insertions(+), 24 deletions(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 06/20] interconnect: qcom: icc-rpm: Allow negative QoS offset

[Konrad Dybcio]

On 1.06.2023 11:56, Dmitry Baryshkov wrote:
> On 30/05/2023 13:20, Konrad Dybcio wrote:
>> In some very very very very unfortunate cases, the correct offset of
>> the QoS registers will be.. negative. One such case is MSM8998, where
>> The DDR BWMON occupies what-would-be-the-BIMC-base which we usually
>> take into account with the register calculation, making the actual
>> BIMC node start at what-would-be-the-BIMC-base+0x300.
> 
> Can we turn one of devices into a child of another device? This way we won't have to cope with negative offsets.
Let's try to get more insight how they're correlated, but that sounds
like an option.. 8996 will need this as well..

Konrad
> 
>>
>> In order to keep the calculation code sane, the simplest - however
>> ugly it may be - solution is to allow the offset to be negative.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>>   drivers/interconnect/qcom/icc-rpm.h | 6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
>> index d2c04c400cad..ba840a436cc0 100644
>> --- a/drivers/interconnect/qcom/icc-rpm.h
>> +++ b/drivers/interconnect/qcom/icc-rpm.h
>> @@ -29,10 +29,10 @@ enum qcom_icc_type {
>>    * @num_intf_clks: the total number of intf_clks clk_bulk_data entries
>>    * @type: the ICC provider type
>>    * @regmap: regmap for QoS registers read/write access
>> - * @qos_offset: offset to QoS registers
>>    * @bus_clk_rate: bus clock rate in Hz
>>    * @bus_clks: the clk_bulk_data table of bus clocks
>>    * @intf_clks: a clk_bulk_data array of interface clocks
>> + * @qos_offset: offset to QoS registers
> 
> This can be kept in place.
> 
>>    * @keep_alive: whether to always keep a minimum vote on the bus clocks
>>    * @is_on: whether the bus is powered on
>>    */
>> @@ -42,7 +42,7 @@ struct qcom_icc_provider {
>>       int num_intf_clks;
>>       enum qcom_icc_type type;
>>       struct regmap *regmap;
>> -    unsigned int qos_offset;
>> +    int qos_offset;
>>       u64 bus_clk_rate[NUM_BUS_CLKS];
>>       struct clk_bulk_data bus_clks[NUM_BUS_CLKS];
>>       struct clk_bulk_data *intf_clks;
>> @@ -108,7 +108,7 @@ struct qcom_icc_desc {
>>       bool no_clk_scaling;
>>       enum qcom_icc_type type;
>>       const struct regmap_config *regmap_cfg;
>> -    unsigned int qos_offset;
>> +    int qos_offset;
>>   };
>>     /* Valid for all bus types */
>>
> 

Re: [PATCH 07/20] interconnect: qcom: Fold smd-rpm.h into icc-rpm.h

[Konrad Dybcio]

On 1.06.2023 11:57, Dmitry Baryshkov wrote:
> On 30/05/2023 13:20, Konrad Dybcio wrote:
>> smd-rpm.h is not very useful as-is and both files are always included
>> anyway.. Combine them.
> 
> If we ever add interconnect driver for non-SMD RPM platforms (like MSM8960/APQ8064), we can just ignore the smd part.
icc-rpm sends requests via smd so that doesn't sound unifiable

Konrad
> 
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>>   drivers/interconnect/qcom/icc-rpm.c |  1 -
>>   drivers/interconnect/qcom/icc-rpm.h |  5 +++++
>>   drivers/interconnect/qcom/msm8916.c |  1 -
>>   drivers/interconnect/qcom/msm8939.c |  1 -
>>   drivers/interconnect/qcom/msm8974.c |  2 +-
>>   drivers/interconnect/qcom/msm8996.c |  1 -
>>   drivers/interconnect/qcom/qcm2290.c |  1 -
>>   drivers/interconnect/qcom/qcs404.c  |  1 -
>>   drivers/interconnect/qcom/sdm660.c  |  1 -
>>   drivers/interconnect/qcom/smd-rpm.c |  2 +-
>>   drivers/interconnect/qcom/smd-rpm.h | 15 ---------------
>>   11 files changed, 7 insertions(+), 24 deletions(-)
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> 

Re: [PATCH 08/20] interconnect: qcom: smd-rpm: Add rpmcc handling skeleton code

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> Introduce qcom_icc_rpm_set_bus_rate() in preparation for handling RPM
> clock resources within the interconnect framework. This lets us greatly
> simplify all of the code handling, as setting the rate comes down to:
> 
> u32 rate_khz = max(clk.sleep_rate, clk.active_rate, clk_a.active_rate)
> write_to_rpm(clock.description, rate_khz);
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/icc-rpm.h | 15 +++++++++++++++
>   drivers/interconnect/qcom/smd-rpm.c | 37 +++++++++++++++++++++++++++++++++++++
>   2 files changed, 52 insertions(+)
> 
> diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
> index 9b4ea4e39b9f..aec192321411 100644
> --- a/drivers/interconnect/qcom/icc-rpm.h
> +++ b/drivers/interconnect/qcom/icc-rpm.h
> @@ -22,6 +22,18 @@ enum qcom_icc_type {
>   	QCOM_ICC_QNOC,
>   };
>   
> +/**
> + * struct rpm_clk_resource - RPM bus clock resource
> + * @resource_type: RPM resource type of the clock resource
> + * @clock_id: index of the clock resource of a specific resource type
> + * @branch: whether the resource represents a branch clock
> +*/
> +struct rpm_clk_resource {
> +	u32 resource_type;
> +	u32 clock_id;
> +	bool branch;
> +};
> +
>   #define NUM_BUS_CLKS	2
>   
>   /**
> @@ -47,6 +59,7 @@ struct qcom_icc_provider {
>   	int qos_offset;
>   	u64 bus_clk_rate[NUM_BUS_CLKS];
>   	struct clk_bulk_data bus_clks[NUM_BUS_CLKS];
> +	const struct rpm_clk_resource *bus_clk_desc;
>   	struct clk_bulk_data *intf_clks;
>   	bool keep_alive;
>   	bool is_on;
> @@ -104,6 +117,7 @@ struct qcom_icc_desc {
>   	struct qcom_icc_node * const *nodes;
>   	size_t num_nodes;
>   	const char * const *bus_clocks;
> +	const struct rpm_clk_resource *bus_clk_desc;
>   	const char * const *intf_clocks;
>   	size_t num_intf_clocks;
>   	bool keep_alive;
> @@ -125,5 +139,6 @@ int qnoc_remove(struct platform_device *pdev);
>   
>   bool qcom_icc_rpm_smd_available(void);
>   int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val);
> +int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, u32 active_rate, u32 sleep_rate);
>   
>   #endif
> diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c
> index b0183262ba66..6c51e346b326 100644
> --- a/drivers/interconnect/qcom/smd-rpm.c
> +++ b/drivers/interconnect/qcom/smd-rpm.c
> @@ -16,6 +16,7 @@
>   #include "icc-rpm.h"
>   
>   #define RPM_KEY_BW		0x00007762
> +#define QCOM_RPM_SMD_KEY_RATE	0x007a484b

Nit: can we move all RPM keys to some common header?

>   
>   static struct qcom_smd_rpm *icc_smd_rpm;
>   
> @@ -44,6 +45,38 @@ int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val)
>   }
>   EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_send);
>   
> +int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, u32 active_rate, u32 sleep_rate)
> +{
> +	struct clk_smd_rpm_req req = {
> +		.key = cpu_to_le32(QCOM_RPM_SMD_KEY_RATE),
> +		.nbytes = cpu_to_le32(sizeof(u32)),
> +	};
> +	int ret;
> +
> +	/* Branch clocks are only on/off */
> +	if (clk->branch) {
> +		active_rate = !!active_rate;
> +		sleep_rate = !!sleep_rate;
> +	}
> +
> +	req.value = cpu_to_le32(active_rate);
> +	ret = qcom_rpm_smd_write(icc_smd_rpm,
> +				 QCOM_SMD_RPM_ACTIVE_STATE,
> +				 clk->resource_type,
> +				 clk->clock_id,
> +				 &req, sizeof(req));
> +	if (ret)
> +		return ret;
> +
> +	req.value = cpu_to_le32(sleep_rate);
> +	return qcom_rpm_smd_write(icc_smd_rpm,
> +				  QCOM_SMD_RPM_SLEEP_STATE,
> +				  clk->resource_type,
> +				  clk->clock_id,
> +				  &req, sizeof(req));
> +}
> +EXPORT_SYMBOL_GPL(qcom_icc_rpm_set_bus_rate);
> +
>   static int qcom_icc_rpm_smd_remove(struct platform_device *pdev)
>   {
>   	icc_smd_rpm = NULL;
> @@ -60,6 +93,10 @@ static int qcom_icc_rpm_smd_probe(struct platform_device *pdev)
>   		return -ENODEV;
>   	}
>   
> +	/* We need the clock driver to kick things off first to avoid ugly races */
> +	if (!qcom_smd_rpm_scaling_available())
> +		return -EPROBE_DEFER;


This should not be a part of this commit.

> +
>   	return 0;
>   }
>   
> 

-- 
With best wishes
Dmitry

Re: [PATCH 01/20] soc: qcom: smd-rpm: Add QCOM_SMD_RPM_STATE_NUM

[Konrad Dybcio]

On 1.06.2023 11:20, Dmitry Baryshkov wrote:
> On 30/05/2023 13:20, Konrad Dybcio wrote:
>> Add a preprocessor define to indicate the number of RPM contexts/states.
>> While at it, use tabs instead of spaces for the existing entries.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>>   include/linux/soc/qcom/smd-rpm.h | 5 +++--
>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h
>> index 2990f425fdef..99499e4b080e 100644
>> --- a/include/linux/soc/qcom/smd-rpm.h
>> +++ b/include/linux/soc/qcom/smd-rpm.h
>> @@ -4,8 +4,9 @@
>>     struct qcom_smd_rpm;
>>   -#define QCOM_SMD_RPM_ACTIVE_STATE        0
>> -#define QCOM_SMD_RPM_SLEEP_STATE         1
>> +#define QCOM_SMD_RPM_ACTIVE_STATE    0
>> +#define QCOM_SMD_RPM_SLEEP_STATE    1
> 
> This is what we usually try to abstain from: ident changes + functional changes. I'd say, leave spaces as is and just add the new entry.
I think I might wanna turn this into an enum..

Also, I'd like to rename it but that's a story for another day, as
it'd require even more messy merging..

Konrad
> 
>> +#define QCOM_SMD_RPM_STATE_NUM        2
>>     /*
>>    * Constants used for addressing resources in the RPM.
>>
> 

Re: [PATCH 06/20] interconnect: qcom: icc-rpm: Allow negative QoS offset

[Dmitry Baryshkov]

On 01/06/2023 12:59, Konrad Dybcio wrote:
> 
> 
> On 1.06.2023 11:56, Dmitry Baryshkov wrote:
>> On 30/05/2023 13:20, Konrad Dybcio wrote:
>>> In some very very very very unfortunate cases, the correct offset of
>>> the QoS registers will be.. negative. One such case is MSM8998, where
>>> The DDR BWMON occupies what-would-be-the-BIMC-base which we usually
>>> take into account with the register calculation, making the actual
>>> BIMC node start at what-would-be-the-BIMC-base+0x300.
>>
>> Can we turn one of devices into a child of another device? This way we won't have to cope with negative offsets.
> Let's try to get more insight how they're correlated, but that sounds
> like an option.. 8996 will need this as well..

Anyway, I think this commit should be moved closer to the actual use.

> 
> Konrad
>>
>>>
>>> In order to keep the calculation code sane, the simplest - however
>>> ugly it may be - solution is to allow the offset to be negative.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
>>>    drivers/interconnect/qcom/icc-rpm.h | 6 +++---
>>>    1 file changed, 3 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
>>> index d2c04c400cad..ba840a436cc0 100644
>>> --- a/drivers/interconnect/qcom/icc-rpm.h
>>> +++ b/drivers/interconnect/qcom/icc-rpm.h
>>> @@ -29,10 +29,10 @@ enum qcom_icc_type {
>>>     * @num_intf_clks: the total number of intf_clks clk_bulk_data entries
>>>     * @type: the ICC provider type
>>>     * @regmap: regmap for QoS registers read/write access
>>> - * @qos_offset: offset to QoS registers
>>>     * @bus_clk_rate: bus clock rate in Hz
>>>     * @bus_clks: the clk_bulk_data table of bus clocks
>>>     * @intf_clks: a clk_bulk_data array of interface clocks
>>> + * @qos_offset: offset to QoS registers
>>
>> This can be kept in place.
>>
>>>     * @keep_alive: whether to always keep a minimum vote on the bus clocks
>>>     * @is_on: whether the bus is powered on
>>>     */
>>> @@ -42,7 +42,7 @@ struct qcom_icc_provider {
>>>        int num_intf_clks;
>>>        enum qcom_icc_type type;
>>>        struct regmap *regmap;
>>> -    unsigned int qos_offset;
>>> +    int qos_offset;
>>>        u64 bus_clk_rate[NUM_BUS_CLKS];
>>>        struct clk_bulk_data bus_clks[NUM_BUS_CLKS];
>>>        struct clk_bulk_data *intf_clks;
>>> @@ -108,7 +108,7 @@ struct qcom_icc_desc {
>>>        bool no_clk_scaling;
>>>        enum qcom_icc_type type;
>>>        const struct regmap_config *regmap_cfg;
>>> -    unsigned int qos_offset;
>>> +    int qos_offset;
>>>    };
>>>      /* Valid for all bus types */
>>>
>>

-- 
With best wishes
Dmitry

Re: [PATCH 09/20] interconnect: qcom: Add missing headers in icc-rpm.h

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> Currently the header does not provide all the required dependencies.
> Fix it.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/icc-rpm.h | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
> index aec192321411..09abdd0c891e 100644
> --- a/drivers/interconnect/qcom/icc-rpm.h
> +++ b/drivers/interconnect/qcom/icc-rpm.h
> @@ -6,6 +6,8 @@
>   #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
>   #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
>   
> +#include <linux/platform_device.h>
> +#include <linux/interconnect-provider.h>

Alphabetic order?

With that fixed:

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

>   #include <linux/soc/qcom/smd-rpm.h>
>   
>   #include <dt-bindings/interconnect/qcom,icc.h>
> 

-- 
With best wishes
Dmitry

Re: [PATCH 03/20] clk: qcom: smd-rpm: Separate out interconnect bus clocks

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> The interconnect bus clocks are now handled within the ICC framework.

now = since commit ??
Or should this commit be moved closer the end of the series?

> They still however need to get a kickstart *before* we call
> clk_smd_rpm_enable_scaling(), or RPM will assume that they should all
> be running at 0 kHz and the system will inevitably die.
> 
> Separate them out to ensure such a kickstart can still take place.
> 
> As a happy accident, the file got smaller:
> 
> Total: Before=41951, After=41555, chg -0.94%
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/clk/qcom/clk-smd-rpm.c | 278 +++++++++++++++++------------------------
>   1 file changed, 115 insertions(+), 163 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
> index 937cb1515968..b63f946e4520 100644
> --- a/drivers/clk/qcom/clk-smd-rpm.c
> +++ b/drivers/clk/qcom/clk-smd-rpm.c
> @@ -167,6 +167,14 @@ struct clk_smd_rpm {
>   struct rpm_smd_clk_desc {
>   	struct clk_smd_rpm **clks;
>   	size_t num_clks;
> +
> +	/*
> +	 * Interconnect clocks are managed by the icc framework, this driver
> +	 * only kickstarts them so that they don't get gated between
> +	 * clk_smd_rpm_enable_scaling() and interconnect driver initialization.
> +	 */
> +	struct clk_smd_rpm **icc_clks;
> +	size_t num_icc_clks;
>   	bool scaling_before_handover;
>   };
>   
> @@ -498,13 +506,69 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000);
>   DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000);
>   DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000);
>   
> +static struct clk_smd_rpm *bimc_pcnoc_icc_clks[] = {
> +	&clk_smd_rpm_bimc_clk,
> +	&clk_smd_rpm_bus_0_pcnoc_clk,
> +};
> +
> +static struct clk_smd_rpm *bimc_pcnoc_snoc_icc_clks[] = {
> +	&clk_smd_rpm_bimc_clk,
> +	&clk_smd_rpm_bus_0_pcnoc_clk,
> +	&clk_smd_rpm_bus_1_snoc_clk,
> +};
> +
> +static struct clk_smd_rpm *bimc_pcnoc_snoc_smmnoc_icc_clks[] = {
> +	&clk_smd_rpm_bimc_clk,
> +	&clk_smd_rpm_bus_0_pcnoc_clk,
> +	&clk_smd_rpm_bus_1_snoc_clk,
> +	&clk_smd_rpm_bus_2_sysmmnoc_clk,
> +};
> +
> +static struct clk_smd_rpm *bimc_pcnoc_snoc_cnoc_ocmem_icc_clks[] = {
> +	&clk_smd_rpm_bimc_clk,
> +	&clk_smd_rpm_bus_0_pcnoc_clk,
> +	&clk_smd_rpm_bus_1_snoc_clk,
> +	&clk_smd_rpm_bus_2_cnoc_clk,
> +	&clk_smd_rpm_ocmemgx_clk,
> +};
> +
> +static struct clk_smd_rpm *msm8996_icc_clks[] = {
> +	&clk_smd_rpm_bimc_clk,
> +	&clk_smd_rpm_branch_aggre1_noc_clk,
> +	&clk_smd_rpm_branch_aggre2_noc_clk,
> +	&clk_smd_rpm_bus_0_pcnoc_clk,
> +	&clk_smd_rpm_bus_1_snoc_clk,
> +	&clk_smd_rpm_bus_2_cnoc_clk,
> +	&clk_smd_rpm_mmssnoc_axi_rpm_clk,
> +};
> +
> +static struct clk_smd_rpm *msm8998_icc_clks[] = {
> +	&clk_smd_rpm_aggre1_noc_clk,
> +	&clk_smd_rpm_aggre2_noc_clk,
> +	&clk_smd_rpm_bimc_clk,
> +	&clk_smd_rpm_bus_1_snoc_clk,
> +	&clk_smd_rpm_bus_2_cnoc_clk,
> +	&clk_smd_rpm_mmssnoc_axi_rpm_clk,
> +};
> +
> +static struct clk_smd_rpm *sdm660_icc_clks[] = {
> +	&clk_smd_rpm_aggre2_noc_clk,
> +	&clk_smd_rpm_bimc_clk,
> +	&clk_smd_rpm_bus_1_snoc_clk,
> +	&clk_smd_rpm_bus_2_cnoc_clk,
> +	&clk_smd_rpm_mmssnoc_axi_rpm_clk,
> +};
> +
> +static struct clk_smd_rpm *sm_qnoc_icc_clks[] = {
> +	&clk_smd_rpm_bimc_clk,
> +	&clk_smd_rpm_bus_1_cnoc_clk,
> +	&clk_smd_rpm_mmnrt_clk,
> +	&clk_smd_rpm_mmrt_clk,
> +	&clk_smd_rpm_qup_clk,
> +	&clk_smd_rpm_bus_2_snoc_clk,
> +};
> +
>   static struct clk_smd_rpm *msm8909_clks[] = {
> -	[RPM_SMD_PCNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
> -	[RPM_SMD_PCNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_SNOC_CLK]		= &clk_smd_rpm_bus_1_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK]		= &clk_smd_rpm_bus_1_snoc_a_clk,
> -	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
>   	[RPM_SMD_QPIC_CLK]		= &clk_smd_rpm_qpic_clk,
>   	[RPM_SMD_QPIC_CLK_A]		= &clk_smd_rpm_qpic_a_clk,
>   	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
> @@ -530,15 +594,11 @@ static struct clk_smd_rpm *msm8909_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_msm8909 = {
>   	.clks = msm8909_clks,
>   	.num_clks = ARRAY_SIZE(msm8909_clks),
> +	.icc_clks = bimc_pcnoc_snoc_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *msm8916_clks[] = {
> -	[RPM_SMD_PCNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
> -	[RPM_SMD_PCNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_SNOC_CLK]		= &clk_smd_rpm_bus_1_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK]		= &clk_smd_rpm_bus_1_snoc_a_clk,
> -	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
>   	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK]		= &clk_smd_rpm_qdss_a_clk,
>   	[RPM_SMD_BB_CLK1]		= &clk_smd_rpm_bb_clk1,
> @@ -562,21 +622,15 @@ static struct clk_smd_rpm *msm8916_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
>   	.clks = msm8916_clks,
>   	.num_clks = ARRAY_SIZE(msm8916_clks),
> +	.icc_clks = bimc_pcnoc_snoc_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *msm8917_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_PNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
> -	[RPM_SMD_PNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_SNOC_CLK]		= &clk_smd_rpm_bus_1_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK]		= &clk_smd_rpm_bus_1_snoc_a_clk,
> -	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
>   	[RPM_SMD_BIMC_GPU_CLK]		= &clk_smd_rpm_bimc_gpu_clk,
>   	[RPM_SMD_BIMC_GPU_A_CLK]	= &clk_smd_rpm_bimc_gpu_a_clk,
> -	[RPM_SMD_SYSMMNOC_CLK]		= &clk_smd_rpm_bus_2_sysmmnoc_clk,
> -	[RPM_SMD_SYSMMNOC_A_CLK]	= &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
>   	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK]		= &clk_smd_rpm_qdss_a_clk,
>   	[RPM_SMD_BB_CLK1]		= &clk_smd_rpm_bb_clk1,
> @@ -596,19 +650,13 @@ static struct clk_smd_rpm *msm8917_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_msm8917 = {
>   	.clks = msm8917_clks,
>   	.num_clks = ARRAY_SIZE(msm8917_clks),
> +	.icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *msm8936_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_PCNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
> -	[RPM_SMD_PCNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_SNOC_CLK]		= &clk_smd_rpm_bus_1_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK]		= &clk_smd_rpm_bus_1_snoc_a_clk,
> -	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
> -	[RPM_SMD_SYSMMNOC_CLK]		= &clk_smd_rpm_bus_2_sysmmnoc_clk,
> -	[RPM_SMD_SYSMMNOC_A_CLK]	= &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
>   	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK]		= &clk_smd_rpm_qdss_a_clk,
>   	[RPM_SMD_BB_CLK1]		= &clk_smd_rpm_bb_clk1,
> @@ -632,25 +680,17 @@ static struct clk_smd_rpm *msm8936_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
>   		.clks = msm8936_clks,
>   		.num_clks = ARRAY_SIZE(msm8936_clks),
> +		.icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
> +		.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *msm8974_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_PNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
> -	[RPM_SMD_PNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_SNOC_CLK]		= &clk_smd_rpm_bus_1_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK]		= &clk_smd_rpm_bus_1_snoc_a_clk,
> -	[RPM_SMD_CNOC_CLK]		= &clk_smd_rpm_bus_2_cnoc_clk,
> -	[RPM_SMD_CNOC_A_CLK]		= &clk_smd_rpm_bus_2_cnoc_a_clk,
>   	[RPM_SMD_MMSSNOC_AHB_CLK]	= &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,
>   	[RPM_SMD_MMSSNOC_AHB_A_CLK]	= &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,
> -	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
>   	[RPM_SMD_GFX3D_CLK_SRC]		= &clk_smd_rpm_gfx3d_clk_src,
>   	[RPM_SMD_GFX3D_A_CLK_SRC]	= &clk_smd_rpm_gfx3d_a_clk_src,
> -	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
> -	[RPM_SMD_OCMEMGX_CLK]		= &clk_smd_rpm_ocmemgx_clk,
> -	[RPM_SMD_OCMEMGX_A_CLK]		= &clk_smd_rpm_ocmemgx_a_clk,
>   	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK]		= &clk_smd_rpm_qdss_a_clk,
>   	[RPM_SMD_CXO_D0]		= &clk_smd_rpm_cxo_d0,
> @@ -684,20 +724,14 @@ static struct clk_smd_rpm *msm8974_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
>   	.clks = msm8974_clks,
>   	.num_clks = ARRAY_SIZE(msm8974_clks),
> +	.icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
>   	.scaling_before_handover = true,
>   };
>   
>   static struct clk_smd_rpm *msm8976_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
> -	[RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
> -	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
> -	[RPM_SMD_SYSMMNOC_CLK]	= &clk_smd_rpm_bus_2_sysmmnoc_clk,
> -	[RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
>   	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
>   	[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
> @@ -718,24 +752,15 @@ static struct clk_smd_rpm *msm8976_clks[] = {
>   
>   static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
>   	.clks = msm8976_clks,
> -	.num_clks = ARRAY_SIZE(msm8976_clks),
> +	.icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *msm8992_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
> -	[RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk,
> -	[RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk,
> -	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
> -	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
> -	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
>   	[RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
>   	[RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
> -	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
>   	[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
>   	[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
>   	[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
> @@ -777,23 +802,15 @@ static struct clk_smd_rpm *msm8992_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
>   	.clks = msm8992_clks,
>   	.num_clks = ARRAY_SIZE(msm8992_clks),
> +	.icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *msm8994_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
> -	[RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk,
> -	[RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk,
> -	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
> -	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
> -	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
>   	[RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
>   	[RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
> -	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
>   	[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
>   	[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
>   	[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
> @@ -837,29 +854,17 @@ static struct clk_smd_rpm *msm8994_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
>   	.clks = msm8994_clks,
>   	.num_clks = ARRAY_SIZE(msm8994_clks),
> +	.icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *msm8996_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
> -	[RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
> -	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
> -	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
> -	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
> -	[RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk,
> -	[RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk,
>   	[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
>   	[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
>   	[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
>   	[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
> -	[RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_branch_aggre1_noc_clk,
> -	[RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_branch_aggre1_noc_a_clk,
> -	[RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_branch_aggre2_noc_clk,
> -	[RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_branch_aggre2_noc_a_clk,
>   	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
>   	[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
> @@ -891,6 +896,8 @@ static struct clk_smd_rpm *msm8996_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
>   	.clks = msm8996_clks,
>   	.num_clks = ARRAY_SIZE(msm8996_clks),
> +	.icc_clks = msm8996_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(msm8996_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *qcs404_clks[] = {
> @@ -919,19 +926,15 @@ static struct clk_smd_rpm *qcs404_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
>   	.clks = qcs404_clks,
>   	.num_clks = ARRAY_SIZE(qcs404_clks),
> +	.icc_clks = bimc_pcnoc_snoc_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *msm8998_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>   	[RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
>   	[RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
> -	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
> -	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
>   	[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
>   	[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
>   	[RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
> @@ -954,12 +957,6 @@ static struct clk_smd_rpm *msm8998_clks[] = {
>   	[RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin,
>   	[RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin,
>   	[RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin,
> -	[RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk,
> -	[RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk,
> -	[RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_aggre1_noc_clk,
> -	[RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_aggre1_noc_a_clk,
> -	[RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk,
> -	[RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk,
>   	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
>   	[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
> @@ -979,27 +976,19 @@ static struct clk_smd_rpm *msm8998_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
>   	.clks = msm8998_clks,
>   	.num_clks = ARRAY_SIZE(msm8998_clks),
> +	.icc_clks = msm8998_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(msm8998_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *sdm660_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
> -	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
> -	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
>   	[RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
>   	[RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
> -	[RPM_SMD_MMSSNOC_AXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk,
> -	[RPM_SMD_MMSSNOC_AXI_CLK_A] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk,
>   	[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
>   	[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
>   	[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
>   	[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
> -	[RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk,
> -	[RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk,
>   	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
>   	[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
> @@ -1025,15 +1014,13 @@ static struct clk_smd_rpm *sdm660_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
>   	.clks = sdm660_clks,
>   	.num_clks = ARRAY_SIZE(sdm660_clks),
> +	.icc_clks = sdm660_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(sdm660_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *mdm9607_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_PCNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
> -	[RPM_SMD_PCNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
>   	[RPM_SMD_QPIC_CLK]		= &clk_smd_rpm_qpic_clk,
>   	[RPM_SMD_QPIC_CLK_A]		= &clk_smd_rpm_qpic_a_clk,
>   	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
> @@ -1047,21 +1034,15 @@ static struct clk_smd_rpm *mdm9607_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = {
>   	.clks = mdm9607_clks,
>   	.num_clks = ARRAY_SIZE(mdm9607_clks),
> +	.icc_clks = bimc_pcnoc_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *msm8953_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC]		= &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_PCNOC_CLK]		= &clk_smd_rpm_bus_0_pcnoc_clk,
> -	[RPM_SMD_PCNOC_A_CLK]		= &clk_smd_rpm_bus_0_pcnoc_a_clk,
> -	[RPM_SMD_SNOC_CLK]		= &clk_smd_rpm_bus_1_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK]		= &clk_smd_rpm_bus_1_snoc_a_clk,
> -	[RPM_SMD_BIMC_CLK]		= &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK]		= &clk_smd_rpm_bimc_a_clk,
>   	[RPM_SMD_IPA_CLK]		= &clk_smd_rpm_ipa_clk,
>   	[RPM_SMD_IPA_A_CLK]		= &clk_smd_rpm_ipa_a_clk,
> -	[RPM_SMD_SYSMMNOC_CLK]		= &clk_smd_rpm_bus_2_sysmmnoc_clk,
> -	[RPM_SMD_SYSMMNOC_A_CLK]	= &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
>   	[RPM_SMD_QDSS_CLK]		= &clk_smd_rpm_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK]		= &clk_smd_rpm_qdss_a_clk,
>   	[RPM_SMD_BB_CLK1]		= &clk_smd_rpm_bb_clk1,
> @@ -1083,23 +1064,19 @@ static struct clk_smd_rpm *msm8953_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_msm8953 = {
>   	.clks = msm8953_clks,
>   	.num_clks = ARRAY_SIZE(msm8953_clks),
> +	.icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
>   };
>   
>   static struct clk_smd_rpm *sm6125_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
> -	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>   	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
>   	[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
>   	[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
>   	[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
>   	[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
> -	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
> -	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
>   	[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
>   	[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
>   	[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
> @@ -1110,12 +1087,6 @@ static struct clk_smd_rpm *sm6125_clks[] = {
>   	[RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
>   	[RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,
>   	[RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,
> -	[RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
> -	[RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
> -	[RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
> -	[RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
> -	[RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
> -	[RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
>   	[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
>   	[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
>   	[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
> @@ -1125,34 +1096,24 @@ static struct clk_smd_rpm *sm6125_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_sm6125 = {
>   	.clks = sm6125_clks,
>   	.num_clks = ARRAY_SIZE(sm6125_clks),
> +	.icc_clks = sm_qnoc_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
>   };
>   
>   /* SM6115 */
>   static struct clk_smd_rpm *sm6115_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
> -	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>   	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
>   	[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
>   	[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
>   	[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
>   	[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
> -	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
> -	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
>   	[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
>   	[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
>   	[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
>   	[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
> -	[RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
> -	[RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
> -	[RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
> -	[RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
> -	[RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
> -	[RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
>   	[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
>   	[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
>   	[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
> @@ -1166,27 +1127,17 @@ static struct clk_smd_rpm *sm6115_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
>   	.clks = sm6115_clks,
>   	.num_clks = ARRAY_SIZE(sm6115_clks),
> +	.icc_clks = sm_qnoc_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
>   };
>   
>   static struct clk_smd_rpm *sm6375_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
> -	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>   	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
> -	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
> -	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
>   	[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
>   	[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
> -	[RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
> -	[RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
> -	[RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
> -	[RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
> -	[RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
> -	[RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
>   	[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
>   	[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
>   	[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
> @@ -1203,31 +1154,21 @@ static struct clk_smd_rpm *sm6375_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_sm6375 = {
>   	.clks = sm6375_clks,
>   	.num_clks = ARRAY_SIZE(sm6375_clks),
> +	.icc_clks = sm_qnoc_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
>   };
>   
>   static struct clk_smd_rpm *qcm2290_clks[] = {
>   	[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>   	[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
> -	[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
> -	[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
> -	[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
> -	[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>   	[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
>   	[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
>   	[RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
>   	[RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
>   	[RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3,
>   	[RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a,
> -	[RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
> -	[RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
>   	[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
>   	[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
> -	[RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
> -	[RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
> -	[RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
> -	[RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
> -	[RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
> -	[RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
>   	[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
>   	[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
>   	[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
> @@ -1249,6 +1190,8 @@ static struct clk_smd_rpm *qcm2290_clks[] = {
>   static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {
>   	.clks = qcm2290_clks,
>   	.num_clks = ARRAY_SIZE(qcm2290_clks),
> +	.icc_clks = sm_qnoc_icc_clks,
> +	.num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
>   };
>   
>   static const struct of_device_id rpm_smd_clk_match_table[] = {
> @@ -1324,6 +1267,15 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
>   			goto err;
>   	}
>   
> +	for (i = 0; i < desc->num_icc_clks; i++) {
> +		if (!desc->icc_clks[i])
> +			continue;
> +
> +		ret = clk_smd_rpm_handoff(desc->icc_clks[i]);
> +		if (ret)
> +			goto err;
> +	}
> +
>   	if (!desc->scaling_before_handover) {
>   		ret = clk_smd_rpm_enable_scaling();
>   		if (ret)
> 

-- 
With best wishes
Dmitry

Re: [PATCH 07/20] interconnect: qcom: Fold smd-rpm.h into icc-rpm.h

[Dmitry Baryshkov]

On 01/06/2023 13:00, Konrad Dybcio wrote:
> 
> 
> On 1.06.2023 11:57, Dmitry Baryshkov wrote:
>> On 30/05/2023 13:20, Konrad Dybcio wrote:
>>> smd-rpm.h is not very useful as-is and both files are always included
>>> anyway.. Combine them.
>>
>> If we ever add interconnect driver for non-SMD RPM platforms (like MSM8960/APQ8064), we can just ignore the smd part.
> icc-rpm sends requests via smd so that doesn't sound unifiable

Ack. Should we rename it to icc-smd-rpm.c while doing the merge?

> 
> Konrad
>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
>>>    drivers/interconnect/qcom/icc-rpm.c |  1 -
>>>    drivers/interconnect/qcom/icc-rpm.h |  5 +++++
>>>    drivers/interconnect/qcom/msm8916.c |  1 -
>>>    drivers/interconnect/qcom/msm8939.c |  1 -
>>>    drivers/interconnect/qcom/msm8974.c |  2 +-
>>>    drivers/interconnect/qcom/msm8996.c |  1 -
>>>    drivers/interconnect/qcom/qcm2290.c |  1 -
>>>    drivers/interconnect/qcom/qcs404.c  |  1 -
>>>    drivers/interconnect/qcom/sdm660.c  |  1 -
>>>    drivers/interconnect/qcom/smd-rpm.c |  2 +-
>>>    drivers/interconnect/qcom/smd-rpm.h | 15 ---------------
>>>    11 files changed, 7 insertions(+), 24 deletions(-)
>>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>

-- 
With best wishes
Dmitry

Re: [PATCH 08/20] interconnect: qcom: smd-rpm: Add rpmcc handling skeleton code

[Konrad Dybcio]

On 1.06.2023 12:01, Dmitry Baryshkov wrote:
> On 30/05/2023 13:20, Konrad Dybcio wrote:
>> Introduce qcom_icc_rpm_set_bus_rate() in preparation for handling RPM
>> clock resources within the interconnect framework. This lets us greatly
>> simplify all of the code handling, as setting the rate comes down to:
>>
>> u32 rate_khz = max(clk.sleep_rate, clk.active_rate, clk_a.active_rate)
>> write_to_rpm(clock.description, rate_khz);
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>>   drivers/interconnect/qcom/icc-rpm.h | 15 +++++++++++++++
>>   drivers/interconnect/qcom/smd-rpm.c | 37 +++++++++++++++++++++++++++++++++++++
>>   2 files changed, 52 insertions(+)
>>
>> diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
>> index 9b4ea4e39b9f..aec192321411 100644
>> --- a/drivers/interconnect/qcom/icc-rpm.h
>> +++ b/drivers/interconnect/qcom/icc-rpm.h
>> @@ -22,6 +22,18 @@ enum qcom_icc_type {
>>       QCOM_ICC_QNOC,
>>   };
>>   +/**
>> + * struct rpm_clk_resource - RPM bus clock resource
>> + * @resource_type: RPM resource type of the clock resource
>> + * @clock_id: index of the clock resource of a specific resource type
>> + * @branch: whether the resource represents a branch clock
>> +*/
>> +struct rpm_clk_resource {
>> +    u32 resource_type;
>> +    u32 clock_id;
>> +    bool branch;
>> +};
>> +
>>   #define NUM_BUS_CLKS    2
>>     /**
>> @@ -47,6 +59,7 @@ struct qcom_icc_provider {
>>       int qos_offset;
>>       u64 bus_clk_rate[NUM_BUS_CLKS];
>>       struct clk_bulk_data bus_clks[NUM_BUS_CLKS];
>> +    const struct rpm_clk_resource *bus_clk_desc;
>>       struct clk_bulk_data *intf_clks;
>>       bool keep_alive;
>>       bool is_on;
>> @@ -104,6 +117,7 @@ struct qcom_icc_desc {
>>       struct qcom_icc_node * const *nodes;
>>       size_t num_nodes;
>>       const char * const *bus_clocks;
>> +    const struct rpm_clk_resource *bus_clk_desc;
>>       const char * const *intf_clocks;
>>       size_t num_intf_clocks;
>>       bool keep_alive;
>> @@ -125,5 +139,6 @@ int qnoc_remove(struct platform_device *pdev);
>>     bool qcom_icc_rpm_smd_available(void);
>>   int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val);
>> +int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, u32 active_rate, u32 sleep_rate);
>>     #endif
>> diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c
>> index b0183262ba66..6c51e346b326 100644
>> --- a/drivers/interconnect/qcom/smd-rpm.c
>> +++ b/drivers/interconnect/qcom/smd-rpm.c
>> @@ -16,6 +16,7 @@
>>   #include "icc-rpm.h"
>>     #define RPM_KEY_BW        0x00007762
>> +#define QCOM_RPM_SMD_KEY_RATE    0x007a484b
> 
> Nit: can we move all RPM keys to some common header?
They're quite scattered across subsystems so I think it'd be a separate
topic.. Also I think we could think about migrating to stringified raw
values like we have in RPMh - they keys are LE 4-char, non-NULL-terminated
strings (e.g. this one is 'KHz')

> 
>>     static struct qcom_smd_rpm *icc_smd_rpm;
>>   @@ -44,6 +45,38 @@ int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val)
>>   }
>>   EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_send);
>>   +int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, u32 active_rate, u32 sleep_rate)
>> +{
>> +    struct clk_smd_rpm_req req = {
>> +        .key = cpu_to_le32(QCOM_RPM_SMD_KEY_RATE),
>> +        .nbytes = cpu_to_le32(sizeof(u32)),
>> +    };
>> +    int ret;
>> +
>> +    /* Branch clocks are only on/off */
>> +    if (clk->branch) {
>> +        active_rate = !!active_rate;
>> +        sleep_rate = !!sleep_rate;
>> +    }
>> +
>> +    req.value = cpu_to_le32(active_rate);
>> +    ret = qcom_rpm_smd_write(icc_smd_rpm,
>> +                 QCOM_SMD_RPM_ACTIVE_STATE,
>> +                 clk->resource_type,
>> +                 clk->clock_id,
>> +                 &req, sizeof(req));
>> +    if (ret)
>> +        return ret;
>> +
>> +    req.value = cpu_to_le32(sleep_rate);
>> +    return qcom_rpm_smd_write(icc_smd_rpm,
>> +                  QCOM_SMD_RPM_SLEEP_STATE,
>> +                  clk->resource_type,
>> +                  clk->clock_id,
>> +                  &req, sizeof(req));
>> +}
>> +EXPORT_SYMBOL_GPL(qcom_icc_rpm_set_bus_rate);
>> +
>>   static int qcom_icc_rpm_smd_remove(struct platform_device *pdev)
>>   {
>>       icc_smd_rpm = NULL;
>> @@ -60,6 +93,10 @@ static int qcom_icc_rpm_smd_probe(struct platform_device *pdev)
>>           return -ENODEV;
>>       }
>>   +    /* We need the clock driver to kick things off first to avoid ugly races */
>> +    if (!qcom_smd_rpm_scaling_available())
>> +        return -EPROBE_DEFER;
> 
> 
> This should not be a part of this commit.
"eeh", it makes no functional difference, as if this patch is the HEAD,
we're still consuming the clocks via CCF, which guarantees this is always
true.. I can move it if you wish.

Konrad
> 
>> +
>>       return 0;
>>   }
>>  
> 

Re: [PATCH 10/20] interconnect: qcom: Define RPM bus clocks

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> Add the definitions for RPM bus clocks that will be used by many
> different platforms.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/Makefile         |  2 +-
>   drivers/interconnect/qcom/icc-rpm-clocks.c | 66 ++++++++++++++++++++++++++++++
>   drivers/interconnect/qcom/icc-rpm.h        | 13 ++++++
>   3 files changed, 80 insertions(+), 1 deletion(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 03/20] clk: qcom: smd-rpm: Separate out interconnect bus clocks

[Konrad Dybcio]

On 1.06.2023 12:03, Dmitry Baryshkov wrote:
> On 30/05/2023 13:20, Konrad Dybcio wrote:
>> The interconnect bus clocks are now handled within the ICC framework.
> 
> now = since commit ??
> Or should this commit be moved closer the end of the series?
Right, this should have been a bit later in the queue, possibly
right after "Control bus icc from icc".

Konrad
> 
>> They still however need to get a kickstart *before* we call
>> clk_smd_rpm_enable_scaling(), or RPM will assume that they should all
>> be running at 0 kHz and the system will inevitably die.
>>
>> Separate them out to ensure such a kickstart can still take place.
>>
>> As a happy accident, the file got smaller:
>>
>> Total: Before=41951, After=41555, chg -0.94%
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>>   drivers/clk/qcom/clk-smd-rpm.c | 278 +++++++++++++++++------------------------
>>   1 file changed, 115 insertions(+), 163 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
>> index 937cb1515968..b63f946e4520 100644
>> --- a/drivers/clk/qcom/clk-smd-rpm.c
>> +++ b/drivers/clk/qcom/clk-smd-rpm.c
>> @@ -167,6 +167,14 @@ struct clk_smd_rpm {
>>   struct rpm_smd_clk_desc {
>>       struct clk_smd_rpm **clks;
>>       size_t num_clks;
>> +
>> +    /*
>> +     * Interconnect clocks are managed by the icc framework, this driver
>> +     * only kickstarts them so that they don't get gated between
>> +     * clk_smd_rpm_enable_scaling() and interconnect driver initialization.
>> +     */
>> +    struct clk_smd_rpm **icc_clks;
>> +    size_t num_icc_clks;
>>       bool scaling_before_handover;
>>   };
>>   @@ -498,13 +506,69 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000);
>>   DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000);
>>   DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000);
>>   +static struct clk_smd_rpm *bimc_pcnoc_icc_clks[] = {
>> +    &clk_smd_rpm_bimc_clk,
>> +    &clk_smd_rpm_bus_0_pcnoc_clk,
>> +};
>> +
>> +static struct clk_smd_rpm *bimc_pcnoc_snoc_icc_clks[] = {
>> +    &clk_smd_rpm_bimc_clk,
>> +    &clk_smd_rpm_bus_0_pcnoc_clk,
>> +    &clk_smd_rpm_bus_1_snoc_clk,
>> +};
>> +
>> +static struct clk_smd_rpm *bimc_pcnoc_snoc_smmnoc_icc_clks[] = {
>> +    &clk_smd_rpm_bimc_clk,
>> +    &clk_smd_rpm_bus_0_pcnoc_clk,
>> +    &clk_smd_rpm_bus_1_snoc_clk,
>> +    &clk_smd_rpm_bus_2_sysmmnoc_clk,
>> +};
>> +
>> +static struct clk_smd_rpm *bimc_pcnoc_snoc_cnoc_ocmem_icc_clks[] = {
>> +    &clk_smd_rpm_bimc_clk,
>> +    &clk_smd_rpm_bus_0_pcnoc_clk,
>> +    &clk_smd_rpm_bus_1_snoc_clk,
>> +    &clk_smd_rpm_bus_2_cnoc_clk,
>> +    &clk_smd_rpm_ocmemgx_clk,
>> +};
>> +
>> +static struct clk_smd_rpm *msm8996_icc_clks[] = {
>> +    &clk_smd_rpm_bimc_clk,
>> +    &clk_smd_rpm_branch_aggre1_noc_clk,
>> +    &clk_smd_rpm_branch_aggre2_noc_clk,
>> +    &clk_smd_rpm_bus_0_pcnoc_clk,
>> +    &clk_smd_rpm_bus_1_snoc_clk,
>> +    &clk_smd_rpm_bus_2_cnoc_clk,
>> +    &clk_smd_rpm_mmssnoc_axi_rpm_clk,
>> +};
>> +
>> +static struct clk_smd_rpm *msm8998_icc_clks[] = {
>> +    &clk_smd_rpm_aggre1_noc_clk,
>> +    &clk_smd_rpm_aggre2_noc_clk,
>> +    &clk_smd_rpm_bimc_clk,
>> +    &clk_smd_rpm_bus_1_snoc_clk,
>> +    &clk_smd_rpm_bus_2_cnoc_clk,
>> +    &clk_smd_rpm_mmssnoc_axi_rpm_clk,
>> +};
>> +
>> +static struct clk_smd_rpm *sdm660_icc_clks[] = {
>> +    &clk_smd_rpm_aggre2_noc_clk,
>> +    &clk_smd_rpm_bimc_clk,
>> +    &clk_smd_rpm_bus_1_snoc_clk,
>> +    &clk_smd_rpm_bus_2_cnoc_clk,
>> +    &clk_smd_rpm_mmssnoc_axi_rpm_clk,
>> +};
>> +
>> +static struct clk_smd_rpm *sm_qnoc_icc_clks[] = {
>> +    &clk_smd_rpm_bimc_clk,
>> +    &clk_smd_rpm_bus_1_cnoc_clk,
>> +    &clk_smd_rpm_mmnrt_clk,
>> +    &clk_smd_rpm_mmrt_clk,
>> +    &clk_smd_rpm_qup_clk,
>> +    &clk_smd_rpm_bus_2_snoc_clk,
>> +};
>> +
>>   static struct clk_smd_rpm *msm8909_clks[] = {
>> -    [RPM_SMD_PCNOC_CLK]        = &clk_smd_rpm_bus_0_pcnoc_clk,
>> -    [RPM_SMD_PCNOC_A_CLK]        = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_SNOC_CLK]        = &clk_smd_rpm_bus_1_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK]        = &clk_smd_rpm_bus_1_snoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK]        = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK]        = &clk_smd_rpm_bimc_a_clk,
>>       [RPM_SMD_QPIC_CLK]        = &clk_smd_rpm_qpic_clk,
>>       [RPM_SMD_QPIC_CLK_A]        = &clk_smd_rpm_qpic_a_clk,
>>       [RPM_SMD_QDSS_CLK]        = &clk_smd_rpm_qdss_clk,
>> @@ -530,15 +594,11 @@ static struct clk_smd_rpm *msm8909_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_msm8909 = {
>>       .clks = msm8909_clks,
>>       .num_clks = ARRAY_SIZE(msm8909_clks),
>> +    .icc_clks = bimc_pcnoc_snoc_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
>>   };
>>     static struct clk_smd_rpm *msm8916_clks[] = {
>> -    [RPM_SMD_PCNOC_CLK]        = &clk_smd_rpm_bus_0_pcnoc_clk,
>> -    [RPM_SMD_PCNOC_A_CLK]        = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_SNOC_CLK]        = &clk_smd_rpm_bus_1_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK]        = &clk_smd_rpm_bus_1_snoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK]        = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK]        = &clk_smd_rpm_bimc_a_clk,
>>       [RPM_SMD_QDSS_CLK]        = &clk_smd_rpm_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK]        = &clk_smd_rpm_qdss_a_clk,
>>       [RPM_SMD_BB_CLK1]        = &clk_smd_rpm_bb_clk1,
>> @@ -562,21 +622,15 @@ static struct clk_smd_rpm *msm8916_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
>>       .clks = msm8916_clks,
>>       .num_clks = ARRAY_SIZE(msm8916_clks),
>> +    .icc_clks = bimc_pcnoc_snoc_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
>>   };
>>     static struct clk_smd_rpm *msm8917_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC]        = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC]        = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_PNOC_CLK]        = &clk_smd_rpm_bus_0_pcnoc_clk,
>> -    [RPM_SMD_PNOC_A_CLK]        = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_SNOC_CLK]        = &clk_smd_rpm_bus_1_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK]        = &clk_smd_rpm_bus_1_snoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK]        = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK]        = &clk_smd_rpm_bimc_a_clk,
>>       [RPM_SMD_BIMC_GPU_CLK]        = &clk_smd_rpm_bimc_gpu_clk,
>>       [RPM_SMD_BIMC_GPU_A_CLK]    = &clk_smd_rpm_bimc_gpu_a_clk,
>> -    [RPM_SMD_SYSMMNOC_CLK]        = &clk_smd_rpm_bus_2_sysmmnoc_clk,
>> -    [RPM_SMD_SYSMMNOC_A_CLK]    = &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
>>       [RPM_SMD_QDSS_CLK]        = &clk_smd_rpm_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK]        = &clk_smd_rpm_qdss_a_clk,
>>       [RPM_SMD_BB_CLK1]        = &clk_smd_rpm_bb_clk1,
>> @@ -596,19 +650,13 @@ static struct clk_smd_rpm *msm8917_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_msm8917 = {
>>       .clks = msm8917_clks,
>>       .num_clks = ARRAY_SIZE(msm8917_clks),
>> +    .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
>>   };
>>     static struct clk_smd_rpm *msm8936_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC]        = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC]        = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_PCNOC_CLK]        = &clk_smd_rpm_bus_0_pcnoc_clk,
>> -    [RPM_SMD_PCNOC_A_CLK]        = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_SNOC_CLK]        = &clk_smd_rpm_bus_1_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK]        = &clk_smd_rpm_bus_1_snoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK]        = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK]        = &clk_smd_rpm_bimc_a_clk,
>> -    [RPM_SMD_SYSMMNOC_CLK]        = &clk_smd_rpm_bus_2_sysmmnoc_clk,
>> -    [RPM_SMD_SYSMMNOC_A_CLK]    = &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
>>       [RPM_SMD_QDSS_CLK]        = &clk_smd_rpm_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK]        = &clk_smd_rpm_qdss_a_clk,
>>       [RPM_SMD_BB_CLK1]        = &clk_smd_rpm_bb_clk1,
>> @@ -632,25 +680,17 @@ static struct clk_smd_rpm *msm8936_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
>>           .clks = msm8936_clks,
>>           .num_clks = ARRAY_SIZE(msm8936_clks),
>> +        .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
>> +        .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
>>   };
>>     static struct clk_smd_rpm *msm8974_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC]        = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC]        = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_PNOC_CLK]        = &clk_smd_rpm_bus_0_pcnoc_clk,
>> -    [RPM_SMD_PNOC_A_CLK]        = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_SNOC_CLK]        = &clk_smd_rpm_bus_1_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK]        = &clk_smd_rpm_bus_1_snoc_a_clk,
>> -    [RPM_SMD_CNOC_CLK]        = &clk_smd_rpm_bus_2_cnoc_clk,
>> -    [RPM_SMD_CNOC_A_CLK]        = &clk_smd_rpm_bus_2_cnoc_a_clk,
>>       [RPM_SMD_MMSSNOC_AHB_CLK]    = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,
>>       [RPM_SMD_MMSSNOC_AHB_A_CLK]    = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,
>> -    [RPM_SMD_BIMC_CLK]        = &clk_smd_rpm_bimc_clk,
>>       [RPM_SMD_GFX3D_CLK_SRC]        = &clk_smd_rpm_gfx3d_clk_src,
>>       [RPM_SMD_GFX3D_A_CLK_SRC]    = &clk_smd_rpm_gfx3d_a_clk_src,
>> -    [RPM_SMD_BIMC_A_CLK]        = &clk_smd_rpm_bimc_a_clk,
>> -    [RPM_SMD_OCMEMGX_CLK]        = &clk_smd_rpm_ocmemgx_clk,
>> -    [RPM_SMD_OCMEMGX_A_CLK]        = &clk_smd_rpm_ocmemgx_a_clk,
>>       [RPM_SMD_QDSS_CLK]        = &clk_smd_rpm_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK]        = &clk_smd_rpm_qdss_a_clk,
>>       [RPM_SMD_CXO_D0]        = &clk_smd_rpm_cxo_d0,
>> @@ -684,20 +724,14 @@ static struct clk_smd_rpm *msm8974_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
>>       .clks = msm8974_clks,
>>       .num_clks = ARRAY_SIZE(msm8974_clks),
>> +    .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
>>       .scaling_before_handover = true,
>>   };
>>     static struct clk_smd_rpm *msm8976_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
>> -    [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>> -    [RPM_SMD_SYSMMNOC_CLK]    = &clk_smd_rpm_bus_2_sysmmnoc_clk,
>> -    [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
>>       [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
>>       [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
>> @@ -718,24 +752,15 @@ static struct clk_smd_rpm *msm8976_clks[] = {
>>     static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
>>       .clks = msm8976_clks,
>> -    .num_clks = ARRAY_SIZE(msm8976_clks),
>> +    .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
>>   };
>>     static struct clk_smd_rpm *msm8992_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
>> -    [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk,
>> -    [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk,
>> -    [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>> -    [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
>> -    [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
>>       [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
>>       [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
>> -    [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
>>       [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
>>       [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
>>       [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
>> @@ -777,23 +802,15 @@ static struct clk_smd_rpm *msm8992_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
>>       .clks = msm8992_clks,
>>       .num_clks = ARRAY_SIZE(msm8992_clks),
>> +    .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
>>   };
>>     static struct clk_smd_rpm *msm8994_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
>> -    [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk,
>> -    [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk,
>> -    [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>> -    [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
>> -    [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
>>       [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
>>       [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
>> -    [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
>>       [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
>>       [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
>>       [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
>> @@ -837,29 +854,17 @@ static struct clk_smd_rpm *msm8994_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
>>       .clks = msm8994_clks,
>>       .num_clks = ARRAY_SIZE(msm8994_clks),
>> +    .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
>>   };
>>     static struct clk_smd_rpm *msm8996_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
>> -    [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
>> -    [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
>> -    [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>> -    [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk,
>> -    [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk,
>>       [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
>>       [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
>>       [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
>>       [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
>> -    [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_branch_aggre1_noc_clk,
>> -    [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_branch_aggre1_noc_a_clk,
>> -    [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_branch_aggre2_noc_clk,
>> -    [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_branch_aggre2_noc_a_clk,
>>       [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
>>       [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
>> @@ -891,6 +896,8 @@ static struct clk_smd_rpm *msm8996_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
>>       .clks = msm8996_clks,
>>       .num_clks = ARRAY_SIZE(msm8996_clks),
>> +    .icc_clks = msm8996_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(msm8996_icc_clks),
>>   };
>>     static struct clk_smd_rpm *qcs404_clks[] = {
>> @@ -919,19 +926,15 @@ static struct clk_smd_rpm *qcs404_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
>>       .clks = qcs404_clks,
>>       .num_clks = ARRAY_SIZE(qcs404_clks),
>> +    .icc_clks = bimc_pcnoc_snoc_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
>>   };
>>     static struct clk_smd_rpm *msm8998_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>>       [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
>>       [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
>> -    [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
>> -    [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
>>       [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
>>       [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
>>       [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
>> @@ -954,12 +957,6 @@ static struct clk_smd_rpm *msm8998_clks[] = {
>>       [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin,
>>       [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin,
>>       [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin,
>> -    [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk,
>> -    [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk,
>> -    [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_aggre1_noc_clk,
>> -    [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_aggre1_noc_a_clk,
>> -    [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk,
>> -    [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk,
>>       [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
>>       [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
>> @@ -979,27 +976,19 @@ static struct clk_smd_rpm *msm8998_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
>>       .clks = msm8998_clks,
>>       .num_clks = ARRAY_SIZE(msm8998_clks),
>> +    .icc_clks = msm8998_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(msm8998_icc_clks),
>>   };
>>     static struct clk_smd_rpm *sdm660_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
>> -    [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
>> -    [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
>>       [RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
>>       [RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>> -    [RPM_SMD_MMSSNOC_AXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk,
>> -    [RPM_SMD_MMSSNOC_AXI_CLK_A] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk,
>>       [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
>>       [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
>>       [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
>>       [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
>> -    [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk,
>> -    [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk,
>>       [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
>>       [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
>> @@ -1025,15 +1014,13 @@ static struct clk_smd_rpm *sdm660_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
>>       .clks = sdm660_clks,
>>       .num_clks = ARRAY_SIZE(sdm660_clks),
>> +    .icc_clks = sdm660_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(sdm660_icc_clks),
>>   };
>>     static struct clk_smd_rpm *mdm9607_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC]        = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC]        = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_PCNOC_CLK]        = &clk_smd_rpm_bus_0_pcnoc_clk,
>> -    [RPM_SMD_PCNOC_A_CLK]        = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK]        = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK]        = &clk_smd_rpm_bimc_a_clk,
>>       [RPM_SMD_QPIC_CLK]        = &clk_smd_rpm_qpic_clk,
>>       [RPM_SMD_QPIC_CLK_A]        = &clk_smd_rpm_qpic_a_clk,
>>       [RPM_SMD_QDSS_CLK]        = &clk_smd_rpm_qdss_clk,
>> @@ -1047,21 +1034,15 @@ static struct clk_smd_rpm *mdm9607_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = {
>>       .clks = mdm9607_clks,
>>       .num_clks = ARRAY_SIZE(mdm9607_clks),
>> +    .icc_clks = bimc_pcnoc_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_icc_clks),
>>   };
>>     static struct clk_smd_rpm *msm8953_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC]        = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC]        = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_PCNOC_CLK]        = &clk_smd_rpm_bus_0_pcnoc_clk,
>> -    [RPM_SMD_PCNOC_A_CLK]        = &clk_smd_rpm_bus_0_pcnoc_a_clk,
>> -    [RPM_SMD_SNOC_CLK]        = &clk_smd_rpm_bus_1_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK]        = &clk_smd_rpm_bus_1_snoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK]        = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK]        = &clk_smd_rpm_bimc_a_clk,
>>       [RPM_SMD_IPA_CLK]        = &clk_smd_rpm_ipa_clk,
>>       [RPM_SMD_IPA_A_CLK]        = &clk_smd_rpm_ipa_a_clk,
>> -    [RPM_SMD_SYSMMNOC_CLK]        = &clk_smd_rpm_bus_2_sysmmnoc_clk,
>> -    [RPM_SMD_SYSMMNOC_A_CLK]    = &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
>>       [RPM_SMD_QDSS_CLK]        = &clk_smd_rpm_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK]        = &clk_smd_rpm_qdss_a_clk,
>>       [RPM_SMD_BB_CLK1]        = &clk_smd_rpm_bb_clk1,
>> @@ -1083,23 +1064,19 @@ static struct clk_smd_rpm *msm8953_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_msm8953 = {
>>       .clks = msm8953_clks,
>>       .num_clks = ARRAY_SIZE(msm8953_clks),
>> +    .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
>>   };
>>     static struct clk_smd_rpm *sm6125_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>>       [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
>>       [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
>>       [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
>>       [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
>>       [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
>> -    [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
>> -    [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
>>       [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
>>       [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
>>       [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
>> @@ -1110,12 +1087,6 @@ static struct clk_smd_rpm *sm6125_clks[] = {
>>       [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
>>       [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,
>>       [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,
>> -    [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
>> -    [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
>> -    [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
>> -    [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
>> -    [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
>> -    [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
>>       [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
>>       [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
>>       [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
>> @@ -1125,34 +1096,24 @@ static struct clk_smd_rpm *sm6125_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_sm6125 = {
>>       .clks = sm6125_clks,
>>       .num_clks = ARRAY_SIZE(sm6125_clks),
>> +    .icc_clks = sm_qnoc_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
>>   };
>>     /* SM6115 */
>>   static struct clk_smd_rpm *sm6115_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>>       [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
>>       [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
>>       [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
>>       [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
>>       [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
>> -    [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
>> -    [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
>>       [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
>>       [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
>>       [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
>>       [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
>> -    [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
>> -    [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
>> -    [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
>> -    [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
>> -    [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
>> -    [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
>>       [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
>>       [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
>>       [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
>> @@ -1166,27 +1127,17 @@ static struct clk_smd_rpm *sm6115_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
>>       .clks = sm6115_clks,
>>       .num_clks = ARRAY_SIZE(sm6115_clks),
>> +    .icc_clks = sm_qnoc_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
>>   };
>>     static struct clk_smd_rpm *sm6375_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>>       [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
>> -    [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
>> -    [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
>>       [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
>>       [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
>> -    [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
>> -    [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
>> -    [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
>> -    [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
>> -    [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
>> -    [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
>>       [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
>>       [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
>>       [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
>> @@ -1203,31 +1154,21 @@ static struct clk_smd_rpm *sm6375_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_sm6375 = {
>>       .clks = sm6375_clks,
>>       .num_clks = ARRAY_SIZE(sm6375_clks),
>> +    .icc_clks = sm_qnoc_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
>>   };
>>     static struct clk_smd_rpm *qcm2290_clks[] = {
>>       [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
>>       [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
>> -    [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
>> -    [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
>> -    [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
>> -    [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
>>       [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
>>       [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
>>       [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
>>       [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
>>       [RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3,
>>       [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a,
>> -    [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
>> -    [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
>>       [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
>>       [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
>> -    [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
>> -    [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
>> -    [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
>> -    [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
>> -    [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
>> -    [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
>>       [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
>>       [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
>>       [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
>> @@ -1249,6 +1190,8 @@ static struct clk_smd_rpm *qcm2290_clks[] = {
>>   static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {
>>       .clks = qcm2290_clks,
>>       .num_clks = ARRAY_SIZE(qcm2290_clks),
>> +    .icc_clks = sm_qnoc_icc_clks,
>> +    .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
>>   };
>>     static const struct of_device_id rpm_smd_clk_match_table[] = {
>> @@ -1324,6 +1267,15 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
>>               goto err;
>>       }
>>   +    for (i = 0; i < desc->num_icc_clks; i++) {
>> +        if (!desc->icc_clks[i])
>> +            continue;
>> +
>> +        ret = clk_smd_rpm_handoff(desc->icc_clks[i]);
>> +        if (ret)
>> +            goto err;
>> +    }
>> +
>>       if (!desc->scaling_before_handover) {
>>           ret = clk_smd_rpm_enable_scaling();
>>           if (ret)
>>
> 

Re: [PATCH 07/20] interconnect: qcom: Fold smd-rpm.h into icc-rpm.h

[Konrad Dybcio]

On 1.06.2023 12:04, Dmitry Baryshkov wrote:
> On 01/06/2023 13:00, Konrad Dybcio wrote:
>>
>>
>> On 1.06.2023 11:57, Dmitry Baryshkov wrote:
>>> On 30/05/2023 13:20, Konrad Dybcio wrote:
>>>> smd-rpm.h is not very useful as-is and both files are always included
>>>> anyway.. Combine them.
>>>
>>> If we ever add interconnect driver for non-SMD RPM platforms (like MSM8960/APQ8064), we can just ignore the smd part.
>> icc-rpm sends requests via smd so that doesn't sound unifiable
> 
> Ack. Should we rename it to icc-smd-rpm.c while doing the merge?
I'd stay it's fine if it stays as-is for now, until (if) somebody
tackles "old" RPM.

Konrad
> 
>>
>> Konrad
>>>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>> ---
>>>>    drivers/interconnect/qcom/icc-rpm.c |  1 -
>>>>    drivers/interconnect/qcom/icc-rpm.h |  5 +++++
>>>>    drivers/interconnect/qcom/msm8916.c |  1 -
>>>>    drivers/interconnect/qcom/msm8939.c |  1 -
>>>>    drivers/interconnect/qcom/msm8974.c |  2 +-
>>>>    drivers/interconnect/qcom/msm8996.c |  1 -
>>>>    drivers/interconnect/qcom/qcm2290.c |  1 -
>>>>    drivers/interconnect/qcom/qcs404.c  |  1 -
>>>>    drivers/interconnect/qcom/sdm660.c  |  1 -
>>>>    drivers/interconnect/qcom/smd-rpm.c |  2 +-
>>>>    drivers/interconnect/qcom/smd-rpm.h | 15 ---------------
>>>>    11 files changed, 7 insertions(+), 24 deletions(-)
>>>
>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>
> 

Re: [PATCH 12/20] interconnect: qcom: msm8996: Hook up RPM bus clk definitions

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> Assign the necessary definitions to migrate to the new bus clock
> handling mechanism.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/msm8996.c | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c
> index 1f7e88a37acd..a596f4035d2e 100644
> --- a/drivers/interconnect/qcom/msm8996.c
> +++ b/drivers/interconnect/qcom/msm8996.c
> @@ -1840,6 +1840,7 @@ static const struct qcom_icc_desc msm8996_a1noc = {
>   	.type = QCOM_ICC_NOC,
>   	.nodes = a1noc_nodes,
>   	.num_nodes = ARRAY_SIZE(a1noc_nodes),
> +	.bus_clk_desc = &aggre1_branch_clk,
>   	.regmap_cfg = &msm8996_a1noc_regmap_config
>   };
>   
> @@ -1861,6 +1862,7 @@ static const struct qcom_icc_desc msm8996_a2noc = {
>   	.type = QCOM_ICC_NOC,
>   	.nodes = a2noc_nodes,
>   	.num_nodes = ARRAY_SIZE(a2noc_nodes),
> +	.bus_clk_desc = &aggre2_branch_clk,
>   	.intf_clocks = a2noc_intf_clocks,
>   	.num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
>   	.regmap_cfg = &msm8996_a2noc_regmap_config
> @@ -1889,6 +1891,7 @@ static const struct qcom_icc_desc msm8996_bimc = {
>   	.type = QCOM_ICC_BIMC,
>   	.nodes = bimc_nodes,
>   	.num_nodes = ARRAY_SIZE(bimc_nodes),
> +	.bus_clk_desc = &bimc_clk,
>   	.regmap_cfg = &msm8996_bimc_regmap_config
>   };
>   
> @@ -1947,6 +1950,7 @@ static const struct qcom_icc_desc msm8996_cnoc = {
>   	.type = QCOM_ICC_NOC,
>   	.nodes = cnoc_nodes,
>   	.num_nodes = ARRAY_SIZE(cnoc_nodes),
> +	.bus_clk_desc = &bus_2_clk,
>   	.regmap_cfg = &msm8996_cnoc_regmap_config
>   };
>   
> @@ -2000,6 +2004,7 @@ static const struct qcom_icc_desc msm8996_mnoc = {
>   	.type = QCOM_ICC_NOC,
>   	.nodes = mnoc_nodes,
>   	.num_nodes = ARRAY_SIZE(mnoc_nodes),
> +	.bus_clk_desc = &mmaxi_0_clk,

What about an ahb_clk_src here?

>   	.intf_clocks = mm_intf_clocks,
>   	.num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
>   	.regmap_cfg = &msm8996_mnoc_regmap_config
> @@ -2038,6 +2043,7 @@ static const struct qcom_icc_desc msm8996_pnoc = {
>   	.type = QCOM_ICC_NOC,
>   	.nodes = pnoc_nodes,
>   	.num_nodes = ARRAY_SIZE(pnoc_nodes),
> +	.bus_clk_desc = &bus_0_clk,
>   	.regmap_cfg = &msm8996_pnoc_regmap_config
>   };
>   
> @@ -2082,6 +2088,7 @@ static const struct qcom_icc_desc msm8996_snoc = {
>   	.type = QCOM_ICC_NOC,
>   	.nodes = snoc_nodes,
>   	.num_nodes = ARRAY_SIZE(snoc_nodes),
> +	.bus_clk_desc = &bus_1_clk,
>   	.regmap_cfg = &msm8996_snoc_regmap_config
>   };
>   
> 

-- 
With best wishes
Dmitry

Re: [PATCH 11/20] interconnect: qcom: sdm660: Hook up RPM bus clk definitions

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> Assign the necessary definitions to migrate to the new bus clock
> handling mechanism.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/sdm660.c | 5 +++++
>   1 file changed, 5 insertions(+)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 13/20] interconnect: qcom: qcs404: Hook up RPM bus clk definitions

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> Assign the necessary definitions to migrate to the new bus clock
> handling mechanism.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/qcs404.c | 3 +++
>   1 file changed, 3 insertions(+)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 14/20] interconnect: qcom: msm8939: Hook up RPM bus clk definitions

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> Assign the necessary definitions to migrate to the new bus clock
> handling mechanism.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/msm8939.c | 4 ++++
>   1 file changed, 4 insertions(+)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 12/20] interconnect: qcom: msm8996: Hook up RPM bus clk definitions

[Konrad Dybcio]

On 1.06.2023 12:08, Dmitry Baryshkov wrote:
> On 30/05/2023 13:20, Konrad Dybcio wrote:
>> Assign the necessary definitions to migrate to the new bus clock
>> handling mechanism.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>>   drivers/interconnect/qcom/msm8996.c | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c
>> index 1f7e88a37acd..a596f4035d2e 100644
>> --- a/drivers/interconnect/qcom/msm8996.c
>> +++ b/drivers/interconnect/qcom/msm8996.c
>> @@ -1840,6 +1840,7 @@ static const struct qcom_icc_desc msm8996_a1noc = {
>>       .type = QCOM_ICC_NOC,
>>       .nodes = a1noc_nodes,
>>       .num_nodes = ARRAY_SIZE(a1noc_nodes),
>> +    .bus_clk_desc = &aggre1_branch_clk,
>>       .regmap_cfg = &msm8996_a1noc_regmap_config
>>   };
>>   @@ -1861,6 +1862,7 @@ static const struct qcom_icc_desc msm8996_a2noc = {
>>       .type = QCOM_ICC_NOC,
>>       .nodes = a2noc_nodes,
>>       .num_nodes = ARRAY_SIZE(a2noc_nodes),
>> +    .bus_clk_desc = &aggre2_branch_clk,
>>       .intf_clocks = a2noc_intf_clocks,
>>       .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
>>       .regmap_cfg = &msm8996_a2noc_regmap_config
>> @@ -1889,6 +1891,7 @@ static const struct qcom_icc_desc msm8996_bimc = {
>>       .type = QCOM_ICC_BIMC,
>>       .nodes = bimc_nodes,
>>       .num_nodes = ARRAY_SIZE(bimc_nodes),
>> +    .bus_clk_desc = &bimc_clk,
>>       .regmap_cfg = &msm8996_bimc_regmap_config
>>   };
>>   @@ -1947,6 +1950,7 @@ static const struct qcom_icc_desc msm8996_cnoc = {
>>       .type = QCOM_ICC_NOC,
>>       .nodes = cnoc_nodes,
>>       .num_nodes = ARRAY_SIZE(cnoc_nodes),
>> +    .bus_clk_desc = &bus_2_clk,
>>       .regmap_cfg = &msm8996_cnoc_regmap_config
>>   };
>>   @@ -2000,6 +2004,7 @@ static const struct qcom_icc_desc msm8996_mnoc = {
>>       .type = QCOM_ICC_NOC,
>>       .nodes = mnoc_nodes,
>>       .num_nodes = ARRAY_SIZE(mnoc_nodes),
>> +    .bus_clk_desc = &mmaxi_0_clk,
> 
> What about an ahb_clk_src here?
This should be remodeled to MNoC (MMAXI clk) + MNoC_AHB (ahb_clk_src).

I can fix this after this series.

Konrad
> 
>>       .intf_clocks = mm_intf_clocks,
>>       .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
>>       .regmap_cfg = &msm8996_mnoc_regmap_config
>> @@ -2038,6 +2043,7 @@ static const struct qcom_icc_desc msm8996_pnoc = {
>>       .type = QCOM_ICC_NOC,
>>       .nodes = pnoc_nodes,
>>       .num_nodes = ARRAY_SIZE(pnoc_nodes),
>> +    .bus_clk_desc = &bus_0_clk,
>>       .regmap_cfg = &msm8996_pnoc_regmap_config
>>   };
>>   @@ -2082,6 +2088,7 @@ static const struct qcom_icc_desc msm8996_snoc = {
>>       .type = QCOM_ICC_NOC,
>>       .nodes = snoc_nodes,
>>       .num_nodes = ARRAY_SIZE(snoc_nodes),
>> +    .bus_clk_desc = &bus_1_clk,
>>       .regmap_cfg = &msm8996_snoc_regmap_config
>>   };
>>  
> 

Re: [PATCH 15/20] interconnect: qcom: msm8916: Hook up RPM bus clk definitions

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> Assign the necessary definitions to migrate to the new bus clock
> handling mechanism.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/msm8916.c | 3 +++
>   1 file changed, 3 insertions(+)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 12/20] interconnect: qcom: msm8996: Hook up RPM bus clk definitions

[Dmitry Baryshkov]

On 01/06/2023 13:10, Konrad Dybcio wrote:
> 
> 
> On 1.06.2023 12:08, Dmitry Baryshkov wrote:
>> On 30/05/2023 13:20, Konrad Dybcio wrote:
>>> Assign the necessary definitions to migrate to the new bus clock
>>> handling mechanism.
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
>>>    drivers/interconnect/qcom/msm8996.c | 7 +++++++
>>>    1 file changed, 7 insertions(+)
>>>
>>> diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c
>>> index 1f7e88a37acd..a596f4035d2e 100644
>>> --- a/drivers/interconnect/qcom/msm8996.c
>>> +++ b/drivers/interconnect/qcom/msm8996.c
>>> @@ -1840,6 +1840,7 @@ static const struct qcom_icc_desc msm8996_a1noc = {
>>>        .type = QCOM_ICC_NOC,
>>>        .nodes = a1noc_nodes,
>>>        .num_nodes = ARRAY_SIZE(a1noc_nodes),
>>> +    .bus_clk_desc = &aggre1_branch_clk,
>>>        .regmap_cfg = &msm8996_a1noc_regmap_config
>>>    };
>>>    @@ -1861,6 +1862,7 @@ static const struct qcom_icc_desc msm8996_a2noc = {
>>>        .type = QCOM_ICC_NOC,
>>>        .nodes = a2noc_nodes,
>>>        .num_nodes = ARRAY_SIZE(a2noc_nodes),
>>> +    .bus_clk_desc = &aggre2_branch_clk,
>>>        .intf_clocks = a2noc_intf_clocks,
>>>        .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
>>>        .regmap_cfg = &msm8996_a2noc_regmap_config
>>> @@ -1889,6 +1891,7 @@ static const struct qcom_icc_desc msm8996_bimc = {
>>>        .type = QCOM_ICC_BIMC,
>>>        .nodes = bimc_nodes,
>>>        .num_nodes = ARRAY_SIZE(bimc_nodes),
>>> +    .bus_clk_desc = &bimc_clk,
>>>        .regmap_cfg = &msm8996_bimc_regmap_config
>>>    };
>>>    @@ -1947,6 +1950,7 @@ static const struct qcom_icc_desc msm8996_cnoc = {
>>>        .type = QCOM_ICC_NOC,
>>>        .nodes = cnoc_nodes,
>>>        .num_nodes = ARRAY_SIZE(cnoc_nodes),
>>> +    .bus_clk_desc = &bus_2_clk,
>>>        .regmap_cfg = &msm8996_cnoc_regmap_config
>>>    };
>>>    @@ -2000,6 +2004,7 @@ static const struct qcom_icc_desc msm8996_mnoc = {
>>>        .type = QCOM_ICC_NOC,
>>>        .nodes = mnoc_nodes,
>>>        .num_nodes = ARRAY_SIZE(mnoc_nodes),
>>> +    .bus_clk_desc = &mmaxi_0_clk,
>>
>> What about an ahb_clk_src here?
> This should be remodeled to MNoC (MMAXI clk) + MNoC_AHB (ahb_clk_src).
> 
> I can fix this after this series.

As long as it doesn't result in a regression.

> Konrad
>>
>>>        .intf_clocks = mm_intf_clocks,
>>>        .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
>>>        .regmap_cfg = &msm8996_mnoc_regmap_config
>>> @@ -2038,6 +2043,7 @@ static const struct qcom_icc_desc msm8996_pnoc = {
>>>        .type = QCOM_ICC_NOC,
>>>        .nodes = pnoc_nodes,
>>>        .num_nodes = ARRAY_SIZE(pnoc_nodes),
>>> +    .bus_clk_desc = &bus_0_clk,
>>>        .regmap_cfg = &msm8996_pnoc_regmap_config
>>>    };
>>>    @@ -2082,6 +2088,7 @@ static const struct qcom_icc_desc msm8996_snoc = {
>>>        .type = QCOM_ICC_NOC,
>>>        .nodes = snoc_nodes,
>>>        .num_nodes = ARRAY_SIZE(snoc_nodes),
>>> +    .bus_clk_desc = &bus_1_clk,
>>>        .regmap_cfg = &msm8996_snoc_regmap_config
>>>    };
>>>   
>>

-- 
With best wishes
Dmitry

Re: [PATCH 16/20] interconnect: qcom: qcm2290: Hook up RPM bus clk definitions

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> Assign the necessary definitions to migrate to the new bus clock
> handling mechanism.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/qcm2290.c | 6 ++++++
>   1 file changed, 6 insertions(+)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 18/20] interconnect: qcom: icc-rpm: Fix bucket number

[Dmitry Baryshkov]

On 30/05/2023 13:20, Konrad Dybcio wrote:
> SMD RPM only provides two buckets, one each for the active-only and
> active-sleep RPM contexts. Use the correct constant to allocate and
> operate on them.
> 
> Fixes: dcbce7b0a79c ("interconnect: qcom: icc-rpm: Support multiple buckets")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/icc-rpm.c | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 12/20] interconnect: qcom: msm8996: Hook up RPM bus clk definitions

[Konrad Dybcio]

On 1.06.2023 12:11, Dmitry Baryshkov wrote:
> On 01/06/2023 13:10, Konrad Dybcio wrote:
>>
>>
>> On 1.06.2023 12:08, Dmitry Baryshkov wrote:
>>> On 30/05/2023 13:20, Konrad Dybcio wrote:
>>>> Assign the necessary definitions to migrate to the new bus clock
>>>> handling mechanism.
>>>>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>> ---
>>>>    drivers/interconnect/qcom/msm8996.c | 7 +++++++
>>>>    1 file changed, 7 insertions(+)
>>>>
>>>> diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c
>>>> index 1f7e88a37acd..a596f4035d2e 100644
>>>> --- a/drivers/interconnect/qcom/msm8996.c
>>>> +++ b/drivers/interconnect/qcom/msm8996.c
>>>> @@ -1840,6 +1840,7 @@ static const struct qcom_icc_desc msm8996_a1noc = {
>>>>        .type = QCOM_ICC_NOC,
>>>>        .nodes = a1noc_nodes,
>>>>        .num_nodes = ARRAY_SIZE(a1noc_nodes),
>>>> +    .bus_clk_desc = &aggre1_branch_clk,
>>>>        .regmap_cfg = &msm8996_a1noc_regmap_config
>>>>    };
>>>>    @@ -1861,6 +1862,7 @@ static const struct qcom_icc_desc msm8996_a2noc = {
>>>>        .type = QCOM_ICC_NOC,
>>>>        .nodes = a2noc_nodes,
>>>>        .num_nodes = ARRAY_SIZE(a2noc_nodes),
>>>> +    .bus_clk_desc = &aggre2_branch_clk,
>>>>        .intf_clocks = a2noc_intf_clocks,
>>>>        .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
>>>>        .regmap_cfg = &msm8996_a2noc_regmap_config
>>>> @@ -1889,6 +1891,7 @@ static const struct qcom_icc_desc msm8996_bimc = {
>>>>        .type = QCOM_ICC_BIMC,
>>>>        .nodes = bimc_nodes,
>>>>        .num_nodes = ARRAY_SIZE(bimc_nodes),
>>>> +    .bus_clk_desc = &bimc_clk,
>>>>        .regmap_cfg = &msm8996_bimc_regmap_config
>>>>    };
>>>>    @@ -1947,6 +1950,7 @@ static const struct qcom_icc_desc msm8996_cnoc = {
>>>>        .type = QCOM_ICC_NOC,
>>>>        .nodes = cnoc_nodes,
>>>>        .num_nodes = ARRAY_SIZE(cnoc_nodes),
>>>> +    .bus_clk_desc = &bus_2_clk,
>>>>        .regmap_cfg = &msm8996_cnoc_regmap_config
>>>>    };
>>>>    @@ -2000,6 +2004,7 @@ static const struct qcom_icc_desc msm8996_mnoc = {
>>>>        .type = QCOM_ICC_NOC,
>>>>        .nodes = mnoc_nodes,
>>>>        .num_nodes = ARRAY_SIZE(mnoc_nodes),
>>>> +    .bus_clk_desc = &mmaxi_0_clk,
>>>
>>> What about an ahb_clk_src here?
>> This should be remodeled to MNoC (MMAXI clk) + MNoC_AHB (ahb_clk_src).
>>
>> I can fix this after this series.
> 
> As long as it doesn't result in a regression.
"works on my machine".. We've not been setting the rate on it
before and it's currently turned on by being an intf_clock, so
I think it doesn't even change the behavior.

Konrad
> 
>> Konrad
>>>
>>>>        .intf_clocks = mm_intf_clocks,
>>>>        .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
>>>>        .regmap_cfg = &msm8996_mnoc_regmap_config
>>>> @@ -2038,6 +2043,7 @@ static const struct qcom_icc_desc msm8996_pnoc = {
>>>>        .type = QCOM_ICC_NOC,
>>>>        .nodes = pnoc_nodes,
>>>>        .num_nodes = ARRAY_SIZE(pnoc_nodes),
>>>> +    .bus_clk_desc = &bus_0_clk,
>>>>        .regmap_cfg = &msm8996_pnoc_regmap_config
>>>>    };
>>>>    @@ -2082,6 +2088,7 @@ static const struct qcom_icc_desc msm8996_snoc = {
>>>>        .type = QCOM_ICC_NOC,
>>>>        .nodes = snoc_nodes,
>>>>        .num_nodes = ARRAY_SIZE(snoc_nodes),
>>>> +    .bus_clk_desc = &bus_1_clk,
>>>>        .regmap_cfg = &msm8996_snoc_regmap_config
>>>>    };
>>>>   
>>>
> 

Re: [PATCH 20/20] interconnect: qcom: Divide clk rate by src node bus width

[Konrad Dybcio]

On 30.05.2023 21:02, Stephan Gerhold wrote:
> On Tue, May 30, 2023 at 06:32:04PM +0200, Konrad Dybcio wrote:
>> On 30.05.2023 12:20, Konrad Dybcio wrote:
>>> Ever since the introduction of SMD RPM ICC, we've been dividing the
>>> clock rate by the wrong bus width. This has resulted in:
>>>
>>> - setting wrong (mostly too low) rates, affecting performance
>>>   - most often /2 or /4
>>>   - things like DDR never hit their full potential
>>>   - the rates were only correct if src bus width == dst bus width
>>>     for all src, dst pairs on a given bus
>>>
>>> - Qualcomm using the same wrong logic in their BSP driver in msm-5.x
>>>   that ships in production devices today
>>>
>>> - me losing my sanity trying to find this
>>>
>>> Resolve it by using dst_qn, if it exists.
>>>
>>> Fixes: 5e4e6c4d3ae0 ("interconnect: qcom: Add QCS404 interconnect provider driver")
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
>> The problem is deeper.
>>
>> Chatting with Stephan (+CC), we tackled a few issues (that I will send
>> fixes for in v2):
>>
>> 1. qcom_icc_rpm_set() should take per-node (src_qn->sum_avg, dst_qn->sum_avg)
>>    and NOT aggregated bw (unless you want ALL of your nodes on a given provider
>>    to "go very fast")
>>
>> 2. the aggregate bw/clk rate calculation should use the node-specific bus widths
>>    and not only the bus width of the src/dst node, otherwise the average bw
>>    values will be utterly meaningless
>>
> 
> The peak bandwidth / clock rate is wrong as well if you have two paths
> with different buswidths on the same bus/NoC. (If someone is interested
> in details I can post my specific example I had in the chat, it shows
> this more clearly.)
agg_peak takes care of that, I believe..


> 
>> 3. thanks to (1) and (2) qcom_icc_bus_aggregate() can be remodeled to instead
>>    calculate the clock rates for the two rpm contexts, which we can then max()
>>    and pass on to the ratesetting call
>>
> 
> Sounds good.
> 
>>
>> ----8<---- Cutting off Stephan's seal of approval, this is my thinking ----
>>
>> 4. I *think* Qualcomm really made a mistake in their msm-5.4 driver where they
>>    took most of the logic from the current -next state and should have been
>>    setting the rate based on the *DST* provider, or at least that's my
>>    understanding trying to read the "known good" msm-4.19 driver
>>    (which remembers msm-3.0 lol).. Or maybe we should keep src but ensure there's
>>    also a final (dst, dst) vote cast:
>>
>> provider->inter_set = false // current state upstream
>>
>> setting apps_proc<->slv_bimc_snoc
>> setting mas_bimc_snoc<->slv_snoc_cnoc
>> setting mas_snoc_cnoc<->qhs_sdc2
>>
>>
>> provider->inter_set = true // I don't think there's effectively a difference?
>>
>> setting apps_proc<->slv_bimc_snoc
>> setting slv_bimc_snoc<->mas_bimc_snoc
>> setting mas_bimc_snoc<->slv_snoc_cnoc
>> setting slv_snoc_cnoc<->mas_snoc_cnoc
>> setting mas_snoc_cnoc<->qhs_sdc2
>>
> 
> I think with our proposed changes above it does no longer matter if a
> node is passed as "src" or "dst". This means in your example above you
> just waste additional time setting the bandwidth twice for
> slv_bimc_snoc, mas_bimc_snoc, slv_snoc_cnoc and mas_snoc_cnoc.
> The final outcome is the same with or without "inter_set".
Yeah I guess due to the fact that two "real" nodes are always
connected by a set of "gateway" nodes, the rate will be applied..

I am however not sure if we're supposed to set the bandwidth
(via qcom_icc_rpm_set()) on all of them..

Konrad
> 
> Thanks,
> Stephan

Re: [PATCH 20/20] interconnect: qcom: Divide clk rate by src node bus width

[Stephan Gerhold]

On Thu, Jun 01, 2023 at 02:43:50PM +0200, Konrad Dybcio wrote:
> On 30.05.2023 21:02, Stephan Gerhold wrote:
> > On Tue, May 30, 2023 at 06:32:04PM +0200, Konrad Dybcio wrote:
> >> On 30.05.2023 12:20, Konrad Dybcio wrote:
> >>> Ever since the introduction of SMD RPM ICC, we've been dividing the
> >>> clock rate by the wrong bus width. This has resulted in:
> >>>
> >>> - setting wrong (mostly too low) rates, affecting performance
> >>>   - most often /2 or /4
> >>>   - things like DDR never hit their full potential
> >>>   - the rates were only correct if src bus width == dst bus width
> >>>     for all src, dst pairs on a given bus
> >>>
> >>> - Qualcomm using the same wrong logic in their BSP driver in msm-5.x
> >>>   that ships in production devices today
> >>>
> >>> - me losing my sanity trying to find this
> >>>
> >>> Resolve it by using dst_qn, if it exists.
> >>>
> >>> Fixes: 5e4e6c4d3ae0 ("interconnect: qcom: Add QCS404 interconnect provider driver")
> >>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> >>> ---
> >> The problem is deeper.
> >>
> >> Chatting with Stephan (+CC), we tackled a few issues (that I will send
> >> fixes for in v2):
> >>
> >> 1. qcom_icc_rpm_set() should take per-node (src_qn->sum_avg, dst_qn->sum_avg)
> >>    and NOT aggregated bw (unless you want ALL of your nodes on a given provider
> >>    to "go very fast")
> >>
> >> 2. the aggregate bw/clk rate calculation should use the node-specific bus widths
> >>    and not only the bus width of the src/dst node, otherwise the average bw
> >>    values will be utterly meaningless
> >>
> > 
> > The peak bandwidth / clock rate is wrong as well if you have two paths
> > with different buswidths on the same bus/NoC. (If someone is interested
> > in details I can post my specific example I had in the chat, it shows
> > this more clearly.)
> agg_peak takes care of that, I believe..
> 

I was just nitpicking on your description here, I think the solution
you/we had in mind was already correct. :)

> 
> > 
> >> 3. thanks to (1) and (2) qcom_icc_bus_aggregate() can be remodeled to instead
> >>    calculate the clock rates for the two rpm contexts, which we can then max()
> >>    and pass on to the ratesetting call
> >>
> > 
> > Sounds good.
> > 
> >>
> >> ----8<---- Cutting off Stephan's seal of approval, this is my thinking ----
> >>
> >> 4. I *think* Qualcomm really made a mistake in their msm-5.4 driver where they
> >>    took most of the logic from the current -next state and should have been
> >>    setting the rate based on the *DST* provider, or at least that's my
> >>    understanding trying to read the "known good" msm-4.19 driver
> >>    (which remembers msm-3.0 lol).. Or maybe we should keep src but ensure there's
> >>    also a final (dst, dst) vote cast:
> >>
> >> provider->inter_set = false // current state upstream
> >>
> >> setting apps_proc<->slv_bimc_snoc
> >> setting mas_bimc_snoc<->slv_snoc_cnoc
> >> setting mas_snoc_cnoc<->qhs_sdc2
> >>
> >>
> >> provider->inter_set = true // I don't think there's effectively a difference?
> >>
> >> setting apps_proc<->slv_bimc_snoc
> >> setting slv_bimc_snoc<->mas_bimc_snoc
> >> setting mas_bimc_snoc<->slv_snoc_cnoc
> >> setting slv_snoc_cnoc<->mas_snoc_cnoc
> >> setting mas_snoc_cnoc<->qhs_sdc2
> >>
> > 
> > I think with our proposed changes above it does no longer matter if a
> > node is passed as "src" or "dst". This means in your example above you
> > just waste additional time setting the bandwidth twice for
> > slv_bimc_snoc, mas_bimc_snoc, slv_snoc_cnoc and mas_snoc_cnoc.
> > The final outcome is the same with or without "inter_set".
> Yeah I guess due to the fact that two "real" nodes are always
> connected by a set of "gateway" nodes, the rate will be applied..
> 
> I am however not sure if we're supposed to set the bandwidth
> (via qcom_icc_rpm_set()) on all of them..
> 

I think so? The nodes RPM doesn't care about shouldn't have
a slv/mas_rpm_id.

Re: [PATCH 20/20] interconnect: qcom: Divide clk rate by src node bus width

[Konrad Dybcio]

On 1.06.2023 15:23, Stephan Gerhold wrote:
> On Thu, Jun 01, 2023 at 02:43:50PM +0200, Konrad Dybcio wrote:
>> On 30.05.2023 21:02, Stephan Gerhold wrote:
>>> On Tue, May 30, 2023 at 06:32:04PM +0200, Konrad Dybcio wrote:
>>>> On 30.05.2023 12:20, Konrad Dybcio wrote:
>>>>> Ever since the introduction of SMD RPM ICC, we've been dividing the
>>>>> clock rate by the wrong bus width. This has resulted in:
>>>>>
>>>>> - setting wrong (mostly too low) rates, affecting performance
>>>>>   - most often /2 or /4
>>>>>   - things like DDR never hit their full potential
>>>>>   - the rates were only correct if src bus width == dst bus width
>>>>>     for all src, dst pairs on a given bus
>>>>>
>>>>> - Qualcomm using the same wrong logic in their BSP driver in msm-5.x
>>>>>   that ships in production devices today
>>>>>
>>>>> - me losing my sanity trying to find this
>>>>>
>>>>> Resolve it by using dst_qn, if it exists.
>>>>>
>>>>> Fixes: 5e4e6c4d3ae0 ("interconnect: qcom: Add QCS404 interconnect provider driver")
>>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>>> ---
>>>> The problem is deeper.
>>>>
>>>> Chatting with Stephan (+CC), we tackled a few issues (that I will send
>>>> fixes for in v2):
>>>>
>>>> 1. qcom_icc_rpm_set() should take per-node (src_qn->sum_avg, dst_qn->sum_avg)
>>>>    and NOT aggregated bw (unless you want ALL of your nodes on a given provider
>>>>    to "go very fast")
>>>>
>>>> 2. the aggregate bw/clk rate calculation should use the node-specific bus widths
>>>>    and not only the bus width of the src/dst node, otherwise the average bw
>>>>    values will be utterly meaningless
>>>>
>>>
>>> The peak bandwidth / clock rate is wrong as well if you have two paths
>>> with different buswidths on the same bus/NoC. (If someone is interested
>>> in details I can post my specific example I had in the chat, it shows
>>> this more clearly.)
>> agg_peak takes care of that, I believe..
>>
> 
> I was just nitpicking on your description here, I think the solution
> you/we had in mind was already correct. :)
> 
>>
>>>
>>>> 3. thanks to (1) and (2) qcom_icc_bus_aggregate() can be remodeled to instead
>>>>    calculate the clock rates for the two rpm contexts, which we can then max()
>>>>    and pass on to the ratesetting call
>>>>
>>>
>>> Sounds good.
>>>
>>>>
>>>> ----8<---- Cutting off Stephan's seal of approval, this is my thinking ----
>>>>
>>>> 4. I *think* Qualcomm really made a mistake in their msm-5.4 driver where they
>>>>    took most of the logic from the current -next state and should have been
>>>>    setting the rate based on the *DST* provider, or at least that's my
>>>>    understanding trying to read the "known good" msm-4.19 driver
>>>>    (which remembers msm-3.0 lol).. Or maybe we should keep src but ensure there's
>>>>    also a final (dst, dst) vote cast:
>>>>
>>>> provider->inter_set = false // current state upstream
>>>>
>>>> setting apps_proc<->slv_bimc_snoc
>>>> setting mas_bimc_snoc<->slv_snoc_cnoc
>>>> setting mas_snoc_cnoc<->qhs_sdc2
>>>>
>>>>
>>>> provider->inter_set = true // I don't think there's effectively a difference?
>>>>
>>>> setting apps_proc<->slv_bimc_snoc
>>>> setting slv_bimc_snoc<->mas_bimc_snoc
>>>> setting mas_bimc_snoc<->slv_snoc_cnoc
>>>> setting slv_snoc_cnoc<->mas_snoc_cnoc
>>>> setting mas_snoc_cnoc<->qhs_sdc2
>>>>
>>>
>>> I think with our proposed changes above it does no longer matter if a
>>> node is passed as "src" or "dst". This means in your example above you
>>> just waste additional time setting the bandwidth twice for
>>> slv_bimc_snoc, mas_bimc_snoc, slv_snoc_cnoc and mas_snoc_cnoc.
>>> The final outcome is the same with or without "inter_set".
>> Yeah I guess due to the fact that two "real" nodes are always
>> connected by a set of "gateway" nodes, the rate will be applied..
>>
>> I am however not sure if we're supposed to set the bandwidth
>> (via qcom_icc_rpm_set()) on all of them..
>>
> 
> I think so? The nodes RPM doesn't care about shouldn't have
> a slv/mas_rpm_id.
Hm I guess the inter_set doesn't make a difference anyway, as you
pointed out.. Thankfully one thing less to fix :D

Konrad