From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Johan Hovold <johan@kernel.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
Vinod Koul <vkoul@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v8 10/10] arm64: dts: qcom: sm8250: provide additional MSI interrupts
Date: Fri, 13 May 2022 15:24:52 +0300 [thread overview]
Message-ID: <CAA8EJpqbs1TYYQG5AmgR0snZDzgcgSobLThQYpDCbEHv3d3mLg@mail.gmail.com> (raw)
In-Reply-To: <Yn5HEUkNW+g20u58@hovoldconsulting.com>
On Fri, 13 May 2022 at 14:55, Johan Hovold <johan@kernel.org> wrote:
>
> On Thu, May 12, 2022 at 01:45:45PM +0300, Dmitry Baryshkov wrote:
> > On SM8250 each group of MSI interrupts is mapped to the separate host
> > interrupt. Describe each of interrupts in the device tree for PCIe0
> > host.
> >
> > Tested on Qualcomm RB5 platform with first group of MSI interrupts being
> > used by the PME and attached ath11k WiFi chip using second group of MSI
> > interrupts.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++++++++--
> > 1 file changed, 9 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > index 410272a1e19b..ef683a2f7412 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > @@ -1807,8 +1807,15 @@ pcie0: pci@1c00000 {
> > ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
> > <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
> >
> > - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> > - interrupt-names = "msi";
> > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "msi", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7";
>
> You must use "msi0" instead of "msi" or you only get 32 MSI regardless
> of what follows currently (and this wouldn't pass DT validation either).
Yes. And that's why I didn't notice that I broke msi0 parsing.
>
> > #interrupt-cells = <1>;
> > interrupt-map-mask = <0 0 0 0x7>;
> > interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
>
> Johan
--
With best wishes
Dmitry
next prev parent reply other threads:[~2022-05-13 12:25 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-12 10:45 [PATCH v8 00/10] PCI: qcom: Fix higher MSI vectors handling Dmitry Baryshkov
2022-05-12 10:45 ` [PATCH v8 01/10] PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" Dmitry Baryshkov
2022-05-12 18:48 ` Bjorn Helgaas
2022-05-12 10:45 ` [PATCH v8 02/10] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
2022-05-12 10:45 ` [PATCH v8 03/10] PCI: dwc: Convert msi_irq to the array Dmitry Baryshkov
2022-05-12 10:45 ` [PATCH v8 04/10] PCI: dwc: Propagate error from dma_mapping_error() Dmitry Baryshkov
2022-05-12 10:45 ` [PATCH v8 05/10] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Dmitry Baryshkov
2022-05-12 18:54 ` Bjorn Helgaas
2022-05-12 10:45 ` [PATCH v8 06/10] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
2022-05-12 18:55 ` Bjorn Helgaas
2022-05-13 11:52 ` Johan Hovold
2022-05-13 12:19 ` Dmitry Baryshkov
2022-05-13 12:33 ` Johan Hovold
2022-05-12 10:45 ` [PATCH v8 07/10] PCI: qcom: " Dmitry Baryshkov
2022-05-13 12:42 ` Johan Hovold
2022-05-13 12:48 ` Dmitry Baryshkov
2022-05-13 12:57 ` Johan Hovold
2022-05-12 10:45 ` [PATCH v8 08/10] PCI: dwc: Implement special ISR handler for split MSI IRQ setup Dmitry Baryshkov
2022-05-12 10:45 ` [PATCH v8 09/10] dt-bindings: PCI: qcom: Support additional MSI interrupts Dmitry Baryshkov
2022-05-12 10:45 ` [PATCH v8 10/10] arm64: dts: qcom: sm8250: provide " Dmitry Baryshkov
2022-05-13 11:54 ` Johan Hovold
2022-05-13 12:24 ` Dmitry Baryshkov [this message]
2022-05-13 8:58 ` [PATCH v8 00/10] PCI: qcom: Fix higher MSI vectors handling Johan Hovold
2022-05-13 9:28 ` Dmitry Baryshkov
2022-05-13 9:36 ` Johan Hovold
2022-05-13 10:10 ` Dmitry Baryshkov
2022-05-13 12:52 ` Johan Hovold
2022-05-13 13:50 ` Dmitry Baryshkov
2022-05-13 15:11 ` Johan Hovold
2022-05-13 12:39 ` Dmitry Baryshkov
2022-05-13 13:08 ` Dmitry Baryshkov
2022-05-13 13:17 ` Johan Hovold
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