From: Doug Anderson <dianders@chromium.org>
To: Sharat Masetty <smasetty@codeaurora.org>
Cc: freedreno <freedreno@lists.freedesktop.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
dri-devel@freedesktop.org,
linux-arm-msm <linux-arm-msm@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Jordan Crouse <jcrouse@codeaurora.org>,
Matthias Kaehlcke <mka@chromium.org>
Subject: Re: [PATCH v3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
Date: Fri, 31 Jan 2020 13:43:06 -0800 [thread overview]
Message-ID: <CAD=FV=XJF4KworkHFLoNtxB7d+VyGqZSZkDUdie+09ur1g5thw@mail.gmail.com> (raw)
In-Reply-To: <1580472220-3453-2-git-send-email-smasetty@codeaurora.org>
Hi,
On Fri, Jan 31, 2020 at 4:04 AM Sharat Masetty <smasetty@codeaurora.org> wrote:
>
> + adreno_smmu: iommu@5040000 {
> + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
> + reg = <0 0x05040000 0 0x10000>;
> + #iommu-cells = <1>;
> + #global-interrupts = <2>;
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gcc GCC_GPU_CFG_AHB_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>;
> +
> + clock-names = "bus", "iface", "mem_iface_clk";
Repeated comment from v2 feedback:
Please send a patch to:
Documentation/devicetree/bindings/iommu/arm,smmu.yaml
...adding 'qcom,sc7180-smmu-v2'. If you do this it will point out
that you've added a new clock: "mem_iface_clk". Is this truly a new
clock in sc7180 compared to previous IOMMUs? ...or is it not really
needed?
> + gmu: gmu@506a000 {
> + compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
> + reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
> + <0 0x0b490000 0 0x10000>;
> + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hfi", "gmu";
> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
> + clock-names = "gmu", "cxo", "axi", "memnoc";
> + power-domains = <&gpucc CX_GDSC>;
> + power-domain-names = "cx";
As per continued comments on v2, please see if this works for you:
power-domains = <&gpucc CX_GDSC>, <0>;
power-domain-names = "cx", "gx";
...and work to get something more real for "gx" ASAP. It did seem to
boot for me and (unless someone disagrees) it seems better than
totally leaving it out / violating the bindings?
-Doug
next prev parent reply other threads:[~2020-01-31 21:43 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-31 12:03 [PATCH v3] Add A618 GPU nodes Sharat Masetty
2020-01-31 12:03 ` [PATCH v3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob Sharat Masetty
2020-01-31 21:43 ` Doug Anderson [this message]
2020-02-05 6:51 ` smasetty
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