From: Rob Clark <robdclark@gmail.com>
To: Sharat Masetty <smasetty@codeaurora.org>
Cc: freedreno <freedreno@lists.freedesktop.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>
Subject: Re: [PATCH] rnndb: Add GBIF registers for a6xx GPU
Date: Mon, 2 Dec 2019 09:24:59 -0800 [thread overview]
Message-ID: <CAF6AEGtMXOjZPG1_EwdwBGp7TOVrXwBKo6eG-ryT_-OhxrfQWg@mail.gmail.com> (raw)
In-Reply-To: <0101016eb61a0601-14bd7732-c07c-4674-899f-0e570c145195-000000@us-west-2.amazonses.com>
On Thu, Nov 28, 2019 at 11:41 PM Sharat Masetty <smasetty@codeaurora.org> wrote:
>
> Add GBIF register definitions required to implement a618
> GPU revision
>
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
thanks, I've pushed the xml to envytools
BR,
-R
> ---
> rnndb/adreno/a6xx.xml | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/rnndb/adreno/a6xx.xml b/rnndb/adreno/a6xx.xml
> index 747f071..2d2063a 100644
> --- a/rnndb/adreno/a6xx.xml
> +++ b/rnndb/adreno/a6xx.xml
> @@ -1748,6 +1748,32 @@ to upconvert to 32b float internally?
> <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
> <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
>
> + <!-- GBIF registers -->
> + <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
> + <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
> + <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
> + <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
> + <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
> + <reg32 offset="0x3c45" name="GBIF_HALT"/>
> + <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
> +
> + <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
> + <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
> + <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
> + <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
> + <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
> + <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
> + <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
> + <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
> + <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
> + <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
> + <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
> + <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
> + <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
> + <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
> + <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
> + <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
> + <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
> <!-- move/rename these.. -->
>
> <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/>
> --
> 1.9.1
>
prev parent reply other threads:[~2019-12-02 17:25 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-29 7:39 [PATCH] rnndb: Add GBIF registers for a6xx GPU Sharat Masetty
2019-12-02 17:24 ` Rob Clark [this message]
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