Linux-ARM-MSM Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH] rnndb: Add GBIF registers for a6xx GPU
@ 2019-11-29  7:39 Sharat Masetty
  2019-12-02 17:24 ` Rob Clark
  0 siblings, 1 reply; 2+ messages in thread
From: Sharat Masetty @ 2019-11-29  7:39 UTC (permalink / raw)
  To: freedreno; +Cc: dri-devel, linux-arm-msm, Sharat Masetty

Add GBIF register definitions required to implement a618
GPU revision

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
 rnndb/adreno/a6xx.xml | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/rnndb/adreno/a6xx.xml b/rnndb/adreno/a6xx.xml
index 747f071..2d2063a 100644
--- a/rnndb/adreno/a6xx.xml
+++ b/rnndb/adreno/a6xx.xml
@@ -1748,6 +1748,32 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
 	<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
 
+	<!-- GBIF registers -->
+	<reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
+	<reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
+	<reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
+	<reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
+	<reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
+	<reg32 offset="0x3c45" name="GBIF_HALT"/>
+	<reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
+
+	<reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
+	<reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
+	<reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
+	<reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
+	<reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
+	<reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
+	<reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
+	<reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
+	<reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
+	<reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
+	<reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
+	<reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
+	<reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
+	<reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
+	<reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
+	<reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
+	<reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
 	<!-- move/rename these.. -->
 
 	<reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/>
-- 
1.9.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] rnndb: Add GBIF registers for a6xx GPU
  2019-11-29  7:39 [PATCH] rnndb: Add GBIF registers for a6xx GPU Sharat Masetty
@ 2019-12-02 17:24 ` Rob Clark
  0 siblings, 0 replies; 2+ messages in thread
From: Rob Clark @ 2019-12-02 17:24 UTC (permalink / raw)
  To: Sharat Masetty; +Cc: freedreno, dri-devel, linux-arm-msm

On Thu, Nov 28, 2019 at 11:41 PM Sharat Masetty <smasetty@codeaurora.org> wrote:
>
> Add GBIF register definitions required to implement a618
> GPU revision
>
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>

thanks, I've pushed the xml to envytools

BR,
-R

> ---
>  rnndb/adreno/a6xx.xml | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/rnndb/adreno/a6xx.xml b/rnndb/adreno/a6xx.xml
> index 747f071..2d2063a 100644
> --- a/rnndb/adreno/a6xx.xml
> +++ b/rnndb/adreno/a6xx.xml
> @@ -1748,6 +1748,32 @@ to upconvert to 32b float internally?
>         <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
>         <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
>
> +       <!-- GBIF registers -->
> +       <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
> +       <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
> +       <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
> +       <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
> +       <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
> +       <reg32 offset="0x3c45" name="GBIF_HALT"/>
> +       <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
> +
> +       <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
> +       <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
> +       <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
> +       <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
> +       <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
> +       <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
> +       <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
> +       <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
> +       <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
> +       <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
> +       <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
> +       <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
> +       <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
> +       <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
> +       <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
> +       <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
> +       <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
>         <!-- move/rename these.. -->
>
>         <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/>
> --
> 1.9.1
>

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, back to index

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-29  7:39 [PATCH] rnndb: Add GBIF registers for a6xx GPU Sharat Masetty
2019-12-02 17:24 ` Rob Clark

Linux-ARM-MSM Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-arm-msm/0 linux-arm-msm/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-arm-msm linux-arm-msm/ https://lore.kernel.org/linux-arm-msm \
		linux-arm-msm@vger.kernel.org
	public-inbox-index linux-arm-msm

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-arm-msm


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git