* [PATCH v3 00/11] Enable Display for SM8350
@ 2022-12-05 16:37 Robert Foss
2022-12-05 16:37 ` [PATCH v3 01/11] dt-bindings: display: msm: Add qcom,sm8350-dpu binding Robert Foss
` (10 more replies)
0 siblings, 11 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-05 16:37 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
robert.foss, loic.poulain, swboyd, quic_vpolimer, vkoul,
dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
Dependencies:
https://lore.kernel.org/all/20221102231309.583587-1-dmitry.baryshkov@linaro.org/
https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.baryshkov@linaro.org/
https://lore.kernel.org/all/20221104130324.1024242-5-dmitry.baryshkov@linaro.org/
Branch:
https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v3
This series implements display support for SM8350 and
enables HDMI output for the SM8350-HDK platform.
Changes from v1:
- Added R-b tags from v1
- Added qcom,sm8350-dpu binding patch
- Added qcom,sm8350-mdss binding patch
- Corrected sm8350.dtsi according to new dpu/mdss bindings
- Bjorn: Removed regulator-always-on property from lt9611_1v2 regulator
- Bjorn: Moved lt9611 pinctl pins into a common node
- Bjorn/Krzysztof: Moved status property to last in node
- Krzysztof: Changed hdmi-out to hdmi-connector
- Krzysztof: Fixed regulator node name
- Krzysztof: Changed &mdss to status=disabled as default
- Krzysztof: Changed &mdss_mdp node name to display-controller
- Krzysztof: Fixed opp-table node name
- Krzysztof: Fixed phy node name
- Dmitry: Split commit containing dpu & mdss compatibles string
- Dmitry: Added msm_mdss_enable case
- Dmitry: Fixed dpu ctl features
Changes from v2:
- Rob: Added r-b
- Rob: Improved mdss binding description
- Rob: Added interconnect names for mdss-binding
- Rob: Removed phy from example
- Konrad: Remove sc7280_pp refactor patch
- Konrad: Fixed upper case hex in dpu_hw_catalog
- Konrad: Fixed various downstream dts based values for dpu_hw_catalog
- Konrad: Removed status=disabled from mdss_mdp
- Konrad: Removed phy-names from dsi nodes
- Konrad/Dmitry: Change mdp_opp_table opp-200000000 to use &rpmhpd_opp_svs, add comment
- Dmitry: Move mdp_opp_table to dsi0 node
Robert Foss (11):
dt-bindings: display: msm: Add qcom,sm8350-dpu binding
dt-bindings: display: msm: Add qcom,sm8350-mdss binding
drm/msm/dpu: Add SM8350 to hw catalog
drm/msm/dpu: Add support for SM8350
drm/msm: Add support for SM8350
arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
arm64: dts: qcom: sm8350: Use 2 interconnect cells
arm64: dts: qcom: sm8350: Add display system nodes
arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
.../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 +++++++
.../display/msm/qcom,sm8350-mdss.yaml | 221 ++++++++++++
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 332 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8350.dtsi | 228 +++++++++++-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 196 +++++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_mdss.c | 4 +
8 files changed, 1084 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
--
2.34.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 01/11] dt-bindings: display: msm: Add qcom,sm8350-dpu binding
2022-12-05 16:37 [PATCH v3 00/11] Enable Display for SM8350 Robert Foss
@ 2022-12-05 16:37 ` Robert Foss
2022-12-05 16:37 ` [PATCH v3 02/11] dt-bindings: display: msm: Add qcom,sm8350-mdss binding Robert Foss
` (9 subsequent siblings)
10 siblings, 0 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-05 16:37 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
robert.foss, loic.poulain, swboyd, quic_vpolimer, vkoul,
dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
Cc: Rob Herring
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for DPU device
tree bindings
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++++++++++++++++++
1 file changed, 120 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
new file mode 100644
index 000000000000..120500395c9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display DPU
+
+maintainers:
+ - Robert Foss <robert.foss@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm8350-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display ahb clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm8350.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,sm8350.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+...
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 02/11] dt-bindings: display: msm: Add qcom,sm8350-mdss binding
2022-12-05 16:37 [PATCH v3 00/11] Enable Display for SM8350 Robert Foss
2022-12-05 16:37 ` [PATCH v3 01/11] dt-bindings: display: msm: Add qcom,sm8350-dpu binding Robert Foss
@ 2022-12-05 16:37 ` Robert Foss
2022-12-05 21:08 ` Rob Herring
2022-12-05 16:37 ` [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog Robert Foss
` (8 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Robert Foss @ 2022-12-05 16:37 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
robert.foss, loic.poulain, swboyd, quic_vpolimer, vkoul,
dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for MDSS device
tree bindings
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
.../display/msm/qcom,sm8350-mdss.yaml | 221 ++++++++++++++++++
1 file changed, 221 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
new file mode 100644
index 000000000000..d9aa6e857d1f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
@@ -0,0 +1,221 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display MDSS
+
+maintainers:
+ - Robert Foss <robert.foss@linaro.org>
+
+description:
+ MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
+ DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm8350-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: nrt_bus
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: mdp0-mem
+ - const: mdp1-mem
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm8350-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,dsi-phy-5nm-8350
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
+ #include <dt-bindings/clock/qcom,gcc-sm8350.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,sm8350.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,sm8350-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ iommus = <&apps_smmu 0x820 0x402>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>,
+ <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ phys = <&dsi0_phy>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+ };
+...
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog
2022-12-05 16:37 [PATCH v3 00/11] Enable Display for SM8350 Robert Foss
2022-12-05 16:37 ` [PATCH v3 01/11] dt-bindings: display: msm: Add qcom,sm8350-dpu binding Robert Foss
2022-12-05 16:37 ` [PATCH v3 02/11] dt-bindings: display: msm: Add qcom,sm8350-mdss binding Robert Foss
@ 2022-12-05 16:37 ` Robert Foss
2022-12-05 16:43 ` Konrad Dybcio
` (2 more replies)
2022-12-05 16:37 ` [PATCH v3 04/11] drm/msm/dpu: Add support for SM8350 Robert Foss
` (7 subsequent siblings)
10 siblings, 3 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-05 16:37 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
robert.foss, loic.poulain, swboyd, quic_vpolimer, vkoul,
dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 196 ++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
2 files changed, 197 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4dac90ee5b8a..ba26af73be53 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -112,6 +112,15 @@
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR))
+#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_7xxx_INTR) | \
+ BIT(MDP_INTF1_7xxx_INTR) | \
+ BIT(MDP_INTF2_7xxx_INTR) | \
+ BIT(MDP_INTF3_7xxx_INTR) | \
+ 0)
+
#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
@@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sm8450_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2ac, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2b4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2bc, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2c4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2ac, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2b4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2bc, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2c4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2bc, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sm8450_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_ctl_cfg sm8450_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1294,6 +1383,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
-1),
};
+static const struct dpu_pingpong_cfg sm8350_pp[] = {
+ PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
+ PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
+ PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
+ PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
+ PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ -1),
+ PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ -1),
+};
+
static struct dpu_pingpong_cfg qcm2290_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1345,6 +1455,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
};
+static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
+ MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
+ MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
+ MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
+};
+
static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
@@ -1376,6 +1492,12 @@ static struct dpu_dsc_cfg sdm845_dsc[] = {
DSC_BLK("dsc_3", DSC_3, 0x80c00),
};
+static struct dpu_dsc_cfg sm8350_dsc[] = {
+ DSC_BLK("dsc_0", DSC_0, 0x80000),
+ DSC_BLK("dsc_1", DSC_1, 0x81000),
+ DSC_BLK("dsc_2", DSC_2, 0x82000),
+};
+
/*************************************************************
* INTF sub blocks config
*************************************************************/
@@ -1423,6 +1545,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
};
+static const struct dpu_intf_cfg sm8350_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+};
+
static const struct dpu_intf_cfg sc8180x_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
@@ -1558,6 +1687,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = {
.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
};
+static const struct dpu_reg_dma_cfg sm8350_regdma = {
+ .base = 0x400,
+ .version = 0x00020000,
+ .trigger_sel_off = 0x119c,
+ .xin_id = 7,
+ .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
+};
+
static const struct dpu_reg_dma_cfg sm8450_regdma = {
.base = 0x0,
.version = 0x00020000,
@@ -1899,6 +2036,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
.bw_inefficiency_factor = 120,
};
+static const struct dpu_perf_cfg sm8350_perf_data = {
+ .max_bw_low = 11800000,
+ .max_bw_high = 15500000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 800000,
+ .min_prefill_lines = 40,
+ /* FIXME: lut tables */
+ .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
+ .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+ .entries = sc7180_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
static const struct dpu_perf_cfg qcm2290_perf_data = {
.max_bw_low = 2700000,
.max_bw_high = 2700000,
@@ -2075,6 +2242,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
.mdss_irqs = IRQ_SM8250_MASK,
};
+static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
+ .caps = &sm8350_dpu_caps,
+ .mdp_count = ARRAY_SIZE(sm8350_mdp),
+ .mdp = sm8350_mdp,
+ .ctl_count = ARRAY_SIZE(sm8350_ctl),
+ .ctl = sm8350_ctl,
+ .sspp_count = ARRAY_SIZE(sm8250_sspp),
+ .sspp = sm8250_sspp,
+ .mixer_count = ARRAY_SIZE(sm8150_lm),
+ .mixer = sm8150_lm,
+ .dspp_count = ARRAY_SIZE(sm8150_dspp),
+ .dspp = sm8150_dspp,
+ .pingpong_count = ARRAY_SIZE(sm8350_pp),
+ .pingpong = sm8350_pp,
+ .dsc_count = ARRAY_SIZE(sm8350_dsc),
+ .dsc = sm8350_dsc,
+ .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
+ .merge_3d = sm8350_merge_3d,
+ .intf_count = ARRAY_SIZE(sm8350_intf),
+ .intf = sm8350_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .reg_dma_count = 1,
+ .dma_cfg = &sm8250_regdma,
+ .perf = &sm8350_perf_data,
+ .mdss_irqs = IRQ_SM8350_MASK,
+};
+
static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
.caps = &sm8450_dpu_caps,
.mdp_count = ARRAY_SIZE(sm8450_mdp),
@@ -2158,6 +2353,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
{ .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
{ .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
+ { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
{ .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 664c4876f44a..5335123a0289 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -45,6 +45,7 @@
#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
+#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 04/11] drm/msm/dpu: Add support for SM8350
2022-12-05 16:37 [PATCH v3 00/11] Enable Display for SM8350 Robert Foss
` (2 preceding siblings ...)
2022-12-05 16:37 ` [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog Robert Foss
@ 2022-12-05 16:37 ` Robert Foss
2022-12-07 23:40 ` Dmitry Baryshkov
2022-12-07 23:47 ` Abhinav Kumar
2022-12-05 16:37 ` [PATCH v3 05/11] drm/msm: " Robert Foss
` (6 subsequent siblings)
10 siblings, 2 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-05 16:37 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
robert.foss, loic.poulain, swboyd, quic_vpolimer, vkoul,
dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
Add compatibles string, "qcom,sm8350-dpu", for the display processing unit
used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 9827914dc096..6048bfae0824 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1322,6 +1322,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", },
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
+ { .compatible = "qcom,sm8350-dpu", },
{ .compatible = "qcom,sm8450-dpu", },
{}
};
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 05/11] drm/msm: Add support for SM8350
2022-12-05 16:37 [PATCH v3 00/11] Enable Display for SM8350 Robert Foss
` (3 preceding siblings ...)
2022-12-05 16:37 ` [PATCH v3 04/11] drm/msm/dpu: Add support for SM8350 Robert Foss
@ 2022-12-05 16:37 ` Robert Foss
2022-12-05 16:43 ` Konrad Dybcio
2022-12-07 23:50 ` Dmitry Baryshkov
2022-12-05 16:37 ` [PATCH v3 06/11] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names Robert Foss
` (5 subsequent siblings)
10 siblings, 2 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-05 16:37 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
robert.foss, loic.poulain, swboyd, quic_vpolimer, vkoul,
dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
subsystem unit used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index a2264fb517a1..39746b972cdd 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
/* UBWC_2_0 */
msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
break;
+ case DPU_HW_VER_700:
+ msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1);
+ break;
case DPU_HW_VER_720:
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
@@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+ { .compatible = "qcom,sm8350-mdss" },
{ .compatible = "qcom,sm8450-mdss" },
{}
};
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 06/11] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
2022-12-05 16:37 [PATCH v3 00/11] Enable Display for SM8350 Robert Foss
` (4 preceding siblings ...)
2022-12-05 16:37 ` [PATCH v3 05/11] drm/msm: " Robert Foss
@ 2022-12-05 16:37 ` Robert Foss
2022-12-05 16:37 ` [PATCH v3 07/11] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name Robert Foss
` (4 subsequent siblings)
10 siblings, 0 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-05 16:37 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
robert.foss, loic.poulain, swboyd, quic_vpolimer, vkoul,
dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
Add GPIO line names as described by the sm8350-hdk schematic.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 205 ++++++++++++++++++++++++
1 file changed, 205 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 0fcf5bd88fc7..e6deb08c6da0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -233,6 +233,211 @@ &slpi {
&tlmm {
gpio-reserved-ranges = <52 8>;
+
+ gpio-line-names =
+ "APPS_I2C_SDA", /* GPIO_0 */
+ "APPS_I2C_SCL",
+ "FSA_INT_N",
+ "USER_LED3_EN",
+ "SMBUS_SDA_1P8",
+ "SMBUS_SCL_1P8",
+ "2M2_3P3_EN",
+ "ALERT_DUAL_M2_N",
+ "EXP_UART_CTS",
+ "EXP_UART_RFR",
+ "EXP_UART_TX", /* GPIO_10 */
+ "EXP_UART_RX",
+ "NC",
+ "NC",
+ "RCM_MARKER1",
+ "WSA0_EN",
+ "CAM1_RESET_N",
+ "CAM0_RESET_N",
+ "DEBUG_UART_TX",
+ "DEBUG_UART_RX",
+ "TS_I2C_SDA", /* GPIO_20 */
+ "TS_I2C_SCL",
+ "TS_RESET_N",
+ "TS_INT_N",
+ "DISP0_RESET_N",
+ "DISP1_RESET_N",
+ "ETH_RESET",
+ "RCM_MARKER2",
+ "CAM_DC_MIPI_MUX_EN",
+ "CAM_DC_MIPI_MUX_SEL",
+ "AFC_PHY_TA_D_PLUS", /* GPIO_30 */
+ "AFC_PHY_TA_D_MINUS",
+ "PM8008_1_IRQ",
+ "PM8008_1_RESET_N",
+ "PM8008_2_IRQ",
+ "PM8008_2_RESET_N",
+ "CAM_DC_I3C_SDA",
+ "CAM_DC_I3C_SCL",
+ "FP_INT_N",
+ "FP_WUHB_INT_N",
+ "SMB_SPMI_DATA", /* GPIO_40 */
+ "SMB_SPMI_CLK",
+ "USB_HUB_RESET",
+ "FORCE_USB_BOOT",
+ "LRF_IRQ",
+ "NC",
+ "IMU2_INT",
+ "HDMI_3P3_EN",
+ "HDMI_RSTN",
+ "HDMI_1P2_EN",
+ "HDMI_INT", /* GPIO_50 */
+ "USB1_ID",
+ "FP_SPI_MISO",
+ "FP_SPI_MOSI",
+ "FP_SPI_CLK",
+ "FP_SPI_CS_N",
+ "NFC_ESE_SPI_MISO",
+ "NFC_ESE_SPI_MOSI",
+ "NFC_ESE_SPI_CLK",
+ "NFC_ESE_SPI_CS",
+ "NFC_I2C_SDA", /* GPIO_60 */
+ "NFC_I2C_SCLC",
+ "NFC_EN",
+ "NFC_CLK_REQ",
+ "HST_WLAN_EN",
+ "HST_BT_EN",
+ "HST_SW_CTRL",
+ "NC",
+ "HST_BT_UART_CTS",
+ "HST_BT_UART_RFR",
+ "HST_BT_UART_TX", /* GPIO_70 */
+ "HST_BT_UART_RX",
+ "CAM_DC_SPI0_MISO",
+ "CAM_DC_SPI0_MOSI",
+ "CAM_DC_SPI0_CLK",
+ "CAM_DC_SPI0_CS_N",
+ "CAM_DC_SPI1_MISO",
+ "CAM_DC_SPI1_MOSI",
+ "CAM_DC_SPI1_CLK",
+ "CAM_DC_SPI1_CS_N",
+ "HALL_INT_N", /* GPIO_80 */
+ "USB_PHY_PS",
+ "MDP_VSYNC_P",
+ "MDP_VSYNC_S",
+ "ETH_3P3_EN",
+ "RADAR_INT",
+ "NFC_DWL_REQ",
+ "SM_GPIO_87",
+ "WCD_RESET_N",
+ "ALSP_INT_N",
+ "PRESS_INT", /* GPIO_90 */
+ "SAR_INT_N",
+ "SD_CARD_DET_N",
+ "NC",
+ "PCIE0_RESET_N",
+ "PCIE0_CLK_REQ_N",
+ "PCIE0_WAKE_N",
+ "PCIE1_RESET_N",
+ "PCIE1_CLK_REQ_N",
+ "PCIE1_WAKE_N",
+ "CAM_MCLK0", /* GPIO_100 */
+ "CAM_MCLK1",
+ "CAM_MCLK2",
+ "CAM_MCLK3",
+ "CAM_MCLK4",
+ "CAM_MCLK5",
+ "CAM2_RESET_N",
+ "CCI_I2C0_SDA",
+ "CCI_I2C0_SCL",
+ "CCI_I2C1_SDA",
+ "CCI_I2C1_SCL", /* GPIO_110 */
+ "CCI_I2C2_SDA",
+ "CCI_I2C2_SCL",
+ "CCI_I2C3_SDA",
+ "CCI_I2C3_SCL",
+ "CAM5_RESET_N",
+ "CAM4_RESET_N",
+ "CAM3_RESET_N",
+ "IMU1_INT",
+ "MAG_INT_N",
+ "MI2S2_I2S_SCK", /* GPIO_120 */
+ "MI2S2_I2S_DAT0",
+ "MI2S2_I2S_WS",
+ "HIFI_DAC_I2S_MCLK",
+ "MI2S2_I2S_DAT1",
+ "HIFI_DAC_I2S_SCK",
+ "HIFI_DAC_I2S_DAT0",
+ "NC",
+ "HIFI_DAC_I2S_WS",
+ "HST_BT_WLAN_SLIMBUS_CLK",
+ "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */
+ "BT_LED_EN",
+ "WLAN_LED_EN",
+ "NC",
+ "NC",
+ "NC",
+ "UIM2_PRESENT",
+ "NC",
+ "NC",
+ "NC",
+ "UIM1_PRESENT", /* GPIO_140 */
+ "NC",
+ "SM_RFFE0_DATA",
+ "NC",
+ "SM_RFFE1_DATA",
+ "SM_MSS_GRFC4",
+ "SM_MSS_GRFC5",
+ "SM_MSS_GRFC6",
+ "SM_MSS_GRFC7",
+ "SM_RFFE4_CLK",
+ "SM_RFFE4_DATA", /* GPIO_150 */
+ "WLAN_COEX_UART1_RX",
+ "WLAN_COEX_UART1_TX",
+ "HST_SW_CTRL",
+ "DSI0_STATUS",
+ "DSI1_STATUS",
+ "APPS_PBL_BOOT_SPEED_1",
+ "APPS_BOOT_FROM_ROM",
+ "APPS_PBL_BOOT_SPEED_0",
+ "QLINK0_REQ",
+ "QLINK0_EN", /* GPIO_160 */
+ "QLINK0_WMSS_RESET_N",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "WCD_SWR_TX_CLK",
+ "WCD_SWR_TX_DATA0",
+ "WCD_SWR_TX_DATA1", /* GPIO_170 */
+ "WCD_SWR_RX_CLK",
+ "WCD_SWR_RX_DATA0",
+ "WCD_SWR_RX_DATA1",
+ "DMIC01_CLK",
+ "DMIC01_DATA",
+ "DMIC23_CLK",
+ "DMIC23_DATA",
+ "WSA_SWR_CLK",
+ "WSA_SWR_DATA",
+ "DMIC45_CLK", /* GPIO_180 */
+ "DMIC45_DATA",
+ "WCD_SWR_TX_DATA2",
+ "SENSOR_I3C_SDA",
+ "SENSOR_I3C_SCL",
+ "CAM_OIS0_I3C_SDA",
+ "CAM_OIS0_I3C_SCL",
+ "IMU_SPI_MISO",
+ "IMU_SPI_MOSI",
+ "IMU_SPI_CLK",
+ "IMU_SPI_CS_N", /* GPIO_190 */
+ "MAG_I2C_SDA",
+ "MAG_I2C_SCL",
+ "SENSOR_I2C_SDA",
+ "SENSOR_I2C_SCL",
+ "RADAR_SPI_MISO",
+ "RADAR_SPI_MOSI",
+ "RADAR_SPI_CLK",
+ "RADAR_SPI_CS_N",
+ "HST_BLE_UART_TX",
+ "HST_BLE_UART_RX", /* GPIO_200 */
+ "HST_WLAN_UART_TX",
+ "HST_WLAN_UART_RX";
};
&uart2 {
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 07/11] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
2022-12-05 16:37 [PATCH v3 00/11] Enable Display for SM8350 Robert Foss
` (5 preceding siblings ...)
2022-12-05 16:37 ` [PATCH v3 06/11] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names Robert Foss
@ 2022-12-05 16:37 ` Robert Foss
2022-12-05 16:37 ` [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells Robert Foss
` (3 subsequent siblings)
10 siblings, 0 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-05 16:37 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
robert.foss, loic.poulain, swboyd, quic_vpolimer, vkoul,
dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
Cc: Konrad Dybcio
The mmxc power-domain-name is not required, and is not
used by either earlier or later SoC versions (sm8250 / sm8450).
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index cbd48f248df4..805d53d91952 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2558,7 +2558,6 @@ dispcc: clock-controller@af00000 {
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8350_MMCX>;
- power-domain-names = "mmcx";
};
adsp: remoteproc@17300000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells
2022-12-05 16:37 [PATCH v3 00/11] Enable Display for SM8350 Robert Foss
` (6 preceding siblings ...)
2022-12-05 16:37 ` [PATCH v3 07/11] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name Robert Foss
@ 2022-12-05 16:37 ` Robert Foss
2022-12-05 19:19 ` Georgi Djakov
2022-12-05 16:37 ` [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes Robert Foss
` (2 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Robert Foss @ 2022-12-05 16:37 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
robert.foss, loic.poulain, swboyd, quic_vpolimer, vkoul,
dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
Cc: Konrad Dybcio
Use two interconnect cells in order to optionally
support a path tag.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 805d53d91952..434f8e8b12c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1543,56 +1543,56 @@ apps_smmu: iommu@15000000 {
config_noc: interconnect@1500000 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x01500000 0 0xa580>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@1580000 {
compatible = "qcom,sm8350-mc-virt";
reg = <0 0x01580000 0 0x1000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1680000 {
compatible = "qcom,sm8350-system-noc";
reg = <0 0x01680000 0 0x1c200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm8350-aggre1-noc";
reg = <0 0x016e0000 0 0x1f180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@1700000 {
compatible = "qcom,sm8350-aggre2-noc";
reg = <0 0x01700000 0 0x33000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
compatible = "qcom,sm8350-mmss-noc";
reg = <0 0x01740000 0 0x1f080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_ag_noc: interconnect@3c40000 {
compatible = "qcom,sm8350-lpass-ag-noc";
reg = <0 0x03c40000 0 0xf080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
compute_noc: interconnect@a0c0000{
compatible = "qcom,sm8350-compute-noc";
reg = <0 0x0a0c0000 0 0xa180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
@@ -1620,8 +1620,8 @@ ipa: ipa@1e40000 {
clocks = <&rpmhcc RPMH_IPA_CLK>;
clock-names = "core";
- interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
- <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
+ interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
interconnect-names = "memory",
"config";
@@ -1661,7 +1661,7 @@ mpss: remoteproc@4080000 {
<&rpmhpd SM8350_MSS>;
power-domain-names = "cx", "mss";
- interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
+ interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1 0>;
memory-region = <&pil_modem_mem>;
@@ -2239,7 +2239,7 @@ cdsp: remoteproc@98900000 {
<&rpmhpd SM8350_MXC>;
power-domain-names = "cx", "mxc";
- interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
+ interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
memory-region = <&pil_cdsp_mem>;
@@ -2421,14 +2421,14 @@ usb_2_ssphy: phy@88ebe00 {
dc_noc: interconnect@90c0000 {
compatible = "qcom,sm8350-dc-noc";
reg = <0 0x090c0000 0 0x4200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect@9100000 {
compatible = "qcom,sm8350-gem-noc";
reg = <0 0x09100000 0 0xb4000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
2022-12-05 16:37 [PATCH v3 00/11] Enable Display for SM8350 Robert Foss
` (7 preceding siblings ...)
2022-12-05 16:37 ` [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells Robert Foss
@ 2022-12-05 16:37 ` Robert Foss
2022-12-05 16:43 ` Dmitry Baryshkov
` (2 more replies)
2022-12-05 16:37 ` [PATCH v3 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes Robert Foss
2022-12-05 16:37 ` [PATCH v3 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Robert Foss
10 siblings, 3 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-05 16:37 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
robert.foss, loic.poulain, swboyd, quic_vpolimer, vkoul,
dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
nodes the display subsystem is configured to support
one DSI output.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++++++++++++++++++++++++++-
1 file changed, 195 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 434f8e8b12c1..fb1c616c5e89 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2020, Linaro Limited
*/
+#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
@@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a800000 {
};
};
+ mdss: mdss@ae00000 {
+ compatible = "qcom,sm8350-mdss";
+ reg = <0 0x0ae00000 0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x820 0x402>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb0000 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>,
+ <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ phys = <&dsi0_phy>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* TODO: opp-200000000 should work with
+ * &rpmhpd_opp_low_svs, but one some of
+ * sm8350_hdk boards reboot using this
+ * opp.
+ */
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ dsi0_phy: phy@ae94400 {
+ compatible = "qcom,dsi-phy-5nm-8350";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94900 0 0x260>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+
+ dsi_opp_table: dsi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,sm8350-dispcc";
reg = <0 0x0af00000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
- <0>,
- <0>,
- <0>,
- <0>,
+ <&dsi0_phy 0>, <&dsi0_phy 1>,
+ <0>, <0>,
<0>,
<0>;
clock-names = "bi_tcxo",
@@ -2558,6 +2748,7 @@ dispcc: clock-controller@af00000 {
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8350_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
};
adsp: remoteproc@17300000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
2022-12-05 16:37 [PATCH v3 00/11] Enable Display for SM8350 Robert Foss
` (8 preceding siblings ...)
2022-12-05 16:37 ` [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes Robert Foss
@ 2022-12-05 16:37 ` Robert Foss
2022-12-05 16:44 ` Dmitry Baryshkov
2022-12-05 16:37 ` [PATCH v3 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Robert Foss
10 siblings, 1 reply; 31+ messages in thread
From: Robert Foss @ 2022-12-05 16:37 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
robert.foss, loic.poulain, swboyd, quic_vpolimer, vkoul,
dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
Enable the display subsystem and the dsi0 output for
the sm8350-hdk board.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index e6deb08c6da0..39462c659c58 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -213,10 +213,32 @@ &cdsp {
firmware-name = "qcom/sm8350/cdsp.mbn";
};
+&dispcc {
+ status = "okay";
+};
+
+&dsi0 {
+ vdda-supply = <&vreg_l6b_1p2>;
+ status = "okay";
+};
+
+&dsi0_phy {
+ vdds-supply = <&vreg_l5b_0p88>;
+ status = "okay";
+};
+
&gpi_dma1 {
status = "okay";
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_mdp {
+ status = "okay";
+};
+
&mpss {
status = "okay";
firmware-name = "qcom/sm8350/modem.mbn";
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
2022-12-05 16:37 [PATCH v3 00/11] Enable Display for SM8350 Robert Foss
` (9 preceding siblings ...)
2022-12-05 16:37 ` [PATCH v3 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes Robert Foss
@ 2022-12-05 16:37 ` Robert Foss
2022-12-05 16:47 ` Krzysztof Kozlowski
10 siblings, 1 reply; 31+ messages in thread
From: Robert Foss @ 2022-12-05 16:37 UTC (permalink / raw)
To: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
robert.foss, loic.poulain, swboyd, quic_vpolimer, vkoul,
dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
In order to toggle the board to enable the HDMI output,
switch #7 & #8 on the rightmost multi-switch package have
to be toggled to On.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 105 ++++++++++++++++++++++++
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 39462c659c58..3aa4ca8271e5 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -20,6 +20,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@@ -29,6 +40,31 @@ vph_pwr: vph-pwr-regulator {
regulator-always-on;
regulator-boot-on;
};
+
+ lt9611_1v2: lt9611-1v2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ vin-supply = <&vph_pwr>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ lt9611_3v3: lt9611-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_3V3";
+
+ vin-supply = <&vreg_bob>;
+ gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&adsp {
@@ -220,6 +256,15 @@ &dispcc {
&dsi0 {
vdda-supply = <&vreg_l6b_1p2>;
status = "okay";
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
};
&dsi0_phy {
@@ -231,6 +276,46 @@ &gpi_dma1 {
status = "okay";
};
+&i2c15 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_state>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
&mdss {
status = "okay";
};
@@ -248,6 +333,10 @@ &qupv3_id_0 {
status = "okay";
};
+&qupv3_id_2 {
+ status = "okay";
+};
+
&slpi {
status = "okay";
firmware-name = "qcom/sm8350/slpi.mbn";
@@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state {
drive-strength = <2>;
output-low;
};
+
+ lt9611_state: lt9611-state {
+ lt9611_rst_pin {
+ pins = "gpio48";
+ function = "normal";
+
+ output-high;
+ input-disable;
+ };
+
+ lt9611_irq_pin {
+ pins = "gpio50";
+ function = "gpio";
+ bias-disable;
+ };
+ };
};
--
2.34.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog
2022-12-05 16:37 ` [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog Robert Foss
@ 2022-12-05 16:43 ` Konrad Dybcio
2022-12-07 23:39 ` Dmitry Baryshkov
2022-12-07 23:42 ` Abhinav Kumar
2 siblings, 0 replies; 31+ messages in thread
From: Konrad Dybcio @ 2022-12-05 16:43 UTC (permalink / raw)
To: Robert Foss, robdclark, quic_abhinavk, dmitry.baryshkov, sean,
airlied, daniel, robh+dt, krzysztof.kozlowski+dt, agross,
bjorn.andersson, quic_kalyant, angelogioacchino.delregno,
loic.poulain, swboyd, quic_vpolimer, vkoul, dianders,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jonathan Marek, vinod.koul, quic_jesszhan, andersson
On 05/12/2022 17:37, Robert Foss wrote:
> Add compatibility for SM8350 display subsystem, including
> required entries in DPU hw catalog.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 196 ++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> 2 files changed, 197 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 4dac90ee5b8a..ba26af73be53 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -112,6 +112,15 @@
> BIT(MDP_INTF3_INTR) | \
> BIT(MDP_INTF4_INTR))
>
> +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_7xxx_INTR) | \
> + BIT(MDP_INTF1_7xxx_INTR) | \
> + BIT(MDP_INTF2_7xxx_INTR) | \
> + BIT(MDP_INTF3_7xxx_INTR) | \
> + 0)
> +
> #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> BIT(MDP_SSPP_TOP0_INTR2) | \
> BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> @@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> };
>
> +static const struct dpu_caps sm8350_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0xb,
> + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> + .ubwc_version = DPU_HW_UBWC_VER_40,
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .has_3d_merge = true,
> + .max_linewidth = 4096,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> static const struct dpu_caps sm8450_dpu_caps = {
> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> .max_mixer_blendstages = 0xb,
> @@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> },
> };
>
> +static const struct dpu_mdp_cfg sm8350_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> + .reg_off = 0x2ac, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> + .reg_off = 0x2b4, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> + .reg_off = 0x2bc, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> + .reg_off = 0x2c4, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> + .reg_off = 0x2ac, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> + .reg_off = 0x2b4, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> + .reg_off = 0x2bc, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> + .reg_off = 0x2c4, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> + .reg_off = 0x2bc, .bit_off = 20},
> + },
> +};
> +
> static const struct dpu_mdp_cfg sm8450_mdp[] = {
> {
> .name = "top_0", .id = MDP_TOP,
> @@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
> },
> };
>
> +static const struct dpu_ctl_cfg sm8350_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x15000, .len = 0x1e8,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> + {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x16000, .len = 0x1e8,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + },
> + {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x17000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + },
> + {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x18000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + },
> + {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x19000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + },
> + {
> + .name = "ctl_5", .id = CTL_5,
> + .base = 0x1a000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> + },
> +};
> +
> static const struct dpu_ctl_cfg sm8450_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> @@ -1294,6 +1383,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
> -1),
> };
>
> +static const struct dpu_pingpong_cfg sm8350_pp[] = {
> + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> + -1),
> + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> + -1),
> +};
> +
> static struct dpu_pingpong_cfg qcm2290_pp[] = {
> PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> @@ -1345,6 +1455,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
> MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
> };
>
> +static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
> + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
> +};
> +
> static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
> MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> @@ -1376,6 +1492,12 @@ static struct dpu_dsc_cfg sdm845_dsc[] = {
> DSC_BLK("dsc_3", DSC_3, 0x80c00),
> };
>
> +static struct dpu_dsc_cfg sm8350_dsc[] = {
> + DSC_BLK("dsc_0", DSC_0, 0x80000),
> + DSC_BLK("dsc_1", DSC_1, 0x81000),
> + DSC_BLK("dsc_2", DSC_2, 0x82000),
> +};
> +
> /*************************************************************
> * INTF sub blocks config
> *************************************************************/
> @@ -1423,6 +1545,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
> INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> };
>
> +static const struct dpu_intf_cfg sm8350_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> +};
> +
> static const struct dpu_intf_cfg sc8180x_intf[] = {
> INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> @@ -1558,6 +1687,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = {
> .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
> };
>
> +static const struct dpu_reg_dma_cfg sm8350_regdma = {
> + .base = 0x400,
> + .version = 0x00020000,
> + .trigger_sel_off = 0x119c,
> + .xin_id = 7,
> + .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
> +};
> +
> static const struct dpu_reg_dma_cfg sm8450_regdma = {
> .base = 0x0,
> .version = 0x00020000,
> @@ -1899,6 +2036,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
> .bw_inefficiency_factor = 120,
> };
>
> +static const struct dpu_perf_cfg sm8350_perf_data = {
> + .max_bw_low = 11800000,
> + .max_bw_high = 15500000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0,
> + .min_dram_ib = 800000,
> + .min_prefill_lines = 40,
> + /* FIXME: lut tables */
> + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
> + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sc7180_qos_linear),
> + .entries = sc7180_qos_linear
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
> + .entries = sc7180_qos_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + /* TODO: macrotile-qseed is different from macrotile */
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> static const struct dpu_perf_cfg qcm2290_perf_data = {
> .max_bw_low = 2700000,
> .max_bw_high = 2700000,
> @@ -2075,6 +2242,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
> .mdss_irqs = IRQ_SM8250_MASK,
> };
>
> +static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
> + .caps = &sm8350_dpu_caps,
> + .mdp_count = ARRAY_SIZE(sm8350_mdp),
> + .mdp = sm8350_mdp,
> + .ctl_count = ARRAY_SIZE(sm8350_ctl),
> + .ctl = sm8350_ctl,
> + .sspp_count = ARRAY_SIZE(sm8250_sspp),
> + .sspp = sm8250_sspp,
> + .mixer_count = ARRAY_SIZE(sm8150_lm),
> + .mixer = sm8150_lm,
> + .dspp_count = ARRAY_SIZE(sm8150_dspp),
> + .dspp = sm8150_dspp,
> + .pingpong_count = ARRAY_SIZE(sm8350_pp),
> + .pingpong = sm8350_pp,
> + .dsc_count = ARRAY_SIZE(sm8350_dsc),
> + .dsc = sm8350_dsc,
> + .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
> + .merge_3d = sm8350_merge_3d,
> + .intf_count = ARRAY_SIZE(sm8350_intf),
> + .intf = sm8350_intf,
> + .vbif_count = ARRAY_SIZE(sdm845_vbif),
> + .vbif = sdm845_vbif,
> + .reg_dma_count = 1,
> + .dma_cfg = &sm8250_regdma,
> + .perf = &sm8350_perf_data,
> + .mdss_irqs = IRQ_SM8350_MASK,
> +};
> +
> static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
> .caps = &sm8450_dpu_caps,
> .mdp_count = ARRAY_SIZE(sm8450_mdp),
> @@ -2158,6 +2353,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
> { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
> { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
> { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
> + { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
> { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
> { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 664c4876f44a..5335123a0289 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -45,6 +45,7 @@
> #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
> #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
> #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
> +#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
> #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
> #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
2022-12-05 16:37 ` [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes Robert Foss
@ 2022-12-05 16:43 ` Dmitry Baryshkov
2022-12-05 16:46 ` Krzysztof Kozlowski
2022-12-05 16:49 ` Konrad Dybcio
2 siblings, 0 replies; 31+ messages in thread
From: Dmitry Baryshkov @ 2022-12-05 16:43 UTC (permalink / raw)
To: Robert Foss, robdclark, quic_abhinavk, sean, airlied, daniel,
robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
loic.poulain, swboyd, quic_vpolimer, vkoul, dianders,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jonathan Marek, vinod.koul, quic_jesszhan, andersson
On 05/12/2022 18:37, Robert Foss wrote:
> Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
> nodes the display subsystem is configured to support
> one DSI output.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++++++++++++++++++++++++++-
> 1 file changed, 195 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 434f8e8b12c1..fb1c616c5e89 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -3,6 +3,7 @@
> * Copyright (c) 2020, Linaro Limited
> */
>
> +#include <dt-bindings/interconnect/qcom,sm8350.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a800000 {
> };
> };
>
> + mdss: mdss@ae00000 {
display-sybsystem@
I also had this issue in sm8450.dtsi (and I'm going to fix it in the
next revision).
> + compatible = "qcom,sm8350-mdss";
> + reg = <0 0x0ae00000 0 0x1000>;
> + reg-names = "mdss";
> +
> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> + power-domains = <&dispcc MDSS_GDSC>;
> + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "bus", "nrt_bus", "core";
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu 0x820 0x402>;
> +
> + status = "disabled";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + mdss_mdp: display-controller@ae01000 {
> + compatible = "qcom,sm8350-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb0000 0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> + };
> + };
> +
> + dsi0: dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&dsi0_phy 0>,
> + <&dsi0_phy 1>;
> +
> + operating-points-v2 = <&dsi_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + phys = <&dsi0_phy>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> +
> + mdp_opp_table: opp-table {
The mdp (dpu?) opp table belongs to the display-controller node.
> + compatible = "operating-points-v2";
> +
> + /* TODO: opp-200000000 should work with
> + * &rpmhpd_opp_low_svs, but one some of
> + * sm8350_hdk boards reboot using this
> + * opp.
> + */
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
I have been changing the dsi's opp table, not this one.
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-345000000 {
> + opp-hz = /bits/ 64 <345000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-460000000 {
> + opp-hz = /bits/ 64 <460000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + dsi0_phy: phy@ae94400 {
> + compatible = "qcom,dsi-phy-5nm-8350";
> + reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94900 0 0x260>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> +
> + dsi_opp_table: dsi-opp-table {
And this table should go to dsi node.
> + compatible = "operating-points-v2";
> +
> + opp-187500000 {
> + opp-hz = /bits/ 64 <187500000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-358000000 {
> + opp-hz = /bits/ 64 <358000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> + };
> + };
> + };
> +
> dispcc: clock-controller@af00000 {
> compatible = "qcom,sm8350-dispcc";
> reg = <0 0x0af00000 0 0x10000>;
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> - <0>,
> - <0>,
> - <0>,
> - <0>,
> + <&dsi0_phy 0>, <&dsi0_phy 1>,
> + <0>, <0>,
Let's probably add both DSI controllers and DSI PHYs. It's fine if you
can not verify the second one for real.
> <0>,
> <0>;
> clock-names = "bi_tcxo",
> @@ -2558,6 +2748,7 @@ dispcc: clock-controller@af00000 {
> #power-domain-cells = <1>;
>
> power-domains = <&rpmhpd SM8350_MMCX>;
> + required-opps = <&rpmhpd_opp_low_svs>;
As it's not a turbo level anymore, can we drop it completely?
> };
>
> adsp: remoteproc@17300000 {
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 05/11] drm/msm: Add support for SM8350
2022-12-05 16:37 ` [PATCH v3 05/11] drm/msm: " Robert Foss
@ 2022-12-05 16:43 ` Konrad Dybcio
2022-12-07 23:50 ` Dmitry Baryshkov
1 sibling, 0 replies; 31+ messages in thread
From: Konrad Dybcio @ 2022-12-05 16:43 UTC (permalink / raw)
To: Robert Foss, robdclark, quic_abhinavk, dmitry.baryshkov, sean,
airlied, daniel, robh+dt, krzysztof.kozlowski+dt, agross,
bjorn.andersson, quic_kalyant, angelogioacchino.delregno,
loic.poulain, swboyd, quic_vpolimer, vkoul, dianders,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jonathan Marek, vinod.koul, quic_jesszhan, andersson
On 05/12/2022 17:37, Robert Foss wrote:
> Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
> subsystem unit used on Qualcomm SM8350 platform.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/gpu/drm/msm/msm_mdss.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index a2264fb517a1..39746b972cdd 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
> /* UBWC_2_0 */
> msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
> break;
> + case DPU_HW_VER_700:
> + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1);
> + break;
> case DPU_HW_VER_720:
> msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
> break;
> @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8180x-mdss" },
> { .compatible = "qcom,sm8150-mdss" },
> { .compatible = "qcom,sm8250-mdss" },
> + { .compatible = "qcom,sm8350-mdss" },
> { .compatible = "qcom,sm8450-mdss" },
> {}
> };
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
2022-12-05 16:37 ` [PATCH v3 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes Robert Foss
@ 2022-12-05 16:44 ` Dmitry Baryshkov
2022-12-19 16:11 ` Robert Foss
0 siblings, 1 reply; 31+ messages in thread
From: Dmitry Baryshkov @ 2022-12-05 16:44 UTC (permalink / raw)
To: Robert Foss, robdclark, quic_abhinavk, sean, airlied, daniel,
robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
loic.poulain, swboyd, quic_vpolimer, vkoul, dianders,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jonathan Marek, vinod.koul, quic_jesszhan, andersson
On 05/12/2022 18:37, Robert Foss wrote:
> Enable the display subsystem and the dsi0 output for
> the sm8350-hdk board.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> index e6deb08c6da0..39462c659c58 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> @@ -213,10 +213,32 @@ &cdsp {
> firmware-name = "qcom/sm8350/cdsp.mbn";
> };
>
> +&dispcc {
> + status = "okay";
> +};
> +
> +&dsi0 {
Bjorn suggested using mdss_dsi0 / mdss_dsi0_phy labels for DSI host and
PHY, as it allows us to group them nicely. WDYT?
> + vdda-supply = <&vreg_l6b_1p2>;
> + status = "okay";
> +};
> +
> +&dsi0_phy {
> + vdds-supply = <&vreg_l5b_0p88>;
> + status = "okay";
> +};
> +
> &gpi_dma1 {
> status = "okay";
> };
>
> +&mdss {
> + status = "okay";
> +};
> +
> +&mdss_mdp {
> + status = "okay";
> +};
> +
> &mpss {
> status = "okay";
> firmware-name = "qcom/sm8350/modem.mbn";
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
2022-12-05 16:37 ` [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes Robert Foss
2022-12-05 16:43 ` Dmitry Baryshkov
@ 2022-12-05 16:46 ` Krzysztof Kozlowski
2022-12-05 16:49 ` Konrad Dybcio
2 siblings, 0 replies; 31+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-05 16:46 UTC (permalink / raw)
To: Robert Foss, robdclark, quic_abhinavk, dmitry.baryshkov, sean,
airlied, daniel, robh+dt, krzysztof.kozlowski+dt, agross,
bjorn.andersson, konrad.dybcio, quic_kalyant,
angelogioacchino.delregno, loic.poulain, swboyd, quic_vpolimer,
vkoul, dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
On 05/12/2022 17:37, Robert Foss wrote:
> Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
> nodes the display subsystem is configured to support
> one DSI output.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++++++++++++++++++++++++++-
> 1 file changed, 195 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 434f8e8b12c1..fb1c616c5e89 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -3,6 +3,7 @@
> * Copyright (c) 2020, Linaro Limited
> */
>
> +#include <dt-bindings/interconnect/qcom,sm8350.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a800000 {
> };
> };
>
> + mdss: mdss@ae00000 {
Based on bindings: display-subsystem
> + compatible = "qcom,sm8350-mdss";
> + reg = <0 0x0ae00000 0 0x1000>;
> + reg-names = "mdss";
> +
> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> + power-domains = <&dispcc MDSS_GDSC>;
> + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "bus", "nrt_bus", "core";
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu 0x820 0x402>;
> +
> + status = "disabled";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + mdss_mdp: display-controller@ae01000 {
> + compatible = "qcom,sm8350-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb0000 0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> + };
> + };
> +
> + dsi0: dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&dsi0_phy 0>,
> + <&dsi0_phy 1>;
> +
> + operating-points-v2 = <&dsi_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + phys = <&dsi0_phy>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> +
> + mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + /* TODO: opp-200000000 should work with
> + * &rpmhpd_opp_low_svs, but one some of
> + * sm8350_hdk boards reboot using this
> + * opp.
> + */
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-345000000 {
> + opp-hz = /bits/ 64 <345000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-460000000 {
> + opp-hz = /bits/ 64 <460000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + dsi0_phy: phy@ae94400 {
> + compatible = "qcom,dsi-phy-5nm-8350";
> + reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94900 0 0x260>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> +
> + dsi_opp_table: dsi-opp-table {
node name: opp-table
> + compatible = "operating-points-v2";
> +
> + opp-187500000 {
> + opp-hz = /bits/ 64 <187500000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-358000000 {
> + opp-hz = /bits/ 64 <358000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> + };
> + };
> + };
> +
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
2022-12-05 16:37 ` [PATCH v3 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Robert Foss
@ 2022-12-05 16:47 ` Krzysztof Kozlowski
2022-12-28 8:26 ` Robert Foss
0 siblings, 1 reply; 31+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-05 16:47 UTC (permalink / raw)
To: Robert Foss, robdclark, quic_abhinavk, dmitry.baryshkov, sean,
airlied, daniel, robh+dt, krzysztof.kozlowski+dt, agross,
bjorn.andersson, konrad.dybcio, quic_kalyant,
angelogioacchino.delregno, loic.poulain, swboyd, quic_vpolimer,
vkoul, dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
On 05/12/2022 17:37, Robert Foss wrote:
> The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
>
> In order to toggle the board to enable the HDMI output,
> switch #7 & #8 on the rightmost multi-switch package have
> to be toggled to On.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
Thank you for your patch. There is something to discuss/improve.
> +
> &slpi {
> status = "okay";
> firmware-name = "qcom/sm8350/slpi.mbn";
> @@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state {
> drive-strength = <2>;
> output-low;
> };
> +
> + lt9611_state: lt9611-state {
> + lt9611_rst_pin {
No underscores in node names.
> + pins = "gpio48";
> + function = "normal";
> +
> + output-high;
> + input-disable;
> + };
> +
> + lt9611_irq_pin {
Ditto
> + pins = "gpio50";
> + function = "gpio";
> + bias-disable;
> + };
> + };
> };
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
2022-12-05 16:37 ` [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes Robert Foss
2022-12-05 16:43 ` Dmitry Baryshkov
2022-12-05 16:46 ` Krzysztof Kozlowski
@ 2022-12-05 16:49 ` Konrad Dybcio
2 siblings, 0 replies; 31+ messages in thread
From: Konrad Dybcio @ 2022-12-05 16:49 UTC (permalink / raw)
To: Robert Foss, robdclark, quic_abhinavk, dmitry.baryshkov, sean,
airlied, daniel, robh+dt, krzysztof.kozlowski+dt, agross,
bjorn.andersson, quic_kalyant, angelogioacchino.delregno,
loic.poulain, swboyd, quic_vpolimer, vkoul, dianders,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jonathan Marek, vinod.koul, quic_jesszhan, andersson
On 05/12/2022 17:37, Robert Foss wrote:
> Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
> nodes the display subsystem is configured to support
> one DSI output.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++++++++++++++++++++++++++-
> 1 file changed, 195 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 434f8e8b12c1..fb1c616c5e89 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -3,6 +3,7 @@
> * Copyright (c) 2020, Linaro Limited
> */
>
> +#include <dt-bindings/interconnect/qcom,sm8350.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a800000 {
> };
> };
>
> + mdss: mdss@ae00000 {
> + compatible = "qcom,sm8350-mdss";
> + reg = <0 0x0ae00000 0 0x1000>;
> + reg-names = "mdss";
> +
> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> + power-domains = <&dispcc MDSS_GDSC>;
> + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "bus", "nrt_bus", "core";
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu 0x820 0x402>;
> +
> + status = "disabled";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + mdss_mdp: display-controller@ae01000 {
> + compatible = "qcom,sm8350-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb0000 0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> + };
> + };
> +
> + dsi0: dsi@ae94000 {
With the 8280 patchset [1], it was decided that mdss nodes should now
have a mdss_ prefix in their labels, to keep them near each other when
referencing them in device DTSes.
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&dsi0_phy 0>,
> + <&dsi0_phy 1>;
> +
> + operating-points-v2 = <&dsi_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + phys = <&dsi0_phy>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> +
> + mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + /* TODO: opp-200000000 should work with
/*
* TODO:
and the wrapping looks rather weird.. or is that my email client?
Other than that, lgtm!
Konrad
[1]
https://lore.kernel.org/linux-arm-msm/20221130200739.ube7hvobythkbhuy@builder.lan/T/#m93e15b290b40c2d2c2ec6f639135ffa38882d0b2
> + * &rpmhpd_opp_low_svs, but one some of
> + * sm8350_hdk boards reboot using this
> + * opp.
> + */
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-345000000 {
> + opp-hz = /bits/ 64 <345000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-460000000 {
> + opp-hz = /bits/ 64 <460000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + dsi0_phy: phy@ae94400 {
> + compatible = "qcom,dsi-phy-5nm-8350";
> + reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94900 0 0x260>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> +
> + dsi_opp_table: dsi-opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-187500000 {
> + opp-hz = /bits/ 64 <187500000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-358000000 {
> + opp-hz = /bits/ 64 <358000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> + };
> + };
> + };
> +
> dispcc: clock-controller@af00000 {
> compatible = "qcom,sm8350-dispcc";
> reg = <0 0x0af00000 0 0x10000>;
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> - <0>,
> - <0>,
> - <0>,
> - <0>,
> + <&dsi0_phy 0>, <&dsi0_phy 1>,
> + <0>, <0>,
> <0>,
> <0>;
> clock-names = "bi_tcxo",
> @@ -2558,6 +2748,7 @@ dispcc: clock-controller@af00000 {
> #power-domain-cells = <1>;
>
> power-domains = <&rpmhpd SM8350_MMCX>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> };
>
> adsp: remoteproc@17300000 {
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells
2022-12-05 16:37 ` [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells Robert Foss
@ 2022-12-05 19:19 ` Georgi Djakov
2022-12-19 16:15 ` Robert Foss
0 siblings, 1 reply; 31+ messages in thread
From: Georgi Djakov @ 2022-12-05 19:19 UTC (permalink / raw)
To: Robert Foss, robdclark, quic_abhinavk, dmitry.baryshkov, sean,
airlied, daniel, robh+dt, krzysztof.kozlowski+dt, agross,
bjorn.andersson, konrad.dybcio, quic_kalyant,
angelogioacchino.delregno, loic.poulain, swboyd, quic_vpolimer,
vkoul, dianders, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Jonathan Marek, vinod.koul, quic_jesszhan,
andersson
Cc: Konrad Dybcio
Hi Robert,
On 5.12.22 18:37, Robert Foss wrote:
> Use two interconnect cells in order to optionally
> support a path tag.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 805d53d91952..434f8e8b12c1 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -1543,56 +1543,56 @@ apps_smmu: iommu@15000000 {
> config_noc: interconnect@1500000 {
> compatible = "qcom,sm8350-config-noc";
> reg = <0 0x01500000 0 0xa580>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> mc_virt: interconnect@1580000 {
> compatible = "qcom,sm8350-mc-virt";
> reg = <0 0x01580000 0 0x1000>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
[..]
> @@ -1620,8 +1620,8 @@ ipa: ipa@1e40000 {
> clocks = <&rpmhcc RPMH_IPA_CLK>;
> clock-names = "core";
>
> - interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
> - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
> + interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
> interconnect-names = "memory",
> "config";
>
> @@ -1661,7 +1661,7 @@ mpss: remoteproc@4080000 {
> <&rpmhpd SM8350_MSS>;
> power-domain-names = "cx", "mss";
>
> - interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
> + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1 0>;
The second cell for the first endpoint is missing, so this should be:
interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
Thanks,
Georgi
>
> memory-region = <&pil_modem_mem>;
>
> @@ -2239,7 +2239,7 @@ cdsp: remoteproc@98900000 {
> <&rpmhpd SM8350_MXC>;
> power-domain-names = "cx", "mxc";
>
> - interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
> + interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
>
> memory-region = <&pil_cdsp_mem>;
>
> @@ -2421,14 +2421,14 @@ usb_2_ssphy: phy@88ebe00 {
> dc_noc: interconnect@90c0000 {
> compatible = "qcom,sm8350-dc-noc";
> reg = <0 0x090c0000 0 0x4200>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> gem_noc: interconnect@9100000 {
> compatible = "qcom,sm8350-gem-noc";
> reg = <0 0x09100000 0 0xb4000>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 02/11] dt-bindings: display: msm: Add qcom,sm8350-mdss binding
2022-12-05 16:37 ` [PATCH v3 02/11] dt-bindings: display: msm: Add qcom,sm8350-mdss binding Robert Foss
@ 2022-12-05 21:08 ` Rob Herring
0 siblings, 0 replies; 31+ messages in thread
From: Rob Herring @ 2022-12-05 21:08 UTC (permalink / raw)
To: Robert Foss
Cc: freedreno, robdclark, devicetree, sean, quic_jesszhan,
loic.poulain, konrad.dybcio, airlied, agross,
angelogioacchino.delregno, dmitry.baryshkov, andersson,
bjorn.andersson, vinod.koul, vkoul, dianders, daniel,
linux-kernel, swboyd, dri-devel, linux-arm-msm, robh+dt,
quic_abhinavk, quic_vpolimer, krzysztof.kozlowski+dt,
quic_kalyant, Jonathan Marek
On Mon, 05 Dec 2022 17:37:45 +0100, Robert Foss wrote:
> Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema for MDSS device
> tree bindings
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> .../display/msm/qcom,sm8350-mdss.yaml | 221 ++++++++++++++++++
> 1 file changed, 221 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog
2022-12-05 16:37 ` [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog Robert Foss
2022-12-05 16:43 ` Konrad Dybcio
@ 2022-12-07 23:39 ` Dmitry Baryshkov
2022-12-07 23:42 ` Abhinav Kumar
2 siblings, 0 replies; 31+ messages in thread
From: Dmitry Baryshkov @ 2022-12-07 23:39 UTC (permalink / raw)
To: Robert Foss, robdclark, quic_abhinavk, sean, airlied, daniel,
robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
loic.poulain, swboyd, quic_vpolimer, vkoul, dianders,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jonathan Marek, vinod.koul, quic_jesszhan, andersson
On 05/12/2022 18:37, Robert Foss wrote:
> Add compatibility for SM8350 display subsystem, including
> required entries in DPU hw catalog.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Minor nit below.
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 196 ++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> 2 files changed, 197 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 4dac90ee5b8a..ba26af73be53 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -112,6 +112,15 @@
> BIT(MDP_INTF3_INTR) | \
> BIT(MDP_INTF4_INTR))
>
> +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_7xxx_INTR) | \
> + BIT(MDP_INTF1_7xxx_INTR) | \
> + BIT(MDP_INTF2_7xxx_INTR) | \
> + BIT(MDP_INTF3_7xxx_INTR) | \
> + 0)
> +
> #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> BIT(MDP_SSPP_TOP0_INTR2) | \
> BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> @@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> };
>
> +static const struct dpu_caps sm8350_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0xb,
> + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> + .ubwc_version = DPU_HW_UBWC_VER_40,
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .has_3d_merge = true,
> + .max_linewidth = 4096,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> static const struct dpu_caps sm8450_dpu_caps = {
> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> .max_mixer_blendstages = 0xb,
> @@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> },
> };
>
> +static const struct dpu_mdp_cfg sm8350_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
Missing ubwc_swizzle. I'll probably fix it as a followup or when
applying the patch.
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> + .reg_off = 0x2ac, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> + .reg_off = 0x2b4, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> + .reg_off = 0x2bc, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> + .reg_off = 0x2c4, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> + .reg_off = 0x2ac, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> + .reg_off = 0x2b4, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> + .reg_off = 0x2bc, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> + .reg_off = 0x2c4, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> + .reg_off = 0x2bc, .bit_off = 20},
> + },
> +};
> +
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 04/11] drm/msm/dpu: Add support for SM8350
2022-12-05 16:37 ` [PATCH v3 04/11] drm/msm/dpu: Add support for SM8350 Robert Foss
@ 2022-12-07 23:40 ` Dmitry Baryshkov
2022-12-07 23:47 ` Abhinav Kumar
1 sibling, 0 replies; 31+ messages in thread
From: Dmitry Baryshkov @ 2022-12-07 23:40 UTC (permalink / raw)
To: Robert Foss, robdclark, quic_abhinavk, sean, airlied, daniel,
robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
loic.poulain, swboyd, quic_vpolimer, vkoul, dianders,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jonathan Marek, vinod.koul, quic_jesszhan, andersson
On 05/12/2022 18:37, Robert Foss wrote:
> Add compatibles string, "qcom,sm8350-dpu", for the display processing unit
> used on Qualcomm SM8350 platform.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog
2022-12-05 16:37 ` [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog Robert Foss
2022-12-05 16:43 ` Konrad Dybcio
2022-12-07 23:39 ` Dmitry Baryshkov
@ 2022-12-07 23:42 ` Abhinav Kumar
2022-12-28 9:27 ` Robert Foss
2 siblings, 1 reply; 31+ messages in thread
From: Abhinav Kumar @ 2022-12-07 23:42 UTC (permalink / raw)
To: Robert Foss, robdclark, dmitry.baryshkov, sean, airlied, daniel,
robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
loic.poulain, swboyd, quic_vpolimer, vkoul, dianders,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jonathan Marek, vinod.koul, quic_jesszhan, andersson
On 12/5/2022 8:37 AM, Robert Foss wrote:
> Add compatibility for SM8350 display subsystem, including
> required entries in DPU hw catalog.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 196 ++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> 2 files changed, 197 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 4dac90ee5b8a..ba26af73be53 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -112,6 +112,15 @@
> BIT(MDP_INTF3_INTR) | \
> BIT(MDP_INTF4_INTR))
>
> +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_7xxx_INTR) | \
> + BIT(MDP_INTF1_7xxx_INTR) | \
> + BIT(MDP_INTF2_7xxx_INTR) | \
> + BIT(MDP_INTF3_7xxx_INTR) | \
> + 0)
> +
> #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> BIT(MDP_SSPP_TOP0_INTR2) | \
> BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> @@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> };
>
> +static const struct dpu_caps sm8350_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0xb,
> + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> + .ubwc_version = DPU_HW_UBWC_VER_40,
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .has_3d_merge = true,
> + .max_linewidth = 4096,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> static const struct dpu_caps sm8450_dpu_caps = {
> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> .max_mixer_blendstages = 0xb,
> @@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> },
> };
>
> +static const struct dpu_mdp_cfg sm8350_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> + .reg_off = 0x2ac, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> + .reg_off = 0x2b4, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> + .reg_off = 0x2bc, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> + .reg_off = 0x2c4, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> + .reg_off = 0x2ac, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> + .reg_off = 0x2b4, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> + .reg_off = 0x2bc, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> + .reg_off = 0x2c4, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> + .reg_off = 0x2bc, .bit_off = 20},
> + },
> +};
> +
> static const struct dpu_mdp_cfg sm8450_mdp[] = {
> {
> .name = "top_0", .id = MDP_TOP,
> @@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
> },
> };
>
> +static const struct dpu_ctl_cfg sm8350_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x15000, .len = 0x1e8,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> + {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x16000, .len = 0x1e8,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + },
> + {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x17000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + },
> + {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x18000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + },
> + {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x19000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + },
> + {
> + .name = "ctl_5", .id = CTL_5,
> + .base = 0x1a000, .len = 0x1e8,
> + .features = CTL_SC7280_MASK,
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> + },
> +};
> +
> static const struct dpu_ctl_cfg sm8450_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> @@ -1294,6 +1383,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
> -1),
> };
>
> +static const struct dpu_pingpong_cfg sm8350_pp[] = {
> + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> + -1),
> + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> + -1),
> +};
> +
> static struct dpu_pingpong_cfg qcm2290_pp[] = {
> PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> @@ -1345,6 +1455,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
> MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
> };
>
> +static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
> + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
> +};
> +
> static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
> MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> @@ -1376,6 +1492,12 @@ static struct dpu_dsc_cfg sdm845_dsc[] = {
> DSC_BLK("dsc_3", DSC_3, 0x80c00),
> };
>
> +static struct dpu_dsc_cfg sm8350_dsc[] = {
> + DSC_BLK("dsc_0", DSC_0, 0x80000),
> + DSC_BLK("dsc_1", DSC_1, 0x81000),
> + DSC_BLK("dsc_2", DSC_2, 0x82000),
> +};
I think this was copied over from sm8250, but this is not right.
sm8350 has only 2 DSC blocks not 3. So "dsc_2" is not there.
Thats a change from sm8250.
Please fix this.
> +
> /*************************************************************
> * INTF sub blocks config
> *************************************************************/
> @@ -1423,6 +1545,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
> INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> };
>
> +static const struct dpu_intf_cfg sm8350_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> +};
> +
> static const struct dpu_intf_cfg sc8180x_intf[] = {
> INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> @@ -1558,6 +1687,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = {
> .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
> };
>
> +static const struct dpu_reg_dma_cfg sm8350_regdma = {
> + .base = 0x400,
> + .version = 0x00020000,
> + .trigger_sel_off = 0x119c,
> + .xin_id = 7,
> + .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
> +};
> +
> static const struct dpu_reg_dma_cfg sm8450_regdma = {
> .base = 0x0,
> .version = 0x00020000,
> @@ -1899,6 +2036,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
> .bw_inefficiency_factor = 120,
> };
>
> +static const struct dpu_perf_cfg sm8350_perf_data = {
> + .max_bw_low = 11800000,
> + .max_bw_high = 15500000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0,
> + .min_dram_ib = 800000,
> + .min_prefill_lines = 40,
> + /* FIXME: lut tables */
> + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
> + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sc7180_qos_linear),
> + .entries = sc7180_qos_linear
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
> + .entries = sc7180_qos_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + /* TODO: macrotile-qseed is different from macrotile */
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> static const struct dpu_perf_cfg qcm2290_perf_data = {
> .max_bw_low = 2700000,
> .max_bw_high = 2700000,
> @@ -2075,6 +2242,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
> .mdss_irqs = IRQ_SM8250_MASK,
> };
>
> +static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
> + .caps = &sm8350_dpu_caps,
> + .mdp_count = ARRAY_SIZE(sm8350_mdp),
> + .mdp = sm8350_mdp,
> + .ctl_count = ARRAY_SIZE(sm8350_ctl),
> + .ctl = sm8350_ctl,
> + .sspp_count = ARRAY_SIZE(sm8250_sspp),
> + .sspp = sm8250_sspp,
> + .mixer_count = ARRAY_SIZE(sm8150_lm),
> + .mixer = sm8150_lm,
> + .dspp_count = ARRAY_SIZE(sm8150_dspp),
> + .dspp = sm8150_dspp,
> + .pingpong_count = ARRAY_SIZE(sm8350_pp),
> + .pingpong = sm8350_pp,
> + .dsc_count = ARRAY_SIZE(sm8350_dsc),
> + .dsc = sm8350_dsc,
> + .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
> + .merge_3d = sm8350_merge_3d,
> + .intf_count = ARRAY_SIZE(sm8350_intf),
> + .intf = sm8350_intf,
> + .vbif_count = ARRAY_SIZE(sdm845_vbif),
> + .vbif = sdm845_vbif,
> + .reg_dma_count = 1,
> + .dma_cfg = &sm8250_regdma,
> + .perf = &sm8350_perf_data,
> + .mdss_irqs = IRQ_SM8350_MASK,
> +};
> +
> static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
> .caps = &sm8450_dpu_caps,
> .mdp_count = ARRAY_SIZE(sm8450_mdp),
> @@ -2158,6 +2353,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
> { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
> { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
> { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
> + { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
> { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
> { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 664c4876f44a..5335123a0289 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -45,6 +45,7 @@
> #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
> #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
> #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
> +#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
> #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
> #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 04/11] drm/msm/dpu: Add support for SM8350
2022-12-05 16:37 ` [PATCH v3 04/11] drm/msm/dpu: Add support for SM8350 Robert Foss
2022-12-07 23:40 ` Dmitry Baryshkov
@ 2022-12-07 23:47 ` Abhinav Kumar
1 sibling, 0 replies; 31+ messages in thread
From: Abhinav Kumar @ 2022-12-07 23:47 UTC (permalink / raw)
To: Robert Foss, robdclark, dmitry.baryshkov, sean, airlied, daniel,
robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
loic.poulain, swboyd, quic_vpolimer, vkoul, dianders,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jonathan Marek, vinod.koul, quic_jesszhan, andersson
On 12/5/2022 8:37 AM, Robert Foss wrote:
> Add compatibles string, "qcom,sm8350-dpu", for the display processing unit
> used on Qualcomm SM8350 platform.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 9827914dc096..6048bfae0824 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1322,6 +1322,7 @@ static const struct of_device_id dpu_dt_match[] = {
> { .compatible = "qcom,sc8180x-dpu", },
> { .compatible = "qcom,sm8150-dpu", },
> { .compatible = "qcom,sm8250-dpu", },
> + { .compatible = "qcom,sm8350-dpu", },
> { .compatible = "qcom,sm8450-dpu", },
> {}
> };
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 05/11] drm/msm: Add support for SM8350
2022-12-05 16:37 ` [PATCH v3 05/11] drm/msm: " Robert Foss
2022-12-05 16:43 ` Konrad Dybcio
@ 2022-12-07 23:50 ` Dmitry Baryshkov
2022-12-19 16:18 ` Robert Foss
1 sibling, 1 reply; 31+ messages in thread
From: Dmitry Baryshkov @ 2022-12-07 23:50 UTC (permalink / raw)
To: Robert Foss, robdclark, quic_abhinavk, sean, airlied, daniel,
robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
loic.poulain, swboyd, quic_vpolimer, vkoul, dianders,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jonathan Marek, vinod.koul, quic_jesszhan, andersson
On 05/12/2022 18:37, Robert Foss wrote:
> Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
> subsystem unit used on Qualcomm SM8350 platform.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index a2264fb517a1..39746b972cdd 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
> /* UBWC_2_0 */
> msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
> break;
> + case DPU_HW_VER_700:
> + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1);
> + break;
Judging from the vendor kernel, the highest_rank_bit is 3, with usual
todo for 2 for LP_DDR4.
> case DPU_HW_VER_720:
> msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
> break;
> @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8180x-mdss" },
> { .compatible = "qcom,sm8150-mdss" },
> { .compatible = "qcom,sm8250-mdss" },
> + { .compatible = "qcom,sm8350-mdss" },
> { .compatible = "qcom,sm8450-mdss" },
> {}
> };
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
2022-12-05 16:44 ` Dmitry Baryshkov
@ 2022-12-19 16:11 ` Robert Foss
0 siblings, 0 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-19 16:11 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: robdclark, quic_abhinavk, sean, airlied, daniel, robh+dt,
krzysztof.kozlowski+dt, agross, bjorn.andersson, konrad.dybcio,
quic_kalyant, angelogioacchino.delregno, loic.poulain, swboyd,
quic_vpolimer, vkoul, dianders, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, Jonathan Marek, vinod.koul,
quic_jesszhan, andersson
On Mon, 5 Dec 2022 at 17:44, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 05/12/2022 18:37, Robert Foss wrote:
> > Enable the display subsystem and the dsi0 output for
> > the sm8350-hdk board.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > index e6deb08c6da0..39462c659c58 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > @@ -213,10 +213,32 @@ &cdsp {
> > firmware-name = "qcom/sm8350/cdsp.mbn";
> > };
> >
> > +&dispcc {
> > + status = "okay";
> > +};
> > +
> > +&dsi0 {
>
> Bjorn suggested using mdss_dsi0 / mdss_dsi0_phy labels for DSI host and
> PHY, as it allows us to group them nicely. WDYT?
Sounds quite reasonable, fixing it in dts/dtsi/binding.
>
> > + vdda-supply = <&vreg_l6b_1p2>;
> > + status = "okay";
> > +};
> > +
> > +&dsi0_phy {
> > + vdds-supply = <&vreg_l5b_0p88>;
> > + status = "okay";
> > +};
> > +
> > &gpi_dma1 {
> > status = "okay";
> > };
> >
> > +&mdss {
> > + status = "okay";
> > +};
> > +
> > +&mdss_mdp {
> > + status = "okay";
> > +};
> > +
> > &mpss {
> > status = "okay";
> > firmware-name = "qcom/sm8350/modem.mbn";
>
> --
> With best wishes
> Dmitry
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells
2022-12-05 19:19 ` Georgi Djakov
@ 2022-12-19 16:15 ` Robert Foss
0 siblings, 0 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-19 16:15 UTC (permalink / raw)
To: Georgi Djakov
Cc: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
loic.poulain, swboyd, quic_vpolimer, vkoul, dianders,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jonathan Marek, vinod.koul, quic_jesszhan, andersson,
Konrad Dybcio
On Mon, 5 Dec 2022 at 20:19, Georgi Djakov <djakov@kernel.org> wrote:
>
> Hi Robert,
>
> On 5.12.22 18:37, Robert Foss wrote:
> > Use two interconnect cells in order to optionally
> > support a path tag.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++++++++++++++--------------
> > 1 file changed, 14 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > index 805d53d91952..434f8e8b12c1 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > @@ -1543,56 +1543,56 @@ apps_smmu: iommu@15000000 {
> > config_noc: interconnect@1500000 {
> > compatible = "qcom,sm8350-config-noc";
> > reg = <0 0x01500000 0 0xa580>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > mc_virt: interconnect@1580000 {
> > compatible = "qcom,sm8350-mc-virt";
> > reg = <0 0x01580000 0 0x1000>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> [..]
> > @@ -1620,8 +1620,8 @@ ipa: ipa@1e40000 {
> > clocks = <&rpmhcc RPMH_IPA_CLK>;
> > clock-names = "core";
> >
> > - interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
> > - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
> > + interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
> > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
> > interconnect-names = "memory",
> > "config";
> >
> > @@ -1661,7 +1661,7 @@ mpss: remoteproc@4080000 {
> > <&rpmhpd SM8350_MSS>;
> > power-domain-names = "cx", "mss";
> >
> > - interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
> > + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1 0>;
>
> The second cell for the first endpoint is missing, so this should be:
> interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
Nice catch, thanks!
>
> Thanks,
> Georgi
>
> >
> > memory-region = <&pil_modem_mem>;
> >
> > @@ -2239,7 +2239,7 @@ cdsp: remoteproc@98900000 {
> > <&rpmhpd SM8350_MXC>;
> > power-domain-names = "cx", "mxc";
> >
> > - interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
> > + interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
> >
> > memory-region = <&pil_cdsp_mem>;
> >
> > @@ -2421,14 +2421,14 @@ usb_2_ssphy: phy@88ebe00 {
> > dc_noc: interconnect@90c0000 {
> > compatible = "qcom,sm8350-dc-noc";
> > reg = <0 0x090c0000 0 0x4200>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > gem_noc: interconnect@9100000 {
> > compatible = "qcom,sm8350-gem-noc";
> > reg = <0 0x09100000 0 0xb4000>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 05/11] drm/msm: Add support for SM8350
2022-12-07 23:50 ` Dmitry Baryshkov
@ 2022-12-19 16:18 ` Robert Foss
0 siblings, 0 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-19 16:18 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: robdclark, quic_abhinavk, sean, airlied, daniel, robh+dt,
krzysztof.kozlowski+dt, agross, bjorn.andersson, konrad.dybcio,
quic_kalyant, angelogioacchino.delregno, loic.poulain, swboyd,
quic_vpolimer, vkoul, dianders, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, Jonathan Marek, vinod.koul,
quic_jesszhan, andersson
On Thu, 8 Dec 2022 at 00:50, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 05/12/2022 18:37, Robert Foss wrote:
> > Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
> > subsystem unit used on Qualcomm SM8350 platform.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > ---
> > drivers/gpu/drm/msm/msm_mdss.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> > index a2264fb517a1..39746b972cdd 100644
> > --- a/drivers/gpu/drm/msm/msm_mdss.c
> > +++ b/drivers/gpu/drm/msm/msm_mdss.c
> > @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
> > /* UBWC_2_0 */
> > msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
> > break;
> > + case DPU_HW_VER_700:
> > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1);
> > + break;
>
> Judging from the vendor kernel, the highest_rank_bit is 3, with usual
> todo for 2 for LP_DDR4.
Thanks! Will fix.
>
> > case DPU_HW_VER_720:
> > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
> > break;
> > @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = {
> > { .compatible = "qcom,sc8180x-mdss" },
> > { .compatible = "qcom,sm8150-mdss" },
> > { .compatible = "qcom,sm8250-mdss" },
> > + { .compatible = "qcom,sm8350-mdss" },
> > { .compatible = "qcom,sm8450-mdss" },
> > {}
> > };
>
> --
> With best wishes
> Dmitry
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
2022-12-05 16:47 ` Krzysztof Kozlowski
@ 2022-12-28 8:26 ` Robert Foss
0 siblings, 0 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-28 8:26 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robdclark, quic_abhinavk, dmitry.baryshkov, sean, airlied,
daniel, robh+dt, krzysztof.kozlowski+dt, agross, bjorn.andersson,
konrad.dybcio, quic_kalyant, angelogioacchino.delregno,
loic.poulain, swboyd, quic_vpolimer, vkoul, dianders,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jonathan Marek, vinod.koul, quic_jesszhan, andersson
On Mon, 5 Dec 2022 at 17:47, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 05/12/2022 17:37, Robert Foss wrote:
> > The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
> >
> > In order to toggle the board to enable the HDMI output,
> > switch #7 & #8 on the rightmost multi-switch package have
> > to be toggled to On.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
>
> Thank you for your patch. There is something to discuss/improve.
>
> > +
> > &slpi {
> > status = "okay";
> > firmware-name = "qcom/sm8350/slpi.mbn";
> > @@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state {
> > drive-strength = <2>;
> > output-low;
> > };
> > +
> > + lt9611_state: lt9611-state {
> > + lt9611_rst_pin {
>
> No underscores in node names.
Ack
>
> > + pins = "gpio48";
> > + function = "normal";
> > +
> > + output-high;
> > + input-disable;
> > + };
> > +
> > + lt9611_irq_pin {
>
> Ditto
Ack
>
> > + pins = "gpio50";
> > + function = "gpio";
> > + bias-disable;
> > + };
> > + };
> > };
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog
2022-12-07 23:42 ` Abhinav Kumar
@ 2022-12-28 9:27 ` Robert Foss
0 siblings, 0 replies; 31+ messages in thread
From: Robert Foss @ 2022-12-28 9:27 UTC (permalink / raw)
To: Abhinav Kumar
Cc: robdclark, dmitry.baryshkov, sean, airlied, daniel, robh+dt,
krzysztof.kozlowski+dt, agross, bjorn.andersson, konrad.dybcio,
quic_kalyant, angelogioacchino.delregno, loic.poulain, swboyd,
quic_vpolimer, vkoul, dianders, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, Jonathan Marek, vinod.koul,
quic_jesszhan, andersson
On Thu, 8 Dec 2022 at 00:42, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/5/2022 8:37 AM, Robert Foss wrote:
> > Add compatibility for SM8350 display subsystem, including
> > required entries in DPU hw catalog.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > ---
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 196 ++++++++++++++++++
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> > 2 files changed, 197 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > index 4dac90ee5b8a..ba26af73be53 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > @@ -112,6 +112,15 @@
> > BIT(MDP_INTF3_INTR) | \
> > BIT(MDP_INTF4_INTR))
> >
> > +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> > + BIT(MDP_SSPP_TOP0_INTR2) | \
> > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > + BIT(MDP_INTF0_7xxx_INTR) | \
> > + BIT(MDP_INTF1_7xxx_INTR) | \
> > + BIT(MDP_INTF2_7xxx_INTR) | \
> > + BIT(MDP_INTF3_7xxx_INTR) | \
> > + 0)
> > +
> > #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> > BIT(MDP_SSPP_TOP0_INTR2) | \
> > BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > @@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
> > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > };
> >
> > +static const struct dpu_caps sm8350_dpu_caps = {
> > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .max_mixer_blendstages = 0xb,
> > + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
> > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> > + .ubwc_version = DPU_HW_UBWC_VER_40,
> > + .has_src_split = true,
> > + .has_dim_layer = true,
> > + .has_idle_pc = true,
> > + .has_3d_merge = true,
> > + .max_linewidth = 4096,
> > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > +};
> > +
> > static const struct dpu_caps sm8450_dpu_caps = {
> > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > .max_mixer_blendstages = 0xb,
> > @@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> > },
> > };
> >
> > +static const struct dpu_mdp_cfg sm8350_mdp[] = {
> > + {
> > + .name = "top_0", .id = MDP_TOP,
> > + .base = 0x0, .len = 0x494,
> > + .features = 0,
> > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> > + .reg_off = 0x2ac, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> > + .reg_off = 0x2b4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> > + .reg_off = 0x2bc, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> > + .reg_off = 0x2c4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> > + .reg_off = 0x2ac, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> > + .reg_off = 0x2b4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> > + .reg_off = 0x2bc, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> > + .reg_off = 0x2c4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> > + .reg_off = 0x2bc, .bit_off = 20},
> > + },
> > +};
> > +
> > static const struct dpu_mdp_cfg sm8450_mdp[] = {
> > {
> > .name = "top_0", .id = MDP_TOP,
> > @@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
> > },
> > };
> >
> > +static const struct dpu_ctl_cfg sm8350_ctl[] = {
> > + {
> > + .name = "ctl_0", .id = CTL_0,
> > + .base = 0x15000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> > + },
> > + {
> > + .name = "ctl_1", .id = CTL_1,
> > + .base = 0x16000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> > + },
> > + {
> > + .name = "ctl_2", .id = CTL_2,
> > + .base = 0x17000, .len = 0x1e8,
> > + .features = CTL_SC7280_MASK,
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> > + },
> > + {
> > + .name = "ctl_3", .id = CTL_3,
> > + .base = 0x18000, .len = 0x1e8,
> > + .features = CTL_SC7280_MASK,
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> > + },
> > + {
> > + .name = "ctl_4", .id = CTL_4,
> > + .base = 0x19000, .len = 0x1e8,
> > + .features = CTL_SC7280_MASK,
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> > + },
> > + {
> > + .name = "ctl_5", .id = CTL_5,
> > + .base = 0x1a000, .len = 0x1e8,
> > + .features = CTL_SC7280_MASK,
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> > + },
> > +};
> > +
> > static const struct dpu_ctl_cfg sm8450_ctl[] = {
> > {
> > .name = "ctl_0", .id = CTL_0,
> > @@ -1294,6 +1383,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
> > -1),
> > };
> >
> > +static const struct dpu_pingpong_cfg sm8350_pp[] = {
> > + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> > + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> > + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> > + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> > + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> > + -1),
> > + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> > + -1),
> > +};
> > +
> > static struct dpu_pingpong_cfg qcm2290_pp[] = {
> > PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
> > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> > @@ -1345,6 +1455,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
> > MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
> > };
> >
> > +static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
> > + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> > + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> > + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
> > +};
> > +
> > static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
> > MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> > MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> > @@ -1376,6 +1492,12 @@ static struct dpu_dsc_cfg sdm845_dsc[] = {
> > DSC_BLK("dsc_3", DSC_3, 0x80c00),
> > };
> >
> > +static struct dpu_dsc_cfg sm8350_dsc[] = {
> > + DSC_BLK("dsc_0", DSC_0, 0x80000),
> > + DSC_BLK("dsc_1", DSC_1, 0x81000),
> > + DSC_BLK("dsc_2", DSC_2, 0x82000),
> > +};
>
> I think this was copied over from sm8250, but this is not right.
>
> sm8350 has only 2 DSC blocks not 3. So "dsc_2" is not there.
>
> Thats a change from sm8250.
>
> Please fix this.
Ack
>
> > +
> > /*************************************************************
> > * INTF sub blocks config
> > *************************************************************/
> > @@ -1423,6 +1545,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
> > INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> > };
> >
> > +static const struct dpu_intf_cfg sm8350_intf[] = {
> > + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> > + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> > + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> > + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> > +};
> > +
> > static const struct dpu_intf_cfg sc8180x_intf[] = {
> > INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> > INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> > @@ -1558,6 +1687,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = {
> > .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
> > };
> >
> > +static const struct dpu_reg_dma_cfg sm8350_regdma = {
> > + .base = 0x400,
> > + .version = 0x00020000,
> > + .trigger_sel_off = 0x119c,
> > + .xin_id = 7,
> > + .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
> > +};
> > +
> > static const struct dpu_reg_dma_cfg sm8450_regdma = {
> > .base = 0x0,
> > .version = 0x00020000,
> > @@ -1899,6 +2036,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
> > .bw_inefficiency_factor = 120,
> > };
> >
> > +static const struct dpu_perf_cfg sm8350_perf_data = {
> > + .max_bw_low = 11800000,
> > + .max_bw_high = 15500000,
> > + .min_core_ib = 2500000,
> > + .min_llcc_ib = 0,
> > + .min_dram_ib = 800000,
> > + .min_prefill_lines = 40,
> > + /* FIXME: lut tables */
> > + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
> > + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
> > + .qos_lut_tbl = {
> > + {.nentry = ARRAY_SIZE(sc7180_qos_linear),
> > + .entries = sc7180_qos_linear
> > + },
> > + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
> > + .entries = sc7180_qos_macrotile
> > + },
> > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> > + .entries = sc7180_qos_nrt
> > + },
> > + /* TODO: macrotile-qseed is different from macrotile */
> > + },
> > + .cdp_cfg = {
> > + {.rd_enable = 1, .wr_enable = 1},
> > + {.rd_enable = 1, .wr_enable = 0}
> > + },
> > + .clk_inefficiency_factor = 105,
> > + .bw_inefficiency_factor = 120,
> > +};
> > +
> > static const struct dpu_perf_cfg qcm2290_perf_data = {
> > .max_bw_low = 2700000,
> > .max_bw_high = 2700000,
> > @@ -2075,6 +2242,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
> > .mdss_irqs = IRQ_SM8250_MASK,
> > };
> >
> > +static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
> > + .caps = &sm8350_dpu_caps,
> > + .mdp_count = ARRAY_SIZE(sm8350_mdp),
> > + .mdp = sm8350_mdp,
> > + .ctl_count = ARRAY_SIZE(sm8350_ctl),
> > + .ctl = sm8350_ctl,
> > + .sspp_count = ARRAY_SIZE(sm8250_sspp),
> > + .sspp = sm8250_sspp,
> > + .mixer_count = ARRAY_SIZE(sm8150_lm),
> > + .mixer = sm8150_lm,
> > + .dspp_count = ARRAY_SIZE(sm8150_dspp),
> > + .dspp = sm8150_dspp,
> > + .pingpong_count = ARRAY_SIZE(sm8350_pp),
> > + .pingpong = sm8350_pp,
> > + .dsc_count = ARRAY_SIZE(sm8350_dsc),
> > + .dsc = sm8350_dsc,
> > + .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
> > + .merge_3d = sm8350_merge_3d,
> > + .intf_count = ARRAY_SIZE(sm8350_intf),
> > + .intf = sm8350_intf,
> > + .vbif_count = ARRAY_SIZE(sdm845_vbif),
> > + .vbif = sdm845_vbif,
> > + .reg_dma_count = 1,
> > + .dma_cfg = &sm8250_regdma,
> > + .perf = &sm8350_perf_data,
> > + .mdss_irqs = IRQ_SM8350_MASK,
> > +};
> > +
> > static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
> > .caps = &sm8450_dpu_caps,
> > .mdp_count = ARRAY_SIZE(sm8450_mdp),
> > @@ -2158,6 +2353,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
> > { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
> > { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
> > { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
> > + { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
> > { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
> > { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
> > };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > index 664c4876f44a..5335123a0289 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > @@ -45,6 +45,7 @@
> > #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
> > #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
> > #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
> > +#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
> > #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
> > #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */
> >
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2022-12-28 9:27 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-05 16:37 [PATCH v3 00/11] Enable Display for SM8350 Robert Foss
2022-12-05 16:37 ` [PATCH v3 01/11] dt-bindings: display: msm: Add qcom,sm8350-dpu binding Robert Foss
2022-12-05 16:37 ` [PATCH v3 02/11] dt-bindings: display: msm: Add qcom,sm8350-mdss binding Robert Foss
2022-12-05 21:08 ` Rob Herring
2022-12-05 16:37 ` [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog Robert Foss
2022-12-05 16:43 ` Konrad Dybcio
2022-12-07 23:39 ` Dmitry Baryshkov
2022-12-07 23:42 ` Abhinav Kumar
2022-12-28 9:27 ` Robert Foss
2022-12-05 16:37 ` [PATCH v3 04/11] drm/msm/dpu: Add support for SM8350 Robert Foss
2022-12-07 23:40 ` Dmitry Baryshkov
2022-12-07 23:47 ` Abhinav Kumar
2022-12-05 16:37 ` [PATCH v3 05/11] drm/msm: " Robert Foss
2022-12-05 16:43 ` Konrad Dybcio
2022-12-07 23:50 ` Dmitry Baryshkov
2022-12-19 16:18 ` Robert Foss
2022-12-05 16:37 ` [PATCH v3 06/11] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names Robert Foss
2022-12-05 16:37 ` [PATCH v3 07/11] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name Robert Foss
2022-12-05 16:37 ` [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells Robert Foss
2022-12-05 19:19 ` Georgi Djakov
2022-12-19 16:15 ` Robert Foss
2022-12-05 16:37 ` [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes Robert Foss
2022-12-05 16:43 ` Dmitry Baryshkov
2022-12-05 16:46 ` Krzysztof Kozlowski
2022-12-05 16:49 ` Konrad Dybcio
2022-12-05 16:37 ` [PATCH v3 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes Robert Foss
2022-12-05 16:44 ` Dmitry Baryshkov
2022-12-19 16:11 ` Robert Foss
2022-12-05 16:37 ` [PATCH v3 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Robert Foss
2022-12-05 16:47 ` Krzysztof Kozlowski
2022-12-28 8:26 ` Robert Foss
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).