Re: [PATCH] arm64: dts: sdm845: Add CPU topology

[Amit Kucheria <amit.kucheria@linaro.org>]

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On Mon, May 13, 2019 at 4:31 PM Amit Kucheria <amit.kucheria@linaro.org> wrote:
>
> On Tue, Jan 15, 2019 at 12:13 AM Matthias Kaehlcke <mka@chromium.org> wrote:
> >
> > The 8 CPU cores of the SDM845 are organized in two clusters of 4 big
> > ("gold") and 4 little ("silver") cores. Add a cpu-map node to the DT
> > that describes this topology.
>
> This is partly true. There are two groups of gold and silver cores,
> but AFAICT they are in a single cluster, not two separate ones. SDM845
> is one of the early examples of ARM's Dynamiq architecture.
>
> > Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
>
> I noticed that this patch sneaked through for this merge window but
> perhaps we can whip up a quick fix for -rc2?
>

And please find attached a patch to fix this up. Andy, since this
hasn't landed yet (can we still squash this into the original patch?),
I couldn't add a Fixes tag.

Regards,
Amit

> > ---
> >  arch/arm64/boot/dts/qcom/sdm845.dtsi | 38 ++++++++++++++++++++++++++++
> >  1 file changed, 38 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > index c27cbd3bcb0a6..f6c0d87e663f3 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > @@ -192,6 +192,44 @@
> >                                 next-level-cache = <&L3_0>;
> >                         };
> >                 };
> > +
> > +               cpu-map {
> > +                       cluster0 {
> > +                               core0 {
> > +                                       cpu = <&CPU0>;
> > +                               };
> > +
> > +                               core1 {
> > +                                       cpu = <&CPU1>;
> > +                               };
> > +
> > +                               core2 {
> > +                                       cpu = <&CPU2>;
> > +                               };
> > +
> > +                               core3 {
> > +                                       cpu = <&CPU3>;
> > +                               };
> > +                       };
> > +
> > +                       cluster1 {
>
> This shouldn't exist.
>
> > +                               core0 {
>
> Rename to core4, 5, etc...
>
> > +                                       cpu = <&CPU4>;
> > +                               };
> > +
> > +                               core1 {
> > +                                       cpu = <&CPU5>;
> > +                               };
> > +
> > +                               core2 {
> > +                                       cpu = <&CPU6>;
> > +                               };
> > +
> > +                               core3 {
> > +                                       cpu = <&CPU7>;
> > +                               };
> > +                       };
> > +               };
> >         };
> >
> >         pmu {
> > --
> > 2.20.1.97.g81188d93c3-goog
> >

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From 9e7d60bcabad7594a1da43982bbc9fda04669717 Mon Sep 17 00:00:00 2001
Message-Id: <9e7d60bcabad7594a1da43982bbc9fda04669717.1557748437.git.amit.kucheria@linaro.org>
From: Amit Kucheria <amit.kucheria@linaro.org>
Date: Mon, 13 May 2019 17:08:33 +0530
Subject: [PATCH] arm64: dts: sdm845: Fix up CPU topology

SDM845 implements ARM's Dynamiq architecture that allows the big and
LITTLE cores to exist in a single cluster sharing the L3 cache.

Fix the cpu-map to put all cpus into a single cluster.

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index ef7ce63eef4e..a30fa54bfccd 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -246,22 +246,20 @@
 				core3 {
 					cpu = <&CPU3>;
 				};
-			};
 
-			cluster1 {
-				core0 {
+				core4 {
 					cpu = <&CPU4>;
 				};
 
-				core1 {
+				core5 {
 					cpu = <&CPU5>;
 				};
 
-				core2 {
+				core6 {
 					cpu = <&CPU6>;
 				};
 
-				core3 {
+				core7 {
 					cpu = <&CPU7>;
 				};
 			};
-- 
2.17.1