From: Arnd Bergmann <arnd@arndb.de>
To: Yassine Oudjana <y.oudjana@protonmail.com>
Cc: Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Ard Biesheuvel <ardb@kernel.org>,
Android Kernel Team <kernel-team@android.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Mark Rutland <mark.rutland@arm.com>,
Vincent Whitchurch <vincent.whitchurch@axis.com>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Subject: Re: [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)
Date: Wed, 7 Jul 2021 11:29:20 +0200 [thread overview]
Message-ID: <CAK8P3a33ZD6uLntmuvp_Rgfj1VYEV3YxP6+BxSDAQLon-q2hGw@mail.gmail.com> (raw)
In-Reply-To: <M0wGhzKTDUUYQPjRdiabG3xuKLx8p19uB1iqdkwfa8Op45i4zBGm4mpcHIxpYzWkJLiUM6JtQIDuBVyLlXtPhrlPyycbhZ2GO1ldLymA40g=@protonmail.com>
On Tue, Jul 6, 2021 at 6:20 PM Will Deacon <will@kernel.org> wrote:
>
> I think the million dollar question is whether the 128-byte cache-lines
> live in a cache above the PoC or not. If it's just a system level cache
> through which all DMA is "coherent", then it doesn't matter.
On Wed, Jul 7, 2021 at 10:24 AM Yassine Oudjana
<y.oudjana@protonmail.com> wrote:
>
> On Wednesday, July 7th, 2021 at 12:33 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> > On Tue, Jul 6, 2021 at 7:15 PM Yassine Oudjana y.oudjana@protonmail.com wrote:
> > >
> > > $ numactl -C 0 line -M 1M
> > > 128
> > > $ numactl -C 3 line -M 1M
> > > 128
> >
> > Can you rerun the the 'line' test with '-M 128K' to see if that confirms the 64
> > byte L1 line size that the 'cache' test reported?
>
> $ numactl -C 0 line -M 128K
> 64
> $ numactl -C 3 line -M 128K
> 64
Ok, so this seems to confirm that the L1 uses 64 byte lines, while the L2 (or
possibly L3) uses 128 byte lines.
On Wed, Jul 7, 2021 at 12:27 AM Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
>
> I can confirm that MSM8996, and a few derivatives, has 128 byte cache lines.
Ok, thanks. Assuming this is an outer cache and the L1 indeed has a smaller line
size, can you also confirm that this 128 byte lines are north of the point of
coherency?
In other words, does the CTR_EL0.DminLine field also show 128 bytes
(in which case
it seems we already lost)? And if not, does a CPU store to the second half of a
128 byte L2 line cause DMA data in the first half to be clobbered?
Arnd
next prev parent reply other threads:[~2021-07-07 9:29 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20210527124356.22367-1-will@kernel.org>
2021-07-06 9:26 ` [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) Yassine Oudjana
2021-07-06 10:26 ` Catalin Marinas
2021-07-06 13:29 ` Robin Murphy
2021-07-06 13:33 ` Will Deacon
2021-07-06 13:44 ` Marc Zyngier
2021-07-06 14:21 ` Robin Murphy
2021-07-06 14:30 ` Arnd Bergmann
2021-07-06 14:46 ` Marc Zyngier
2021-07-06 15:43 ` Arnd Bergmann
2021-07-06 17:15 ` Yassine Oudjana
2021-07-06 20:33 ` Arnd Bergmann
2021-07-06 22:27 ` Bjorn Andersson
2021-07-07 9:27 ` Will Deacon
2021-07-07 8:24 ` Yassine Oudjana
2021-07-07 9:29 ` Arnd Bergmann [this message]
2021-07-07 14:41 ` Jeffrey Hugo
2021-07-08 20:59 ` Jeffrey Hugo
2021-07-09 8:48 ` Will Deacon
2021-07-09 17:10 ` Catalin Marinas
2021-07-06 16:20 ` Will Deacon
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