From: Arnd Bergmann <arnd@arndb.de>
To: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Yassine Oudjana <y.oudjana@protonmail.com>,
Ard Biesheuvel <ardb@kernel.org>,
Android Kernel Team <kernel-team@android.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Mark Rutland <mark.rutland@arm.com>,
Vincent Whitchurch <vincent.whitchurch@axis.com>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>
Subject: Re: [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)
Date: Tue, 6 Jul 2021 16:30:34 +0200 [thread overview]
Message-ID: <CAK8P3a2xWTvj6HjsC6gH44Ad13adKjK0wR7UxFFQ1i=XYixvQA@mail.gmail.com> (raw)
In-Reply-To: <f136da2ea91fc22334c552b8c524f6e7@kernel.org>
On Tue, Jul 6, 2021 at 3:44 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On 2021-07-06 14:33, Will Deacon wrote:
> > On Tue, Jul 06, 2021 at 02:29:07PM +0100, Robin Murphy wrote:
> >
> > I can't find much information about the original Kryo core at all...
>
> I have similar issues with my QDF2400. The UART, RTC and DMA controllers
> are all screaming at me. I'm confident that the UART doesn't do any
> DMA (it is handled by the SBSA driver), but the DMA controllers are
> probably doing what it says on the tin.
But that's a server chip, surely the DMA controller is fully cache coherent
as required by SBSA? (please?)
Maybe just a misannotation on the device node?
> Do we know whether Falkor and Kryo share any part of their design?
I'm fairly sure the Snapdragon 821 / msm8996 is not cache coherent.
I can only speculate on how much got reused between the two, but
as Falkor was released only after they had already given up on
the full-custom Kryo core, it's plausible that it incorporates bits from
that one. In particular the cache controller is probably easy to reuse
even if the rest of it was a new design.
Arnd
next prev parent reply other threads:[~2021-07-06 14:39 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20210527124356.22367-1-will@kernel.org>
2021-07-06 9:26 ` [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) Yassine Oudjana
2021-07-06 10:26 ` Catalin Marinas
2021-07-06 13:29 ` Robin Murphy
2021-07-06 13:33 ` Will Deacon
2021-07-06 13:44 ` Marc Zyngier
2021-07-06 14:21 ` Robin Murphy
2021-07-06 14:30 ` Arnd Bergmann [this message]
2021-07-06 14:46 ` Marc Zyngier
2021-07-06 15:43 ` Arnd Bergmann
2021-07-06 17:15 ` Yassine Oudjana
2021-07-06 20:33 ` Arnd Bergmann
2021-07-06 22:27 ` Bjorn Andersson
2021-07-07 9:27 ` Will Deacon
2021-07-07 8:24 ` Yassine Oudjana
2021-07-07 9:29 ` Arnd Bergmann
2021-07-07 14:41 ` Jeffrey Hugo
2021-07-08 20:59 ` Jeffrey Hugo
2021-07-09 8:48 ` Will Deacon
2021-07-09 17:10 ` Catalin Marinas
2021-07-06 16:20 ` Will Deacon
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