[PATCH 0/4] remoteproc: qcom: Add support for CDSP and MSS on SDM630/660

[PATCH 0/4] remoteproc: qcom: Add support for CDSP and MSS on SDM630/660

[Dmitry Baryshkov]

Acompany existing support for ADSP on SDM630/660 platforms with support
for CDSP (660 only) and MSS (both platforms). Tested on IFC6560 (SDA660)
board.

Dmitry Baryshkov (3):
  dt-bindings: remoteproc: qcom: Add SDM660 modem PAS compatible
  dt-bindings: remoteproc: qcom: pas: Add SDM660 CDSP PAS compatible
  remoteproc: qcom: pas: Add SDM660 CDSP PAS support

Konrad Dybcio (1):
  remoteproc: qcom: q6v5-mss: Add support for SDM630/636/660 MSS
    remoteproc

 .../bindings/remoteproc/qcom,adsp.yaml        |   7 ++
 .../bindings/remoteproc/qcom,q6v5.txt         |   4 +
 drivers/remoteproc/qcom_q6v5_mss.c            | 111 ++++++++++++++++++
 drivers/remoteproc/qcom_q6v5_pas.c            |   1 +
 4 files changed, 123 insertions(+)

-- 
2.35.1

[PATCH 1/4] dt-bindings: remoteproc: qcom: Add SDM660 modem PAS compatible

[Dmitry Baryshkov]

Describe required properties of the SDM660 MSS PIL device.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 8f1507052afd..5ecfaf2048ab 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -16,6 +16,7 @@ on the Qualcomm Hexagon core.
 		    "qcom,msm8998-mss-pil"
 		    "qcom,sc7180-mss-pil"
 		    "qcom,sc7280-mss-pil"
+		    "qcom,sdm660-mss-pil"
 		    "qcom,sdm845-mss-pil"
 
 - reg:
@@ -44,6 +45,7 @@ on the Qualcomm Hexagon core.
 	qcom,qcs404-wcss-pil:
 	qcom,msm8916-mss-pil:
 	qcom,msm8974-mss-pil:
+	qcom,sdm660-mss-pil:
 		    must be "wdog", "fatal", "ready", "handover", "stop-ack"
 	qcom,msm8996-mss-pil:
 	qcom,msm8998-mss-pil:
@@ -84,6 +86,7 @@ on the Qualcomm Hexagon core.
 		    must be "iface", "bus", "mem", "xo", "gpll0_mss",
 		    "snoc_axi", "mnoc_axi", "pnoc", "qdss"
 	qcom,msm8998-mss-pil:
+	qcom,sdm660-mss-pil:
 		    must be "iface", "bus", "mem", "xo", "gpll0_mss",
 		    "snoc_axi", "mnoc_axi", "qdss"
 	qcom,sc7180-mss-pil:
@@ -175,6 +178,7 @@ For the compatible string below the following supplies are required:
 	qcom,msm8974-mss-pil:
 	qcom,msm8996-mss-pil:
 	qcom,msm8998-mss-pil:
+	qcom,sdm660-mss-pil:
 		    must be "cx", "mx"
 	qcom,sc7180-mss-pil:
 		    must be "cx", "mx", "mss"
-- 
2.35.1

Re: [PATCH 1/4] dt-bindings: remoteproc: qcom: Add SDM660 modem PAS compatible

[Rob Herring]

On Sat, 14 May 2022 03:01:05 +0300, Dmitry Baryshkov wrote:
> Describe required properties of the SDM660 MSS PIL device.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 2/4] dt-bindings: remoteproc: qcom: pas: Add SDM660 CDSP PAS compatible

[Dmitry Baryshkov]

The Qualcomm SDM660 has the usual audio, compute, sensor and modem
remoteprocs. Add compatible string and conditions for the compute and
modem PAS.  While we are at it, also add missing conditions for the
audio PAS.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/remoteproc/qcom,adsp.yaml          | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
index a4409c398193..682df80d3a96 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
@@ -30,6 +30,7 @@ properties:
       - qcom,sc8180x-cdsp-pas
       - qcom,sc8180x-mpss-pas
       - qcom,sdm660-adsp-pas
+      - qcom,sdm660-cdsp-pas
       - qcom,sdm845-adsp-pas
       - qcom,sdm845-cdsp-pas
       - qcom,sdx55-mpss-pas
@@ -169,6 +170,8 @@ allOf:
               - qcom,sc8180x-adsp-pas
               - qcom,sc8180x-cdsp-pas
               - qcom,sc8180x-mpss-pas
+              - qcom,sdm660-adsp-pas
+              - qcom,sdm660-cdsp-pas
               - qcom,sdm845-adsp-pas
               - qcom,sdm845-cdsp-pas
               - qcom,sm6350-adsp-pas
@@ -284,6 +287,8 @@ allOf:
               - qcom,qcs404-wcss-pas
               - qcom,sc8180x-adsp-pas
               - qcom,sc8180x-cdsp-pas
+              - qcom,sdm660-adsp-pas
+              - qcom,sdm660-cdsp-pas
               - qcom,sdm845-adsp-pas
               - qcom,sdm845-cdsp-pas
               - qcom,sm6350-adsp-pas
@@ -366,6 +371,8 @@ allOf:
             enum:
               - qcom,msm8996-adsp-pil
               - qcom,msm8998-adsp-pas
+              - qcom,sdm660-adsp-pas
+              - qcom,sdm660-cdsp-pas
     then:
       properties:
         power-domains:
-- 
2.35.1

Re: [PATCH 2/4] dt-bindings: remoteproc: qcom: pas: Add SDM660 CDSP PAS compatible

[Rob Herring]

On Sat, 14 May 2022 03:01:06 +0300, Dmitry Baryshkov wrote:
> The Qualcomm SDM660 has the usual audio, compute, sensor and modem
> remoteprocs. Add compatible string and conditions for the compute and
> modem PAS.  While we are at it, also add missing conditions for the
> audio PAS.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../devicetree/bindings/remoteproc/qcom,adsp.yaml          | 7 +++++++
>  1 file changed, 7 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 3/4] remoteproc: qcom: q6v5-mss: Add support for SDM630/636/660 MSS remoteproc

[Dmitry Baryshkov]

From: Konrad Dybcio <konradybcio@gmail.com>

This adds support for sdm630/636/660 modem subsystem
remote processor.

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
[DB: fixed commit message, removed note about modem restarting regularly]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/remoteproc/qcom_q6v5_mss.c | 111 +++++++++++++++++++++++++++++
 1 file changed, 111 insertions(+)

diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index af217de75e4d..7a4cca30db8a 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -68,6 +68,7 @@
 #define QDSP6SS_MEM_PWR_CTL		0x0B0
 #define QDSP6V6SS_MEM_PWR_CTL		0x034
 #define QDSP6SS_STRAP_ACC		0x110
+#define QDSP6V62SS_BHS_STATUS		0x0C4
 
 /* AXI Halt Register Offsets */
 #define AXI_HALTREQ_REG			0x0
@@ -117,6 +118,9 @@
 #define QDSP6v56_CLAMP_QMC_MEM		BIT(22)
 #define QDSP6SS_XO_CBCR		0x0038
 #define QDSP6SS_ACC_OVERRIDE_VAL		0x20
+#define QDSP6v55_BHS_EN_REST_ACK        BIT(0)
+
+#define BHS_CHECK_MAX_LOOPS             (200)
 
 /* QDSP6v65 parameters */
 #define QDSP6SS_CORE_CBCR		0x20
@@ -239,6 +243,7 @@ enum {
 	MSS_MSM8998,
 	MSS_SC7180,
 	MSS_SC7280,
+	MSS_SDM660,
 	MSS_SDM845,
 };
 
@@ -754,6 +759,79 @@ static int q6v5proc_reset(struct q6v5 *qproc)
 			val |= readl(qproc->reg_base + mem_pwr_ctl);
 			udelay(1);
 		}
+		/* Remove word line clamp */
+		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		val &= ~QDSP6v56_CLAMP_WL;
+		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+	} else if (qproc->version == MSS_SDM660) {
+		int mem_pwr_ctl;
+
+		/* Override the ACC value if required */
+		writel(QDSP6SS_ACC_OVERRIDE_VAL,
+		       qproc->reg_base + QDSP6SS_STRAP_ACC);
+
+		/* Assert resets, stop core */
+		val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
+		val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
+		writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+
+		/* BHS require xo cbcr to be enabled */
+		val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
+		val |= 1;
+		writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
+
+		/* Enable power block headswitch and wait for it to stabilize */
+		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		val |= QDSP6v56_BHS_ON;
+		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		mb();
+		udelay(1);
+
+		for (i = BHS_CHECK_MAX_LOOPS; i > 0; i--) {
+			if (readl_relaxed(qproc->reg_base + QDSP6V62SS_BHS_STATUS)
+			    & QDSP6v55_BHS_EN_REST_ACK)
+				break;
+			udelay(1);
+		}
+		if (!i) {
+			pr_err("%s: BHS_EN_REST_ACK not set!\n", __func__);
+			return -ETIMEDOUT;
+		}
+
+		/* Put LDO in bypass mode */
+		val |= QDSP6v56_LDO_BYP;
+		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+		/* Remove QMC_MEM clamp */
+		val &= ~QDSP6v56_CLAMP_QMC_MEM;
+		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+		/* Deassert QDSP6 compiler memory clamp */
+		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+		val &= ~QDSP6v56_CLAMP_QMC_MEM;
+		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+		/* Deassert memory peripheral sleep and L2 memory standby */
+		val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
+		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+		/* Turn on L1, L2, ETB and JU memories 1 at a time */
+		mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
+		i = 29;
+
+		val = readl(qproc->reg_base + mem_pwr_ctl);
+		for (; i >= 0; i--) {
+			val |= BIT(i);
+			writel(val, qproc->reg_base + mem_pwr_ctl);
+			/*
+			 * Read back value to ensure the write is done then
+			 * wait for 1us for both memory peripheral and data
+			 * array to turn on.
+			 */
+			val |= readl(qproc->reg_base + mem_pwr_ctl);
+			udelay(1);
+		}
+
 		/* Remove word line clamp */
 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 		val &= ~QDSP6v56_CLAMP_WL;
@@ -785,6 +863,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
 		val |= Q6SS_L2DATA_SLP_NRET_N_0;
 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 	}
+
 	/* Remove IO clamp */
 	val &= ~Q6SS_CLAMP_IO;
 	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
@@ -2098,6 +2177,37 @@ static const struct rproc_hexagon_res sc7280_mss = {
 	.version = MSS_SC7280,
 };
 
+static const struct rproc_hexagon_res sdm660_mss = {
+	.hexagon_mba_image = "mba.mbn",
+	.proxy_clk_names = (char*[]){
+			"xo",
+			"qdss",
+			NULL
+	},
+	.active_clk_names = (char*[]){
+			"iface",
+			"bus",
+			"gpll0_mss",
+			"mnoc_axi",
+			"snoc_axi",
+			"mem",
+			NULL
+	},
+	.proxy_pd_names = (char*[]){
+			"cx",
+			"mx",
+			NULL
+	},
+	.need_mem_protection = true,
+	.has_alt_reset = false,
+	.has_mba_logs = false,
+	.has_spare_reg = false,
+	.has_qaccept_regs = false,
+	.has_ext_cntl_regs = false,
+	.has_vq6 = false,
+	.version = MSS_SDM660,
+};
+
 static const struct rproc_hexagon_res sdm845_mss = {
 	.hexagon_mba_image = "mba.mbn",
 	.proxy_clk_names = (char*[]){
@@ -2304,6 +2414,7 @@ static const struct of_device_id q6v5_of_match[] = {
 	{ .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
 	{ .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
 	{ .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
+	{ .compatible = "qcom,sdm660-mss-pil", .data = &sdm660_mss},
 	{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
 	{ },
 };
-- 
2.35.1

Re: [PATCH 3/4] remoteproc: qcom: q6v5-mss: Add support for SDM630/636/660 MSS remoteproc

[Stephan Gerhold]

On Sat, May 14, 2022 at 03:01:07AM +0300, Dmitry Baryshkov wrote:
> From: Konrad Dybcio <konradybcio@gmail.com>
> 
> This adds support for sdm630/636/660 modem subsystem
> remote processor.
> 
> Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
> [DB: fixed commit message, removed note about modem restarting regularly]
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

I was only looking at this by coincidence recently but since it doesn't
seem to be applied yet(?) some comments below.

> ---
>  drivers/remoteproc/qcom_q6v5_mss.c | 111 +++++++++++++++++++++++++++++
>  1 file changed, 111 insertions(+)
> 
> diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
> index af217de75e4d..7a4cca30db8a 100644
> --- a/drivers/remoteproc/qcom_q6v5_mss.c
> +++ b/drivers/remoteproc/qcom_q6v5_mss.c
[...]
> @@ -754,6 +759,79 @@ static int q6v5proc_reset(struct q6v5 *qproc)
>  			val |= readl(qproc->reg_base + mem_pwr_ctl);
>  			udelay(1);
>  		}
> +		/* Remove word line clamp */
> +		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> +		val &= ~QDSP6v56_CLAMP_WL;
> +		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> +	} else if (qproc->version == MSS_SDM660) {
> +		int mem_pwr_ctl;
> +
> +		/* Override the ACC value if required */
> +		writel(QDSP6SS_ACC_OVERRIDE_VAL,
> +		       qproc->reg_base + QDSP6SS_STRAP_ACC);
> +
> +		/* Assert resets, stop core */
> +		val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
> +		val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
> +		writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
> +
> +		/* BHS require xo cbcr to be enabled */
> +		val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
> +		val |= 1;

val |= Q6SS_CBCR_CLKEN; (like in the existing 8996 code)

> +		writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);

I would also expect this to wait for !Q6SS_CBCR_CLKOFF like on all the
other SoCs. Pretty sure downstream does that for all of them in
q6v55_branch_clk_enable().

> +
> +		/* Enable power block headswitch and wait for it to stabilize */
> +		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> +		val |= QDSP6v56_BHS_ON;
> +		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> +		mb();
> +		udelay(1);
> +
> +		for (i = BHS_CHECK_MAX_LOOPS; i > 0; i--) {
> +			if (readl_relaxed(qproc->reg_base + QDSP6V62SS_BHS_STATUS)
> +			    & QDSP6v55_BHS_EN_REST_ACK)
> +				break;
> +			udelay(1);
> +		}

This looks like readl_poll_timeout().

> +		if (!i) {
> +			pr_err("%s: BHS_EN_REST_ACK not set!\n", __func__);

dev_err()

> +			return -ETIMEDOUT;
> +		}
> +
> +		/* Put LDO in bypass mode */
> +		val |= QDSP6v56_LDO_BYP;
> +		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> +
> +		/* Remove QMC_MEM clamp */
> +		val &= ~QDSP6v56_CLAMP_QMC_MEM;
> +		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> +
> +		/* Deassert QDSP6 compiler memory clamp */
> +		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> +		val &= ~QDSP6v56_CLAMP_QMC_MEM;
> +		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> +

Why does this clear QDSP6v56_CLAMP_QMC_MEM twice?

> +		/* Deassert memory peripheral sleep and L2 memory standby */
> +		val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
> +		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> +
> +		/* Turn on L1, L2, ETB and JU memories 1 at a time */
> +		mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
> +		i = 29;
> +
> +		val = readl(qproc->reg_base + mem_pwr_ctl);
> +		for (; i >= 0; i--) {
> +			val |= BIT(i);
> +			writel(val, qproc->reg_base + mem_pwr_ctl);
> +			/*
> +			 * Read back value to ensure the write is done then
> +			 * wait for 1us for both memory peripheral and data
> +			 * array to turn on.
> +			 */
> +			val |= readl(qproc->reg_base + mem_pwr_ctl);
> +			udelay(1);
> +		}
> +
>  		/* Remove word line clamp */
>  		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>  		val &= ~QDSP6v56_CLAMP_WL;

All in all this looks almost exactly like the existing code for
MSS_MSM8996/8. Wouldn't it be cleaner to just add an if statement for
the QDSP6V62SS_BHS_STATUS readl_poll_timeout() to the existing code?

Thanks,
Stephan

Re: [PATCH 3/4] remoteproc: qcom: q6v5-mss: Add support for SDM630/636/660 MSS remoteproc

[Dmitry Baryshkov]

On 3 July 2022 13:13:51 GMT+03:00, Stephan Gerhold <stephan@gerhold.net> wrote:
>On Sat, May 14, 2022 at 03:01:07AM +0300, Dmitry Baryshkov wrote:
>> From: Konrad Dybcio <konradybcio@gmail.com>
>> 
>> This adds support for sdm630/636/660 modem subsystem
>> remote processor.
>> 
>> Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
>> [DB: fixed commit message, removed note about modem restarting regularly]
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
>I was only looking at this by coincidence recently but since it doesn't
>seem to be applied yet(?) some comments below.

Thanks for your comments, I will take a look next week.

>
>> ---
>>  drivers/remoteproc/qcom_q6v5_mss.c | 111 +++++++++++++++++++++++++++++
>>  1 file changed, 111 insertions(+)
>> 
>> diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
>> index af217de75e4d..7a4cca30db8a 100644
>> --- a/drivers/remoteproc/qcom_q6v5_mss.c
>> +++ b/drivers/remoteproc/qcom_q6v5_mss.c
>[...]
>> +		}
>> +
>>  		/* Remove word line clamp */
>>  		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>>  		val &= ~QDSP6v56_CLAMP_WL;
>
>All in all this looks almost exactly like the existing code for
>MSS_MSM8996/8. Wouldn't it be cleaner to just add an if statement for
>the QDSP6V62SS_BHS_STATUS readl_poll_timeout() to the existing code?

For quite some time I was unhappy with this part of the mss driver. Maybe it's time to review platform-specific code in attempt to generalise it.

-- 
With best wishes
Dmitry

[PATCH 4/4] remoteproc: qcom: pas: Add SDM660 CDSP PAS support

[Dmitry Baryshkov]

Add compatible string for the CDSP found on SDM660 platform. The
resources needed matches those of QCS404, so its desc is reused.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/remoteproc/qcom_q6v5_pas.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 1ae47cc153e5..39c9c56e8de9 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -862,6 +862,7 @@ static const struct of_device_id adsp_of_match[] = {
 	{ .compatible = "qcom,sc8180x-cdsp-pas", .data = &sm8150_cdsp_resource},
 	{ .compatible = "qcom,sc8180x-mpss-pas", .data = &sc8180x_mpss_resource},
 	{ .compatible = "qcom,sdm660-adsp-pas", .data = &adsp_resource_init},
+	{ .compatible = "qcom,sdm660-cdsp-pas", .data = &cdsp_resource_init},
 	{ .compatible = "qcom,sdm845-adsp-pas", .data = &sdm845_adsp_resource_init},
 	{ .compatible = "qcom,sdm845-cdsp-pas", .data = &sdm845_cdsp_resource_init},
 	{ .compatible = "qcom,sdx55-mpss-pas", .data = &sdx55_mpss_resource},
-- 
2.35.1