Re: [PATCH v4 1/5] clk: qcom: clk-alpha-pll: replace regval with val

From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Vinod Koul <vkoul@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>,
	linux-arm-msm@vger.kernel.org, Andy Gross <agross@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>,
	Taniya Das <tdas@codeaurora.org>,
	AngeloGioacchino Del Regno 
	<angelogioacchino.delregno@somainline.org>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 1/5] clk: qcom: clk-alpha-pll: replace regval with val
Date: Mon, 25 Jan 2021 11:13:34 -0600	[thread overview]
Message-ID: <YA78PvE4hDLc2Lo9@builder.lan> (raw)
In-Reply-To: <20210118044321.2571775-2-vkoul@kernel.org>

On Sun 17 Jan 22:43 CST 2021, Vinod Koul wrote:

> Driver uses regval variable for holding register values, replace with a
> shorter one val
> 

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> Suggested-by: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>  drivers/clk/qcom/clk-alpha-pll.c | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 21c357c26ec4..f7721088494c 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -777,15 +777,15 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
>  static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
>  				struct regmap *regmap)
>  {
> -	u32 mode_regval, opmode_regval;
> +	u32 mode_val, opmode_val;
>  	int ret;
>  
> -	ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);
> -	ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval);
> +	ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
> +	ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
>  	if (ret)
>  		return 0;
>  
> -	return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL));
> +	return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
>  }
>  
>  static int clk_trion_pll_is_enabled(struct clk_hw *hw)
> @@ -1445,12 +1445,12 @@ EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
>  static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
>  {
>  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> -	u32 regval;
> +	u32 val;
>  	int ret;
>  
>  	/* Return early if calibration is not needed. */
> -	regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);
> -	if (regval & pcal_done)
> +	regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
> +	if (val & pcal_done)
>  		return 0;
>  
>  	/* On/off to calibrate */
> @@ -1476,7 +1476,7 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
>  {
>  	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
>  	unsigned long rrate;
> -	u32 regval, l, alpha_width = pll_alpha_width(pll);
> +	u32 val, l, alpha_width = pll_alpha_width(pll);
>  	u64 a;
>  	int ret;
>  
> @@ -1497,8 +1497,8 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
>  
>  	/* Wait for 2 reference cycles before checking the ACK bit. */
>  	udelay(1);
> -	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
> -	if (!(regval & ALPHA_PLL_ACK_LATCH)) {
> +	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
> +	if (!(val & ALPHA_PLL_ACK_LATCH)) {
>  		pr_err("Lucid PLL latch failed. Output may be unstable!\n");
>  		return -EINVAL;
>  	}
> -- 
> 2.26.2
> 