From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Shawn Guo <shawn.guo@linaro.org>
Cc: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-arm-msm@vger.kernel.org, Evan Green <evgreen@chromium.org>
Subject: Re: [PATCH 1/4] arm64: dts: qcom: sdm845: fix number of pins in 'gpio-ranges'
Date: Wed, 10 Mar 2021 12:22:32 -0600 [thread overview]
Message-ID: <YEkOaK+UiLy8kSDu@builder.lan> (raw)
In-Reply-To: <20210306080049.GM17424@dragon>
On Sat 06 Mar 02:00 CST 2021, Shawn Guo wrote:
> On Fri, Mar 05, 2021 at 07:56:02PM -0600, Bjorn Andersson wrote:
> > On Fri 05 Mar 19:28 CST 2021, Shawn Guo wrote:
> >
> > > On Fri, Mar 05, 2021 at 03:43:08PM -0600, Bjorn Andersson wrote:
> > > > On Tue 02 Mar 21:31 CST 2021, Shawn Guo wrote:
> > > >
> > > > > The last cell of 'gpio-ranges' should be number of GPIO pins, and in
> > > > > case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather
> > > > > than msm_pinctrl_soc_data.ngpio - 1.
> > > > >
> > > >
> > > > This is a historical artifact, SDM845 has 150 GPIO pins. In addition to
> > > > this there's an output-only pin for UFS, which I exposed as an GPIO as
> > > > well - but it's only supposed to be used as a reset-gpio for the UFS
> > > > device.
> > > >
> > > > Perhaps that still mandates that gpio-ranges should cover it?
> > >
> > > I think the number in DT gpio-ranges should match msm_pinctrl_soc_data.ngpio.
> > > Otherwise, kernel will be confused and be running into the issue like
> > > below in some case.
> > >
> > > >
> > > > > This fixes the problem that when the last GPIO pin in the range is
> > > > > configured with the following call sequence, it always fails with
> > > > > -EPROBE_DEFER.
> > > > >
> > > > > pinctrl_gpio_set_config()
> > > > > pinctrl_get_device_gpio_range()
> > > > > pinctrl_match_gpio_range()
> > > >
> > > > When do we hit this sequence? I didn't think operations on the UFS
> > > > GP(I)O would ever take this code path?
> > >
> > > It will, if we have UFS driver booting from ACPI and requesting reset
> > > GPIO.
> >
> > But does the UFS driver somehow request GPIO 190 on SC8180x?
> >
> > I made up the idea that this is a GPIO, there really only is 190 (0-189)
> > GPIOs on thie SoC.
> >
> > Downstream they use a pinconf node with "output-high"/"output-low" to
> > toggle the reset pin and I don't find any references in the Flex 5G
> > DSDT.
>
> Right now, I do not have to request and configure this UFS GPIO for
> getting UFS work with ACPI kernel. And the immediate problem we have is
> that with gpio_chip .set_config patch, devm_gpiod_get_optional() call
> from UFS driver always gets -EPROBE_DEFER.
>
But we don't have a "reset" GPIO specified in the ACPI node, or you mean
with the introduction of .set_config DT no longer works?
Regards,
Bjorn
> >
> > > And we are hit this sequence with my patch that adds .set_config
> > > for gpio_chip [1].
> > >
> >
> > What's calling pinctrl_gpio_set_config() in this case?
>
> ufs_qcom_probe
> ufshcd_pltfrm_init
> ufshcd_init
> ufs_qcom_init
> devm_gpiod_get_optional
> devm_gpiod_get_index
> gpiod_get_index
> gpiod_configure_flags
> gpiod_direction_output
> gpiochip_generic_config
>
> Shawn
next prev parent reply other threads:[~2021-03-10 18:23 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-03 3:31 [PATCH 0/4] Fix number of pins in 'gpio-ranges' Shawn Guo
2021-03-03 3:31 ` [PATCH 1/4] arm64: dts: qcom: sdm845: fix " Shawn Guo
2021-03-05 21:43 ` Bjorn Andersson
2021-03-06 1:28 ` Shawn Guo
2021-03-06 1:56 ` Bjorn Andersson
2021-03-06 8:00 ` Shawn Guo
2021-03-10 18:22 ` Bjorn Andersson [this message]
2021-03-11 1:19 ` Shawn Guo
2021-03-11 16:53 ` Bjorn Andersson
2021-03-11 23:09 ` Shawn Guo
2021-03-11 23:17 ` Bjorn Andersson
2021-03-15 16:11 ` Linus Walleij
2021-03-03 3:31 ` [PATCH 2/4] arm64: dts: qcom: sm8150: " Shawn Guo
2021-03-03 3:31 ` [PATCH 3/4] arm64: dts: qcom: sm8250: " Shawn Guo
2021-03-03 3:31 ` [PATCH 4/4] arm64: dts: qcom: sm8350: " Shawn Guo
2021-03-11 23:40 ` [PATCH 0/4] Fix " patchwork-bot+linux-arm-msm
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