From: Vinod Koul <vkoul@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: kishon@ti.com, robh+dt@kernel.org, bjorn.andersson@linaro.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 0/3] Add support for PCIe PHY in SDX55
Date: Mon, 31 May 2021 11:38:21 +0530 [thread overview]
Message-ID: <YLR9Vd80yA8+/K9O@vkoul-mobl.Dlink> (raw)
In-Reply-To: <20210427065400.18958-1-manivannan.sadhasivam@linaro.org>
On 27-04-21, 12:23, Manivannan Sadhasivam wrote:
> Hi,
>
> This series adds support for PCIe PHY found in Qualcomm SDX55 platform.
> The PHY version is v4.20 which has different register offsets compared with
> previous v4.0x versions. So separate defines are introducted to handle the
> differences.
>
> This series has been tested on Telit FN980 EVB with an out of tree PCIe Endpoint
> driver.
Applied, thanks
I got a conflict on last patch as Dimitry has already added some defines
in the header.. Pls check everything was applied cleanly
Thanks
--
~Vinod
prev parent reply other threads:[~2021-05-31 6:09 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-27 6:53 [PATCH 0/3] Add support for PCIe PHY in SDX55 Manivannan Sadhasivam
2021-04-27 6:53 ` [PATCH 1/3] dt-bindings: phy: qcom,qmp: Add binding for SDX55 PCIe PHY Manivannan Sadhasivam
2021-05-03 19:13 ` Rob Herring
2021-05-29 16:25 ` Bjorn Andersson
2021-04-27 6:53 ` [PATCH 2/3] phy: qcom-qmp: Use phy_status field for the status bit offset Manivannan Sadhasivam
2021-05-29 17:02 ` Bjorn Andersson
2021-04-27 6:54 ` [PATCH 3/3] phy: qcom-qmp: Add support for SDX55 QMP PCIe PHY Manivannan Sadhasivam
2021-05-29 17:05 ` Bjorn Andersson
2021-05-31 6:08 ` Vinod Koul [this message]
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