* [PATCH 1/2] arch: arm64: dts: msm8996: Rename speedbin node @ 2021-05-27 19:44 Konrad Dybcio 2021-05-27 19:44 ` [PATCH 2/2] arch: arm64: dts: msm8996: Add CPU opps Konrad Dybcio 2021-05-31 21:50 ` [PATCH 1/2] arch: arm64: dts: msm8996: Rename speedbin node patchwork-bot+linux-arm-msm 0 siblings, 2 replies; 5+ messages in thread From: Konrad Dybcio @ 2021-05-27 19:44 UTC (permalink / raw) To: ~postmarketos/upstreaming Cc: martin.botka, angelogioacchino.delregno, marijn.suijten, jamipkettunen, Loic Poulain, Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm, devicetree, linux-kernel From: Loic Poulain <loic.poulain@linaro.org> The speedbin value blown in the efuse is used to determine is used to determine the voltage and frequency value for different IPs, including GPU, CPUs... So it's really not a gpu specific information. This patch simply renames 'gpu_speed_bin' node to 'speedbin'. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 3fc912f587ba..509d5bfec8ad 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -425,7 +425,7 @@ qusb2s_hstx_trim: hstx_trim@24f { bits = <1 4>; }; - gpu_speed_bin: gpu_speed_bin@133 { + speedbin_efuse: speedbin@133 { reg = <0x133 0x1>; bits = <5 3>; }; @@ -724,7 +724,7 @@ gpu: gpu@b00000 { power-domains = <&mmcc GPU_GX_GDSC>; iommus = <&adreno_smmu 0>; - nvmem-cells = <&gpu_speed_bin>; + nvmem-cells = <&speedbin_efuse>; nvmem-cell-names = "speed_bin"; qcom,gpu-quirk-two-pass-use-wfi; -- 2.31.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] arch: arm64: dts: msm8996: Add CPU opps 2021-05-27 19:44 [PATCH 1/2] arch: arm64: dts: msm8996: Rename speedbin node Konrad Dybcio @ 2021-05-27 19:44 ` Konrad Dybcio 2021-05-28 2:51 ` Bjorn Andersson 2021-05-31 21:50 ` [PATCH 1/2] arch: arm64: dts: msm8996: Rename speedbin node patchwork-bot+linux-arm-msm 1 sibling, 1 reply; 5+ messages in thread From: Konrad Dybcio @ 2021-05-27 19:44 UTC (permalink / raw) To: ~postmarketos/upstreaming Cc: martin.botka, angelogioacchino.delregno, marijn.suijten, jamipkettunen, Loic Poulain, Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm, devicetree, linux-kernel From: Loic Poulain <loic.poulain@linaro.org> Add the operating points capabilities of the kryo CPUs, that can be used for frequency scaling. There are two differents operating point tables, one for the big cluster and one for the LITTLE cluster. This frequency scaling support can then be used as a passive cooling device (cpufreq cooling device). Only add nominal fmax for now, since there is no dynamic control of VDD APC (s11..) which is statically set at its nominal value. Original patch link: https://patchwork.kernel.org/project/linux-arm-msm/patch/1595253740-29466-6-git-send-email-loic.poulain@linaro.org/ Signed-off-by: Loic Poulain <loic.poulain@linaro.org> [konrad: drop the thermals part, rebase and remove spaces within <>] Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 234 ++++++++++++++++++++++++++ 1 file changed, 234 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 509d5bfec8ad..10e6fecc9e13 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,apr.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; @@ -44,6 +45,9 @@ CPU0: cpu@0 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; + clocks = <&kryocc 0>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -58,6 +62,9 @@ CPU1: cpu@1 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; + clocks = <&kryocc 0>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_0>; }; @@ -68,6 +75,9 @@ CPU2: cpu@100 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; + clocks = <&kryocc 1>; + operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; @@ -82,6 +92,9 @@ CPU3: cpu@101 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; + clocks = <&kryocc 1>; + operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_1>; }; @@ -121,6 +134,227 @@ CPU_SLEEP_0: cpu-sleep-0 { }; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + /* Nominal fmax for now */ + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + /* Nominal fmax for now */ + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + }; + firmware { scm { compatible = "qcom,scm-msm8996"; -- 2.31.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] arch: arm64: dts: msm8996: Add CPU opps 2021-05-27 19:44 ` [PATCH 2/2] arch: arm64: dts: msm8996: Add CPU opps Konrad Dybcio @ 2021-05-28 2:51 ` Bjorn Andersson 2021-05-31 16:48 ` Bjorn Andersson 0 siblings, 1 reply; 5+ messages in thread From: Bjorn Andersson @ 2021-05-28 2:51 UTC (permalink / raw) To: Konrad Dybcio Cc: ~postmarketos/upstreaming, martin.botka, angelogioacchino.delregno, marijn.suijten, jamipkettunen, Loic Poulain, Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel On Thu 27 May 14:44 CDT 2021, Konrad Dybcio wrote: > From: Loic Poulain <loic.poulain@linaro.org> > > Add the operating points capabilities of the kryo CPUs, that can be > used for frequency scaling. There are two differents operating point > tables, one for the big cluster and one for the LITTLE cluster. > > This frequency scaling support can then be used as a passive cooling > device (cpufreq cooling device). > > Only add nominal fmax for now, since there is no dynamic control of > VDD APC (s11..) which is statically set at its nominal value. > > Original patch link: https://patchwork.kernel.org/project/linux-arm-msm/patch/1595253740-29466-6-git-send-email-loic.poulain@linaro.org/ > > Signed-off-by: Loic Poulain <loic.poulain@linaro.org> > [konrad: drop the thermals part, rebase and remove spaces within <>] > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> As reported to Konrad on IRC, booting this causes a lockup before the kernel reaches init, on one of my db820c boards. Booting with powersave governor makes this board boot fine and I'm able to switch to performance after that and at least according to cpufreq we're at full speed on all 4 cores. But I haven't done any proper stress of the system to narrow it down further... PS. This was tested with next-20210527, your 3 patches, defconfig and CONFIG_QCOM_CLK_APCC_MSM8996=y Regards, Bjorn > --- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 234 ++++++++++++++++++++++++++ > 1 file changed, 234 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index 509d5bfec8ad..10e6fecc9e13 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -8,6 +8,7 @@ > #include <dt-bindings/clock/qcom,rpmcc.h> > #include <dt-bindings/power/qcom-rpmpd.h> > #include <dt-bindings/soc/qcom,apr.h> > +#include <dt-bindings/thermal/thermal.h> > > / { > interrupt-parent = <&intc>; > @@ -44,6 +45,9 @@ CPU0: cpu@0 { > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > capacity-dmips-mhz = <1024>; > + clocks = <&kryocc 0>; > + operating-points-v2 = <&cluster0_opp>; > + #cooling-cells = <2>; > next-level-cache = <&L2_0>; > L2_0: l2-cache { > compatible = "cache"; > @@ -58,6 +62,9 @@ CPU1: cpu@1 { > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > capacity-dmips-mhz = <1024>; > + clocks = <&kryocc 0>; > + operating-points-v2 = <&cluster0_opp>; > + #cooling-cells = <2>; > next-level-cache = <&L2_0>; > }; > > @@ -68,6 +75,9 @@ CPU2: cpu@100 { > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > capacity-dmips-mhz = <1024>; > + clocks = <&kryocc 1>; > + operating-points-v2 = <&cluster1_opp>; > + #cooling-cells = <2>; > next-level-cache = <&L2_1>; > L2_1: l2-cache { > compatible = "cache"; > @@ -82,6 +92,9 @@ CPU3: cpu@101 { > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > capacity-dmips-mhz = <1024>; > + clocks = <&kryocc 1>; > + operating-points-v2 = <&cluster1_opp>; > + #cooling-cells = <2>; > next-level-cache = <&L2_1>; > }; > > @@ -121,6 +134,227 @@ CPU_SLEEP_0: cpu-sleep-0 { > }; > }; > > + cluster0_opp: opp_table0 { > + compatible = "operating-points-v2-kryo-cpu"; > + nvmem-cells = <&speedbin_efuse>; > + opp-shared; > + > + /* Nominal fmax for now */ > + opp-307200000 { > + opp-hz = /bits/ 64 <307200000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-422400000 { > + opp-hz = /bits/ 64 <422400000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-480000000 { > + opp-hz = /bits/ 64 <480000000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-556800000 { > + opp-hz = /bits/ 64 <556800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-652800000 { > + opp-hz = /bits/ 64 <652800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-729600000 { > + opp-hz = /bits/ 64 <729600000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-844800000 { > + opp-hz = /bits/ 64 <844800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-960000000 { > + opp-hz = /bits/ 64 <960000000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1036800000 { > + opp-hz = /bits/ 64 <1036800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1113600000 { > + opp-hz = /bits/ 64 <1113600000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1190400000 { > + opp-hz = /bits/ 64 <1190400000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1228800000 { > + opp-hz = /bits/ 64 <1228800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1324800000 { > + opp-hz = /bits/ 64 <1324800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1401600000 { > + opp-hz = /bits/ 64 <1401600000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1478400000 { > + opp-hz = /bits/ 64 <1478400000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1593600000 { > + opp-hz = /bits/ 64 <1593600000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + }; > + > + cluster1_opp: opp_table1 { > + compatible = "operating-points-v2-kryo-cpu"; > + nvmem-cells = <&speedbin_efuse>; > + opp-shared; > + > + /* Nominal fmax for now */ > + opp-307200000 { > + opp-hz = /bits/ 64 <307200000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-403200000 { > + opp-hz = /bits/ 64 <403200000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-480000000 { > + opp-hz = /bits/ 64 <480000000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-556800000 { > + opp-hz = /bits/ 64 <556800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-652800000 { > + opp-hz = /bits/ 64 <652800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-729600000 { > + opp-hz = /bits/ 64 <729600000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-806400000 { > + opp-hz = /bits/ 64 <806400000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-883200000 { > + opp-hz = /bits/ 64 <883200000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-940800000 { > + opp-hz = /bits/ 64 <940800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1036800000 { > + opp-hz = /bits/ 64 <1036800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1113600000 { > + opp-hz = /bits/ 64 <1113600000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1190400000 { > + opp-hz = /bits/ 64 <1190400000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1248000000 { > + opp-hz = /bits/ 64 <1248000000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1324800000 { > + opp-hz = /bits/ 64 <1324800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1401600000 { > + opp-hz = /bits/ 64 <1401600000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1478400000 { > + opp-hz = /bits/ 64 <1478400000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1555200000 { > + opp-hz = /bits/ 64 <1555200000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1632000000 { > + opp-hz = /bits/ 64 <1632000000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1708800000 { > + opp-hz = /bits/ 64 <1708800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1785600000 { > + opp-hz = /bits/ 64 <1785600000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1824000000 { > + opp-hz = /bits/ 64 <1824000000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1920000000 { > + opp-hz = /bits/ 64 <1920000000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-1996800000 { > + opp-hz = /bits/ 64 <1996800000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-2073600000 { > + opp-hz = /bits/ 64 <2073600000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-2150400000 { > + opp-hz = /bits/ 64 <2150400000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + }; > + > firmware { > scm { > compatible = "qcom,scm-msm8996"; > -- > 2.31.1 > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] arch: arm64: dts: msm8996: Add CPU opps 2021-05-28 2:51 ` Bjorn Andersson @ 2021-05-31 16:48 ` Bjorn Andersson 0 siblings, 0 replies; 5+ messages in thread From: Bjorn Andersson @ 2021-05-31 16:48 UTC (permalink / raw) To: Konrad Dybcio Cc: ~postmarketos/upstreaming, martin.botka, angelogioacchino.delregno, marijn.suijten, jamipkettunen, Loic Poulain, Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel On Thu 27 May 21:51 CDT 2021, Bjorn Andersson wrote: > On Thu 27 May 14:44 CDT 2021, Konrad Dybcio wrote: > > > From: Loic Poulain <loic.poulain@linaro.org> > > > > Add the operating points capabilities of the kryo CPUs, that can be > > used for frequency scaling. There are two differents operating point > > tables, one for the big cluster and one for the LITTLE cluster. > > > > This frequency scaling support can then be used as a passive cooling > > device (cpufreq cooling device). > > > > Only add nominal fmax for now, since there is no dynamic control of > > VDD APC (s11..) which is statically set at its nominal value. > > > > Original patch link: https://patchwork.kernel.org/project/linux-arm-msm/patch/1595253740-29466-6-git-send-email-loic.poulain@linaro.org/ > > > > Signed-off-by: Loic Poulain <loic.poulain@linaro.org> > > [konrad: drop the thermals part, rebase and remove spaces within <>] > > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > > As reported to Konrad on IRC, booting this causes a lockup before the > kernel reaches init, on one of my db820c boards. Booting with powersave > governor makes this board boot fine and I'm able to switch to > performance after that and at least according to cpufreq we're at full > speed on all 4 cores. But I haven't done any proper stress of the > system to narrow it down further... > > PS. This was tested with next-20210527, your 3 patches, defconfig and > CONFIG_QCOM_CLK_APCC_MSM8996=y > Again as noted on IRC, I reflashed the boot and tz firmware on my db820c and am now able to boot my board with these patches. Regards, Bjorn > Regards, > Bjorn > > > --- > > arch/arm64/boot/dts/qcom/msm8996.dtsi | 234 ++++++++++++++++++++++++++ > > 1 file changed, 234 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > > index 509d5bfec8ad..10e6fecc9e13 100644 > > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > > @@ -8,6 +8,7 @@ > > #include <dt-bindings/clock/qcom,rpmcc.h> > > #include <dt-bindings/power/qcom-rpmpd.h> > > #include <dt-bindings/soc/qcom,apr.h> > > +#include <dt-bindings/thermal/thermal.h> > > > > / { > > interrupt-parent = <&intc>; > > @@ -44,6 +45,9 @@ CPU0: cpu@0 { > > enable-method = "psci"; > > cpu-idle-states = <&CPU_SLEEP_0>; > > capacity-dmips-mhz = <1024>; > > + clocks = <&kryocc 0>; > > + operating-points-v2 = <&cluster0_opp>; > > + #cooling-cells = <2>; > > next-level-cache = <&L2_0>; > > L2_0: l2-cache { > > compatible = "cache"; > > @@ -58,6 +62,9 @@ CPU1: cpu@1 { > > enable-method = "psci"; > > cpu-idle-states = <&CPU_SLEEP_0>; > > capacity-dmips-mhz = <1024>; > > + clocks = <&kryocc 0>; > > + operating-points-v2 = <&cluster0_opp>; > > + #cooling-cells = <2>; > > next-level-cache = <&L2_0>; > > }; > > > > @@ -68,6 +75,9 @@ CPU2: cpu@100 { > > enable-method = "psci"; > > cpu-idle-states = <&CPU_SLEEP_0>; > > capacity-dmips-mhz = <1024>; > > + clocks = <&kryocc 1>; > > + operating-points-v2 = <&cluster1_opp>; > > + #cooling-cells = <2>; > > next-level-cache = <&L2_1>; > > L2_1: l2-cache { > > compatible = "cache"; > > @@ -82,6 +92,9 @@ CPU3: cpu@101 { > > enable-method = "psci"; > > cpu-idle-states = <&CPU_SLEEP_0>; > > capacity-dmips-mhz = <1024>; > > + clocks = <&kryocc 1>; > > + operating-points-v2 = <&cluster1_opp>; > > + #cooling-cells = <2>; > > next-level-cache = <&L2_1>; > > }; > > > > @@ -121,6 +134,227 @@ CPU_SLEEP_0: cpu-sleep-0 { > > }; > > }; > > > > + cluster0_opp: opp_table0 { > > + compatible = "operating-points-v2-kryo-cpu"; > > + nvmem-cells = <&speedbin_efuse>; > > + opp-shared; > > + > > + /* Nominal fmax for now */ > > + opp-307200000 { > > + opp-hz = /bits/ 64 <307200000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-422400000 { > > + opp-hz = /bits/ 64 <422400000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-480000000 { > > + opp-hz = /bits/ 64 <480000000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-556800000 { > > + opp-hz = /bits/ 64 <556800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-652800000 { > > + opp-hz = /bits/ 64 <652800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-729600000 { > > + opp-hz = /bits/ 64 <729600000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-844800000 { > > + opp-hz = /bits/ 64 <844800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-960000000 { > > + opp-hz = /bits/ 64 <960000000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1036800000 { > > + opp-hz = /bits/ 64 <1036800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1113600000 { > > + opp-hz = /bits/ 64 <1113600000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1190400000 { > > + opp-hz = /bits/ 64 <1190400000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1228800000 { > > + opp-hz = /bits/ 64 <1228800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1324800000 { > > + opp-hz = /bits/ 64 <1324800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1401600000 { > > + opp-hz = /bits/ 64 <1401600000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1478400000 { > > + opp-hz = /bits/ 64 <1478400000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1593600000 { > > + opp-hz = /bits/ 64 <1593600000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + }; > > + > > + cluster1_opp: opp_table1 { > > + compatible = "operating-points-v2-kryo-cpu"; > > + nvmem-cells = <&speedbin_efuse>; > > + opp-shared; > > + > > + /* Nominal fmax for now */ > > + opp-307200000 { > > + opp-hz = /bits/ 64 <307200000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-403200000 { > > + opp-hz = /bits/ 64 <403200000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-480000000 { > > + opp-hz = /bits/ 64 <480000000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-556800000 { > > + opp-hz = /bits/ 64 <556800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-652800000 { > > + opp-hz = /bits/ 64 <652800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-729600000 { > > + opp-hz = /bits/ 64 <729600000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-806400000 { > > + opp-hz = /bits/ 64 <806400000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-883200000 { > > + opp-hz = /bits/ 64 <883200000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-940800000 { > > + opp-hz = /bits/ 64 <940800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1036800000 { > > + opp-hz = /bits/ 64 <1036800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1113600000 { > > + opp-hz = /bits/ 64 <1113600000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1190400000 { > > + opp-hz = /bits/ 64 <1190400000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1248000000 { > > + opp-hz = /bits/ 64 <1248000000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1324800000 { > > + opp-hz = /bits/ 64 <1324800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1401600000 { > > + opp-hz = /bits/ 64 <1401600000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1478400000 { > > + opp-hz = /bits/ 64 <1478400000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1555200000 { > > + opp-hz = /bits/ 64 <1555200000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1632000000 { > > + opp-hz = /bits/ 64 <1632000000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1708800000 { > > + opp-hz = /bits/ 64 <1708800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1785600000 { > > + opp-hz = /bits/ 64 <1785600000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1824000000 { > > + opp-hz = /bits/ 64 <1824000000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1920000000 { > > + opp-hz = /bits/ 64 <1920000000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-1996800000 { > > + opp-hz = /bits/ 64 <1996800000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-2073600000 { > > + opp-hz = /bits/ 64 <2073600000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + opp-2150400000 { > > + opp-hz = /bits/ 64 <2150400000>; > > + opp-supported-hw = <0x77>; > > + clock-latency-ns = <200000>; > > + }; > > + }; > > + > > firmware { > > scm { > > compatible = "qcom,scm-msm8996"; > > -- > > 2.31.1 > > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] arch: arm64: dts: msm8996: Rename speedbin node 2021-05-27 19:44 [PATCH 1/2] arch: arm64: dts: msm8996: Rename speedbin node Konrad Dybcio 2021-05-27 19:44 ` [PATCH 2/2] arch: arm64: dts: msm8996: Add CPU opps Konrad Dybcio @ 2021-05-31 21:50 ` patchwork-bot+linux-arm-msm 1 sibling, 0 replies; 5+ messages in thread From: patchwork-bot+linux-arm-msm @ 2021-05-31 21:50 UTC (permalink / raw) To: Konrad Dybcio; +Cc: linux-arm-msm Hello: This series was applied to qcom/linux.git (refs/heads/for-next): On Thu, 27 May 2021 21:44:54 +0200 you wrote: > From: Loic Poulain <loic.poulain@linaro.org> > > The speedbin value blown in the efuse is used to determine is used to > determine the voltage and frequency value for different IPs, including > GPU, CPUs... So it's really not a gpu specific information. > > This patch simply renames 'gpu_speed_bin' node to 'speedbin'. > > [...] Here is the summary with links: - [1/2] arch: arm64: dts: msm8996: Rename speedbin node https://git.kernel.org/qcom/c/af260f1f7dbd - [2/2] arch: arm64: dts: msm8996: Add CPU opps https://git.kernel.org/qcom/c/90173a954a22 You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-05-31 21:50 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-05-27 19:44 [PATCH 1/2] arch: arm64: dts: msm8996: Rename speedbin node Konrad Dybcio 2021-05-27 19:44 ` [PATCH 2/2] arch: arm64: dts: msm8996: Add CPU opps Konrad Dybcio 2021-05-28 2:51 ` Bjorn Andersson 2021-05-31 16:48 ` Bjorn Andersson 2021-05-31 21:50 ` [PATCH 1/2] arch: arm64: dts: msm8996: Rename speedbin node patchwork-bot+linux-arm-msm
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).