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From: Neeraj Upadhyay <neeraju@codeaurora.org>
To: Stephen Boyd <sboyd@kernel.org>,
	tengfeif@codeaurora.org, Linus Walleij <linus.walleij@linaro.org>,
	bjorn.andersson@linaro.org
Cc: LKML <linux-kernel@vger.kernel.org>,
	linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	sramana@codeaurora.org
Subject: Re: Fwd: Re: [PATCH] pinctrl: qcom: Clear status bit on irq_unmask
Date: Mon, 17 Jun 2019 16:05:19 +0530	[thread overview]
Message-ID: <b0fdbcb1-4d5d-5c60-4150-7762a577cd10@codeaurora.org> (raw)
In-Reply-To: <671f87d6-f4a4-6d2c-967b-e1aa0677d83e@codeaurora.org>


> Quoting tengfeif@codeaurora.org (2019-06-11 03:41:26)
>> On 2019-06-10 22:51, Stephen Boyd wrote:
>> > Quoting Linus Walleij (2019-06-07 14:08:10)
>> >> On Fri, May 31, 2019 at 8:52 AM Tengfei Fan 
>> <tengfeif@codeaurora.org> >> wrote:
>> >> >> > The gpio interrupt status bit is getting set after the
>> >> > irq is disabled and causing an immediate interrupt after
>> >> > enablling the irq, so clear status bit on irq_unmask.
>> >> >
>> >> > Signed-off-by: Tengfei Fan <tengfeif@codeaurora.org>
>> >> >> This looks pretty serious, can one of the Qcom maintainers ACK
>> >> this?
>> >> >> Should it be sent to fixes and even stable?
>> >> >> Fixes: tag?
>> >> > > How is the interrupt status bit getting set after the irq is 
>> disabled?
>> > It looks like this is a level type interrupt? I thought that after
>> > commit b55326dc969e ("pinctrl: msm: Really mask level interrupts to
>> > prevent latching") this wouldn't be a problem. Am I wrong, or is qcom
>> > just clearing out patches on drivers and this is the last one that 
>> > needs
>> > to be upstreamed?
>>
>> Your patch(commit b55326dc969e) can cover our issue, and my patch is 
>> no longer needed.
>> Your patch isn't included in our code, so I submitted this patch.
>
> Alright cool. Sounds like this patch can be dropped then and you can
> pick up the patch from upstream into your vendor kernel.
>

Hi Stephen, there is one use case with is not covered by commit 
b55326dc969e (

"pinctrl: msm: Really mask level interrupts to prevent latching"). That 
happens when

gpio line is toggled between i/o mode and interrupt mode :

1. GPIO is configured as irq line. Peripheral raises interrupt.

2. IRQ handler runs and disables the irq line (through wq work).

3. GPIO is configured for input and and data is received from the 
peripheral.

4. Now, when GPIO is re-enabled as irq, we see spurious irq, and there 
isn't

any data received on the gpio line, when it is read back after 
configuring as input.

This can happen for both edge and level interrupts.

Patch https://lkml.org/lkml/2019/6/17/226 tries to cover this use case. 
Can you please

provide your comments?


Thanks

Neeraj

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member of the Code Aurora Forum, hosted by The Linux Foundation


  parent reply	other threads:[~2019-06-17 10:35 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-31  6:51 [PATCH] pinctrl: qcom: Clear status bit on irq_unmask Tengfei Fan
2019-06-07 21:08 ` Linus Walleij
2019-06-10 14:51   ` Stephen Boyd
2019-06-11 10:41     ` tengfeif
2019-06-11 18:51       ` Stephen Boyd
     [not found]         ` <671f87d6-f4a4-6d2c-967b-e1aa0677d83e@codeaurora.org>
2019-06-17 10:35           ` Neeraj Upadhyay [this message]
2019-06-17 11:50             ` Fwd: " Linus Walleij
2019-06-17 13:22               ` Neeraj Upadhyay

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