[PATCH V3 0/4] Enable crypto for ipq9574

[PATCH V3 0/4] Enable crypto for ipq9574

[Anusha Rao]

Update GCC driver to include clocks required for crypto.
Enable crypto nodes in ipq9574.

DTS patch depends on the below series
https://lore.kernel.org/linux-arm-msm/20230517072806.13170-1-quic_kathirav@quicinc.com/

Changes in V3:
	Detailed change logs are added to the respective patches.

V2 can be found at:
https://lore.kernel.org/linux-arm-msm/20230515150722.12196-1-quic_anusha@quicinc.com/

V1 can be found at
https://lore.kernel.org/linux-arm-msm/20230512090134.9811-1-quic_anusha@quicinc.com/

Anusha Rao (4):
  dt-bindings: clock: Add crypto clock and reset definitions
  clk: qcom: gcc-ipq9574: Enable crypto clocks
  dt-bindings: qcom-qce: add SoC compatible string for ipq9574
  arm64: dts: qcom: ipq9574: Enable crypto nodes

 .../devicetree/bindings/crypto/qcom-qce.yaml  |  1 +
 arch/arm64/boot/dts/qcom/ipq9574.dtsi         | 20 ++++++
 drivers/clk/qcom/gcc-ipq9574.c                | 72 +++++++++++++++++++
 include/dt-bindings/clock/qcom,ipq9574-gcc.h  |  4 ++
 include/dt-bindings/reset/qcom,ipq9574-gcc.h  |  1 +
 5 files changed, 98 insertions(+)


base-commit: aabe491169befbe5481144acf575a0260939764a
-- 
2.17.1

[PATCH V3 1/4] dt-bindings: clock: Add crypto clock and reset definitions

[Anusha Rao]

Add crypto clock and reset ID definitions for ipq9574.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
---
 Changes in V3:
	- Added GCC prefix to CRYPTO_CLK_SRC.
	- Picked up Acked-by tag.

 include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++
 include/dt-bindings/reset/qcom,ipq9574-gcc.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index 5a2961bfe893..b32a7aa65349 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -210,4 +210,8 @@
 #define GCC_SNOC_PCIE1_1LANE_S_CLK			201
 #define GCC_SNOC_PCIE2_2LANE_S_CLK			202
 #define GCC_SNOC_PCIE3_2LANE_S_CLK			203
+#define GCC_CRYPTO_CLK_SRC				204
+#define GCC_CRYPTO_CLK					205
+#define GCC_CRYPTO_AXI_CLK				206
+#define GCC_CRYPTO_AHB_CLK				207
 #endif
diff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h b/include/dt-bindings/reset/qcom,ipq9574-gcc.h
index d01dc6a24cf1..c709d103673d 100644
--- a/include/dt-bindings/reset/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h
@@ -160,5 +160,6 @@
 #define GCC_WCSS_Q6_BCR						151
 #define GCC_WCSS_Q6_TBU_BCR					152
 #define GCC_TCSR_BCR						153
+#define GCC_CRYPTO_BCR						154
 
 #endif
-- 
2.17.1

[PATCH V3 2/4] clk: qcom: gcc-ipq9574: Enable crypto clocks

[Anusha Rao]

Enable the clocks required for crypto operation.

Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
---
 Changes in V3:
	- Added GCC prefix to CRYPTO_CLK_SRC.

 drivers/clk/qcom/gcc-ipq9574.c | 72 ++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 7b0505f5c255..73663168d72a 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -728,6 +728,41 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 	},
 };
 
+static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = {
+	F(160000000, P_GPLL0, 5, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 gcc_crypto_clk_src = {
+	.cmd_rcgr = 0x16004,
+	.freq_tbl = ftbl_gcc_crypto_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(const struct clk_init_data) {
+		.name = "gcc_crypto_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_crypto_clk = {
+	.halt_reg = 0x1600c,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x0b004,
+		.enable_mask = BIT(14),
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_crypto_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+				&gcc_crypto_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_apss_ahb_clk = {
 	.halt_reg = 0x24018,
 	.halt_check = BRANCH_HALT_VOTED,
@@ -2071,6 +2106,38 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 	},
 };
 
+static struct clk_branch gcc_crypto_axi_clk = {
+	.halt_reg = 0x16010,
+	.clkr = {
+		.enable_reg = 0x16010,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_crypto_axi_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+				&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_crypto_ahb_clk = {
+	.halt_reg = 0x16014,
+	.clkr = {
+		.enable_reg = 0x16014,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_crypto_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+				&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_nsscfg_clk = {
 	.halt_reg = 0x1702c,
 	.clkr = {
@@ -4036,6 +4103,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
 	[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
 	[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
 	[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
+	[GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr,
+	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
+	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
+	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq9574_resets[] = {
@@ -4193,6 +4264,7 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
 	[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
 	[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
 	[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
+	[GCC_CRYPTO_BCR] = { 0x16000, 0 },
 };
 
 static const struct of_device_id gcc_ipq9574_match_table[] = {
-- 
2.17.1

[PATCH V3 3/4] dt-bindings: qcom-qce: add SoC compatible string for ipq9574

[Anusha Rao]

Document the compatible string for ipq9574.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
---
 Changes in V3:
	- Picked up Acked-by tag.

 Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index e375bd981300..0d1deae06e2d 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -28,6 +28,7 @@ properties:
           - enum:
               - qcom,ipq6018-qce
               - qcom,ipq8074-qce
+              - qcom,ipq9574-qce
               - qcom,msm8996-qce
               - qcom,sdm845-qce
           - const: qcom,ipq4019-qce
-- 
2.17.1

[PATCH V3 4/4] arm64: dts: qcom: ipq9574: Enable crypto nodes

[Anusha Rao]

Enable crypto support for ipq9574.

Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
---
 Changes in V3:
	- No change.

 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index fea15f3cf910..6e52d35a6a15 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -123,6 +123,26 @@
 			clock-names = "core";
 		};
 
+		cryptobam: dma-controller@704000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x00704000 0x20000>;
+			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			qcom,ee = <1>;
+			qcom,controlled-remotely;
+		};
+
+		crypto: crypto@73a000 {
+			compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
+			reg = <0x0073a000 0x6000>;
+			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
+				 <&gcc GCC_CRYPTO_AXI_CLK>,
+				 <&gcc GCC_CRYPTO_CLK>;
+			clock-names = "iface", "bus", "core";
+			dmas = <&cryptobam 2>, <&cryptobam 3>;
+			dma-names = "rx", "tx";
+		};
+
 		tlmm: pinctrl@1000000 {
 			compatible = "qcom,ipq9574-tlmm";
 			reg = <0x01000000 0x300000>;
-- 
2.17.1

Re: [PATCH V3 4/4] arm64: dts: qcom: ipq9574: Enable crypto nodes

[Krzysztof Kozlowski]

On 18/05/2023 16:11, Anusha Rao wrote:
> Enable crypto support for ipq9574.
> 
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> ---

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH V3 1/4] dt-bindings: clock: Add crypto clock and reset definitions

[bhupesh.sharma]

On 5/18/23 7:41 PM, Anusha Rao <quic_anusha@quicinc.com> wrote:
> Add crypto clock and reset ID definitions for ipq9574.
> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> ---
>   Changes in V3:
> 	- Added GCC prefix to CRYPTO_CLK_SRC.
> 	- Picked up Acked-by tag.
> 
>   include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++
>   include/dt-bindings/reset/qcom,ipq9574-gcc.h | 1 +
>   2 files changed, 5 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> index 5a2961bfe893..b32a7aa65349 100644
> --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> @@ -210,4 +210,8 @@
>   #define GCC_SNOC_PCIE1_1LANE_S_CLK			201
>   #define GCC_SNOC_PCIE2_2LANE_S_CLK			202
>   #define GCC_SNOC_PCIE3_2LANE_S_CLK			203
> +#define GCC_CRYPTO_CLK_SRC				204
> +#define GCC_CRYPTO_CLK					205
> +#define GCC_CRYPTO_AXI_CLK				206
> +#define GCC_CRYPTO_AHB_CLK				207
>   #endif
> diff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h b/include/dt-bindings/reset/qcom,ipq9574-gcc.h
> index d01dc6a24cf1..c709d103673d 100644
> --- a/include/dt-bindings/reset/qcom,ipq9574-gcc.h
> +++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h
> @@ -160,5 +160,6 @@
>   #define GCC_WCSS_Q6_BCR						151
>   #define GCC_WCSS_Q6_TBU_BCR					152
>   #define GCC_TCSR_BCR						153
> +#define GCC_CRYPTO_BCR						154
>   
>   #endif

Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>

Thanks.

Re: [PATCH V3 3/4] dt-bindings: qcom-qce: add SoC compatible string for ipq9574

[bhupesh.sharma]

On 5/18/23 7:41 PM, Anusha Rao <quic_anusha@quicinc.com> wrote:
> Document the compatible string for ipq9574.
> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> ---
>   Changes in V3:
> 	- Picked up Acked-by tag.
> 
>   Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> index e375bd981300..0d1deae06e2d 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> @@ -28,6 +28,7 @@ properties:
>             - enum:
>                 - qcom,ipq6018-qce
>                 - qcom,ipq8074-qce
> +              - qcom,ipq9574-qce
>                 - qcom,msm8996-qce
>                 - qcom,sdm845-qce
>             - const: qcom,ipq4019-qce

Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>

Thanks.

Re: [PATCH V3 4/4] arm64: dts: qcom: ipq9574: Enable crypto nodes

[bhupesh.sharma]

On 5/18/23 7:41 PM, Anusha Rao <quic_anusha@quicinc.com> wrote:
> Enable crypto support for ipq9574.
> 
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> ---
>   Changes in V3:
> 	- No change.
> 
>   arch/arm64/boot/dts/qcom/ipq9574.dtsi | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index fea15f3cf910..6e52d35a6a15 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -123,6 +123,26 @@
>   			clock-names = "core";
>   		};
>   
> +		cryptobam: dma-controller@704000 {
> +			compatible = "qcom,bam-v1.7.0";

Please confirm if this is "qcom,bam-v1.7.4" or "qcom,bam-v1.7.0". If "qcom,bam-v1.7.4" please use the newer compatible format.

Thanks,
Bhupesh

> +			reg = <0x00704000 0x20000>;
> +			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> +			#dma-cells = <1>;
> +			qcom,ee = <1>;
> +			qcom,controlled-remotely;
> +		};
> +
> +		crypto: crypto@73a000 {
> +			compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
> +			reg = <0x0073a000 0x6000>;
> +			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
> +				 <&gcc GCC_CRYPTO_AXI_CLK>,
> +				 <&gcc GCC_CRYPTO_CLK>;
> +			clock-names = "iface", "bus", "core";
> +			dmas = <&cryptobam 2>, <&cryptobam 3>;
> +			dma-names = "rx", "tx";
> +		};
> +
>   		tlmm: pinctrl@1000000 {
>   			compatible = "qcom,ipq9574-tlmm";
>   			reg = <0x01000000 0x300000>;
> 

Re: [PATCH V3 2/4] clk: qcom: gcc-ipq9574: Enable crypto clocks

[bhupesh.sharma]

On 5/18/23 7:41 PM, Anusha Rao <quic_anusha@quicinc.com> wrote:
> Enable the clocks required for crypto operation.
> 
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> ---
>   Changes in V3:
> 	- Added GCC prefix to CRYPTO_CLK_SRC.
> 
>   drivers/clk/qcom/gcc-ipq9574.c | 72 ++++++++++++++++++++++++++++++++++
>   1 file changed, 72 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> index 7b0505f5c255..73663168d72a 100644
> --- a/drivers/clk/qcom/gcc-ipq9574.c
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -728,6 +728,41 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
>   	},
>   };
>   
> +static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = {
> +	F(160000000, P_GPLL0, 5, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gcc_crypto_clk_src = {
> +	.cmd_rcgr = 0x16004,
> +	.freq_tbl = ftbl_gcc_crypto_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> +	.clkr.hw.init = &(const struct clk_init_data) {
> +		.name = "gcc_crypto_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_crypto_clk = {
> +	.halt_reg = 0x1600c,
> +	.halt_check = BRANCH_HALT_VOTED,
> +	.clkr = {
> +		.enable_reg = 0x0b004,
> +		.enable_mask = BIT(14),
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_crypto_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +				&gcc_crypto_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
>   static struct clk_branch gcc_apss_ahb_clk = {
>   	.halt_reg = 0x24018,
>   	.halt_check = BRANCH_HALT_VOTED,
> @@ -2071,6 +2106,38 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
>   	},
>   };
>   
> +static struct clk_branch gcc_crypto_axi_clk = {
> +	.halt_reg = 0x16010,
> +	.clkr = {
> +		.enable_reg = 0x16010,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_crypto_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +				&pcnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_crypto_ahb_clk = {
> +	.halt_reg = 0x16014,
> +	.clkr = {
> +		.enable_reg = 0x16014,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_crypto_ahb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +				&pcnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
>   static struct clk_branch gcc_nsscfg_clk = {
>   	.halt_reg = 0x1702c,
>   	.clkr = {
> @@ -4036,6 +4103,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
>   	[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
>   	[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
>   	[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
> +	[GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr,
> +	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
> +	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
> +	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
>   };

Can we please add these in alphabetical order. For e.g. here these entries would follow those for '[GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },'

>   static const struct qcom_reset_map gcc_ipq9574_resets[] = {
> @@ -4193,6 +4264,7 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
>   	[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
>   	[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
>   	[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
> +	[GCC_CRYPTO_BCR] = { 0x16000, 0 },

Same as above.

With the above addressed:
Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>

Thanks.

>   };
>   
>   static const struct of_device_id gcc_ipq9574_match_table[] = {
> 

Re: [PATCH V3 4/4] arm64: dts: qcom: ipq9574: Enable crypto nodes

[Anusha Canchi]

On 5/22/2023 2:23 PM, bhupesh.sharma@linaro.org wrote:
> On 5/18/23 7:41 PM, Anusha Rao <quic_anusha@quicinc.com> wrote:
>> Enable crypto support for ipq9574.
>>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> ---
>>   Changes in V3:
>>     - No change.
>>
>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi | 20 ++++++++++++++++++++
>>   1 file changed, 20 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi 
>> b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index fea15f3cf910..6e52d35a6a15 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -123,6 +123,26 @@
>>               clock-names = "core";
>>           };
>>   +        cryptobam: dma-controller@704000 {
>> +            compatible = "qcom,bam-v1.7.0";
>
> Please confirm if this is "qcom,bam-v1.7.4" or "qcom,bam-v1.7.0". If 
> "qcom,bam-v1.7.4" please use the newer compatible format.
Sure, will update.

Thanks,
Anusha
>
> Thanks,
> Bhupesh
>
>> +            reg = <0x00704000 0x20000>;
>> +            interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
>> +            #dma-cells = <1>;
>> +            qcom,ee = <1>;
>> +            qcom,controlled-remotely;
>> +        };
>> +
>> +        crypto: crypto@73a000 {
>> +            compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", 
>> "qcom,qce";
>> +            reg = <0x0073a000 0x6000>;
>> +            clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
>> +                 <&gcc GCC_CRYPTO_AXI_CLK>,
>> +                 <&gcc GCC_CRYPTO_CLK>;
>> +            clock-names = "iface", "bus", "core";
>> +            dmas = <&cryptobam 2>, <&cryptobam 3>;
>> +            dma-names = "rx", "tx";
>> +        };
>> +
>>           tlmm: pinctrl@1000000 {
>>               compatible = "qcom,ipq9574-tlmm";
>>               reg = <0x01000000 0x300000>;
>>

Re: [PATCH V3 2/4] clk: qcom: gcc-ipq9574: Enable crypto clocks

[Anusha Canchi]

On 5/22/2023 2:28 PM, bhupesh.sharma@linaro.org wrote:
>
>
> On 5/18/23 7:41 PM, Anusha Rao <quic_anusha@quicinc.com> wrote:
>> Enable the clocks required for crypto operation.
>>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> ---
>>   Changes in V3:
>>     - Added GCC prefix to CRYPTO_CLK_SRC.
>>
>>   drivers/clk/qcom/gcc-ipq9574.c | 72 ++++++++++++++++++++++++++++++++++
>>   1 file changed, 72 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c 
>> b/drivers/clk/qcom/gcc-ipq9574.c
>> index 7b0505f5c255..73663168d72a 100644
>> --- a/drivers/clk/qcom/gcc-ipq9574.c
>> +++ b/drivers/clk/qcom/gcc-ipq9574.c
>> @@ -728,6 +728,41 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
>>       },
>>   };
>>   +static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = {
>> +    F(160000000, P_GPLL0, 5, 0, 0),
>> +    { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_crypto_clk_src = {
>> +    .cmd_rcgr = 0x16004,
>> +    .freq_tbl = ftbl_gcc_crypto_clk_src,
>> +    .hid_width = 5,
>> +    .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
>> +    .clkr.hw.init = &(const struct clk_init_data) {
>> +        .name = "gcc_crypto_clk_src",
>> +        .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
>> +        .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
>> +        .ops = &clk_rcg2_ops,
>> +    },
>> +};
>> +
>> +static struct clk_branch gcc_crypto_clk = {
>> +    .halt_reg = 0x1600c,
>> +    .halt_check = BRANCH_HALT_VOTED,
>> +    .clkr = {
>> +        .enable_reg = 0x0b004,
>> +        .enable_mask = BIT(14),
>> +        .hw.init = &(const struct clk_init_data) {
>> +            .name = "gcc_crypto_clk",
>> +            .parent_hws = (const struct clk_hw *[]) {
>> +                &gcc_crypto_clk_src.clkr.hw },
>> +            .num_parents = 1,
>> +            .flags = CLK_SET_RATE_PARENT,
>> +            .ops = &clk_branch2_ops,
>> +        },
>> +    },
>> +};
>> +
>>   static struct clk_branch gcc_apss_ahb_clk = {
>>       .halt_reg = 0x24018,
>>       .halt_check = BRANCH_HALT_VOTED,
>> @@ -2071,6 +2106,38 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
>>       },
>>   };
>>   +static struct clk_branch gcc_crypto_axi_clk = {
>> +    .halt_reg = 0x16010,
>> +    .clkr = {
>> +        .enable_reg = 0x16010,
>> +        .enable_mask = BIT(0),
>> +        .hw.init = &(const struct clk_init_data) {
>> +            .name = "gcc_crypto_axi_clk",
>> +            .parent_hws = (const struct clk_hw *[]) {
>> +                &pcnoc_bfdcd_clk_src.clkr.hw },
>> +            .num_parents = 1,
>> +            .flags = CLK_SET_RATE_PARENT,
>> +            .ops = &clk_branch2_ops,
>> +        },
>> +    },
>> +};
>> +
>> +static struct clk_branch gcc_crypto_ahb_clk = {
>> +    .halt_reg = 0x16014,
>> +    .clkr = {
>> +        .enable_reg = 0x16014,
>> +        .enable_mask = BIT(0),
>> +        .hw.init = &(const struct clk_init_data) {
>> +            .name = "gcc_crypto_ahb_clk",
>> +            .parent_hws = (const struct clk_hw *[]) {
>> +                &pcnoc_bfdcd_clk_src.clkr.hw },
>> +            .num_parents = 1,
>> +            .flags = CLK_SET_RATE_PARENT,
>> +            .ops = &clk_branch2_ops,
>> +        },
>> +    },
>> +};
>> +
>>   static struct clk_branch gcc_nsscfg_clk = {
>>       .halt_reg = 0x1702c,
>>       .clkr = {
>> @@ -4036,6 +4103,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
>>       [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
>>       [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
>>       [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
>> +    [GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr,
>> +    [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
>> +    [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
>> +    [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
>>   };
>
> Can we please add these in alphabetical order. For e.g. here these 
> entries would follow those for '[GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },'
Okay, will update.

Thanks,
Anusha
>
>>   static const struct qcom_reset_map gcc_ipq9574_resets[] = {
>> @@ -4193,6 +4264,7 @@ static const struct qcom_reset_map 
>> gcc_ipq9574_resets[] = {
>>       [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
>>       [GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
>>       [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
>> +    [GCC_CRYPTO_BCR] = { 0x16000, 0 },
>
> Same as above.
Okay.

Thanks,
Anusha
>
> With the above addressed:
> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
>
> Thanks.
>
>>   };
>>     static const struct of_device_id gcc_ipq9574_match_table[] = {
>>