From: abhinavk@codeaurora.org
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Jonathan Marek <jonathan@marek.ca>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org
Subject: Re: [Freedreno] [PATCH v3 15/25] drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers
Date: Mon, 29 Mar 2021 17:01:11 -0700 [thread overview]
Message-ID: <d09bbd7d79f8d99fc906e22be56d8d0f@codeaurora.org> (raw)
In-Reply-To: <20210327110305.3289784-16-dmitry.baryshkov@linaro.org>
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
> These drivers do not use vco_delay variable, so drop it from all of
> them.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ----
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 ---
> 3 files changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index e0df12a841b2..bfb96d87d1d7 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -99,7 +99,6 @@ struct dsi_pll_10nm {
> /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */
> spinlock_t postdiv_lock;
>
> - int vco_delay;
> struct dsi_pll_config pll_configuration;
> struct dsi_pll_regs reg_setup;
>
> @@ -771,8 +770,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy
> *phy)
> pll = &pll_10nm->base;
> pll->cfg = phy->cfg;
>
> - pll_10nm->vco_delay = 1;
> -
> ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
> if (ret) {
> DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 7fe7c8348b42..434d02ffa7fe 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -122,8 +122,6 @@ struct dsi_pll_14nm {
> void __iomem *phy_cmn_mmio;
> void __iomem *mmio;
>
> - int vco_delay;
> -
> struct dsi_pll_input in;
> struct dsi_pll_output out;
>
> @@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy
> *phy)
> pll = &pll_14nm->base;
> pll->cfg = phy->cfg;
>
> - pll_14nm->vco_delay = 1;
> -
> ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
> if (ret) {
> DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index e6c8040e1bd3..f760904efac9 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -99,7 +99,6 @@ struct dsi_pll_7nm {
> /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
> spinlock_t postdiv_lock;
>
> - int vco_delay;
> struct dsi_pll_config pll_configuration;
> struct dsi_pll_regs reg_setup;
>
> @@ -796,8 +795,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy
> *phy)
> pll = &pll_7nm->base;
> pll->cfg = phy->cfg;
>
> - pll_7nm->vco_delay = 1;
> -
> ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
> if (ret) {
> DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
next prev parent reply other threads:[~2021-03-30 0:01 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-27 11:02 [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 01/25] clk: fixed: add devm helper for clk_hw_register_fixed_factor() Dmitry Baryshkov
2021-03-29 21:55 ` abhinavk
2021-03-27 11:02 ` [PATCH v3 02/25] clk: mux: provide devm_clk_hw_register_mux() Dmitry Baryshkov
2021-03-30 0:46 ` Stephen Boyd
2021-03-27 11:02 ` [PATCH v3 03/25] clk: divider: add devm_clk_hw_register_divider Dmitry Baryshkov
2021-03-30 0:46 ` Stephen Boyd
2021-03-27 11:02 ` [PATCH v3 04/25] drm/msm/dsi: replace PHY's init callback with configurable data Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 06/25] drm/msm/dsi: drop multiple pll enable_seq support Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 07/25] drm/msm/dsi: move all PLL callbacks into PHY config struct Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 08/25] drm/msm/dsi: drop global msm_dsi_phy_type enumaration Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 09/25] drm/msm/dsi: move min/max PLL rate to phy config Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 10/25] drm/msm/dsi: remove msm_dsi_pll_set_usecase Dmitry Baryshkov
2021-03-27 11:02 ` [PATCH v3 11/25] drm/msm/dsi: push provided clocks handling into a generic code Dmitry Baryshkov
2021-03-29 22:12 ` [Freedreno] " abhinavk
2021-03-27 11:02 ` [PATCH v3 12/25] drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks Dmitry Baryshkov
2021-03-29 23:33 ` [Freedreno] " abhinavk
2021-03-30 0:49 ` Stephen Boyd
2021-03-27 11:02 ` [PATCH v3 13/25] drm/msm/dsi: use devm_of_clk_add_hw_provider Dmitry Baryshkov
2021-03-29 23:43 ` [Freedreno] " abhinavk
2021-03-30 0:50 ` Stephen Boyd
2021-03-27 11:02 ` [PATCH v3 14/25] drm/msm/dsi: make save/restore_state phy-level functions Dmitry Baryshkov
2021-03-29 23:51 ` [Freedreno] " abhinavk
2021-03-27 11:02 ` [PATCH v3 15/25] drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers Dmitry Baryshkov
2021-03-30 0:01 ` abhinavk [this message]
2021-03-27 11:02 ` [PATCH v3 16/25] drm/msm/dpu: simplify vco_delay handling in dsi_phy_28nm driver Dmitry Baryshkov
2021-03-30 0:03 ` [Freedreno] " abhinavk
2021-03-27 11:02 ` [PATCH v3 17/25] drm/msi/dsi: inline msm_dsi_pll_helper_clk_prepare/unprepare Dmitry Baryshkov
2021-03-30 0:50 ` [Freedreno] " abhinavk
2021-03-27 11:02 ` [PATCH v3 18/25] drm/msm/dsi: make save_state/restore_state callbacks accept msm_dsi_phy Dmitry Baryshkov
2021-03-30 3:09 ` abhinavk
2021-03-27 11:02 ` [PATCH v3 19/25] drm/msm/dsi: drop msm_dsi_pll abstracton Dmitry Baryshkov
2021-03-30 3:13 ` [Freedreno] " abhinavk
2021-03-30 3:35 ` abhinavk
2021-03-27 11:03 ` [PATCH v3 20/25] drm/msm/dsi: drop PLL accessor functions Dmitry Baryshkov
2021-03-30 3:16 ` [Freedreno] " abhinavk
2021-03-27 11:03 ` [PATCH v3 21/25] drm/msm/dsi: move ioremaps to dsi_phy_driver_probe Dmitry Baryshkov
2021-03-30 3:18 ` [Freedreno] " abhinavk
2021-03-27 11:03 ` [PATCH v3 22/25] drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances Dmitry Baryshkov
2021-03-30 3:23 ` abhinavk
2021-03-27 11:03 ` [PATCH v3 23/25] drm/msm/dsi: remove temp data from global pll structure Dmitry Baryshkov
2021-03-30 3:26 ` [Freedreno] " abhinavk
2021-03-30 15:23 ` Dmitry Baryshkov
2021-03-27 11:03 ` [PATCH v3 24/25] drm/msm/dsi: inline msm_dsi_phy_set_src_pll Dmitry Baryshkov
2021-03-30 3:34 ` [Freedreno] " abhinavk
2021-03-30 13:42 ` Dmitry Baryshkov
2021-03-30 17:44 ` abhinavk
2021-03-27 11:03 ` [PATCH v3 25/25] drm/msm/dsi: stop passing src_pll_id to the phy_enable call Dmitry Baryshkov
2021-03-30 19:29 ` [Freedreno] " abhinavk
2021-03-30 1:31 ` [PATCH v3 00/25] drm/msm/dsi: refactor MSM DSI PHY/PLL drivers Stephen Boyd
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