Re: [Freedreno] [PATCH v3 16/25] drm/msm/dpu: simplify vco_delay handling in dsi_phy_28nm driver

[abhinavk@codeaurora.org]

On 2021-03-27 04:02, Dmitry Baryshkov wrote:
> Instead of setting the variable and then using it just in the one 
> place,
> determine vco_delay directly at the PLL configuration time.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
The subject line should still be "drm/msm/dsi" and not "drm/msm/dpu".
Once thats fixed, please apply
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 12 ++++--------
>  1 file changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index 3e9b7949b038..ed369eb18e9d 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -72,8 +72,6 @@ struct dsi_pll_28nm {
>  	struct platform_device *pdev;
>  	void __iomem *mmio;
> 
> -	int vco_delay;
> -
>  	struct pll_28nm_cached_state cached_state;
>  };
> 
> @@ -212,8 +210,10 @@ static int dsi_pll_28nm_clk_set_rate(struct
> clk_hw *hw, unsigned long rate,
>  	pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
> 
>  	/* Add hardware recommended delay for correct PLL configuration */
> -	if (pll_28nm->vco_delay)
> -		udelay(pll_28nm->vco_delay);
> +	if (pll->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> +		udelay(1000);
> +	else
> +		udelay(1);
> 
>  	pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg);
>  	pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00);
> @@ -580,10 +580,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy 
> *phy)
> 
>  	pll = &pll_28nm->base;
>  	pll->cfg = phy->cfg;
> -	if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
> -		pll_28nm->vco_delay = 1000;
> -	else
> -		pll_28nm->vco_delay = 1;
> 
>  	ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
>  	if (ret) {