* [PATCH v2 1/8] dt-bindings: display: msm: dsi-controller-main: restore assigned-clocks
2021-07-09 21:07 [PATCH v2 0/8] dsi: rework clock parents and timing handling Dmitry Baryshkov
@ 2021-07-09 21:07 ` Dmitry Baryshkov
2021-07-15 16:15 ` Rob Herring
2021-07-09 21:07 ` [PATCH v2 2/8] arm64: dts: qcom: sc7180: assign DSI clock source parents Dmitry Baryshkov
` (6 subsequent siblings)
7 siblings, 1 reply; 11+ messages in thread
From: Dmitry Baryshkov @ 2021-07-09 21:07 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar,
Rob Herring
Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
linux-arm-msm, dri-devel, freedreno, devicetree
Restore the assgined-clocks and assigned-clock-parents properties that
were lost during the txt -> YAML conversion.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../display/msm/dsi-controller-main.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index 76348b71f736..760eec6b0db1 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -64,6 +64,18 @@ properties:
Indicates if the DSI controller is driving a panel which needs
2 DSI links.
+ assigned-clocks:
+ minItems: 2
+ maxItems: 2
+ description: |
+ Parents of "byte" and "pixel" for the given platform.
+
+ assigned-clock-parents:
+ minItems: 2
+ maxItems: 2
+ description: |
+ The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
+
power-domains:
maxItems: 1
@@ -119,6 +131,8 @@ required:
- clock-names
- phys
- phy-names
+ - assigned-clocks
+ - assigned-clock-parents
- power-domains
- operating-points-v2
- ports
@@ -159,6 +173,9 @@ examples:
phys = <&dsi0_phy>;
phy-names = "dsi";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
+
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&dsi_opp_table>;
--
2.30.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/8] dt-bindings: display: msm: dsi-controller-main: restore assigned-clocks
2021-07-09 21:07 ` [PATCH v2 1/8] dt-bindings: display: msm: dsi-controller-main: restore assigned-clocks Dmitry Baryshkov
@ 2021-07-15 16:15 ` Rob Herring
0 siblings, 0 replies; 11+ messages in thread
From: Rob Herring @ 2021-07-15 16:15 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Daniel Vetter, devicetree, dri-devel, Rob Herring,
Sean Paul, Abhinav Kumar, David Airlie, Bjorn Andersson,
Stephen Boyd, Rob Clark, linux-arm-msm, Andy Gross,
Jonathan Marek
On Sat, 10 Jul 2021 00:07:22 +0300, Dmitry Baryshkov wrote:
> Restore the assgined-clocks and assigned-clock-parents properties that
> were lost during the txt -> YAML conversion.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../display/msm/dsi-controller-main.yaml | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 2/8] arm64: dts: qcom: sc7180: assign DSI clock source parents
2021-07-09 21:07 [PATCH v2 0/8] dsi: rework clock parents and timing handling Dmitry Baryshkov
2021-07-09 21:07 ` [PATCH v2 1/8] dt-bindings: display: msm: dsi-controller-main: restore assigned-clocks Dmitry Baryshkov
@ 2021-07-09 21:07 ` Dmitry Baryshkov
2021-07-09 21:07 ` [PATCH v2 3/8] arm64: dts: qcom: sdm845: " Dmitry Baryshkov
` (5 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2021-07-09 21:07 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar,
Rob Herring
Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
linux-arm-msm, dri-devel, freedreno, devicetree
Assign DSI clock source parents to DSI PHY clocks.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 6228ba2d8513..bc765598d24e 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3081,6 +3081,9 @@ dsi0: dsi@ae94000 {
"iface",
"bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
+
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SC7180_CX>;
--
2.30.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 3/8] arm64: dts: qcom: sdm845: assign DSI clock source parents
2021-07-09 21:07 [PATCH v2 0/8] dsi: rework clock parents and timing handling Dmitry Baryshkov
2021-07-09 21:07 ` [PATCH v2 1/8] dt-bindings: display: msm: dsi-controller-main: restore assigned-clocks Dmitry Baryshkov
2021-07-09 21:07 ` [PATCH v2 2/8] arm64: dts: qcom: sc7180: assign DSI clock source parents Dmitry Baryshkov
@ 2021-07-09 21:07 ` Dmitry Baryshkov
2021-07-09 21:07 ` [PATCH v2 4/8] arm64: dts: qcom: sdm845-mtp: " Dmitry Baryshkov
` (4 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2021-07-09 21:07 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar,
Rob Herring
Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
linux-arm-msm, dri-devel, freedreno, devicetree
Assign DSI clock source parents to DSI PHY clocks.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0a86fe71a66d..e13097ef271a 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4260,6 +4260,9 @@ dsi0: dsi@ae94000 {
"core",
"iface",
"bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SDM845_CX>;
@@ -4326,6 +4329,9 @@ dsi1: dsi@ae96000 {
"core",
"iface",
"bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SDM845_CX>;
--
2.30.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 4/8] arm64: dts: qcom: sdm845-mtp: assign DSI clock source parents
2021-07-09 21:07 [PATCH v2 0/8] dsi: rework clock parents and timing handling Dmitry Baryshkov
` (2 preceding siblings ...)
2021-07-09 21:07 ` [PATCH v2 3/8] arm64: dts: qcom: sdm845: " Dmitry Baryshkov
@ 2021-07-09 21:07 ` Dmitry Baryshkov
2021-07-09 21:07 ` [PATCH v2 5/8] arm64: dts: qcom: sm8250: " Dmitry Baryshkov
` (3 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2021-07-09 21:07 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar,
Rob Herring
Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
linux-arm-msm, dri-devel, freedreno, devicetree
Assign DSI clock source parents to DSI PHY clocks.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 1372fe8601f5..9e550e3ad678 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -413,6 +413,9 @@ &dsi1 {
qcom,dual-dsi-mode;
+ /* DSI1 is slave, so use DSI0 clocks */
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
ports {
port@1 {
endpoint {
--
2.30.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 5/8] arm64: dts: qcom: sm8250: assign DSI clock source parents
2021-07-09 21:07 [PATCH v2 0/8] dsi: rework clock parents and timing handling Dmitry Baryshkov
` (3 preceding siblings ...)
2021-07-09 21:07 ` [PATCH v2 4/8] arm64: dts: qcom: sdm845-mtp: " Dmitry Baryshkov
@ 2021-07-09 21:07 ` Dmitry Baryshkov
2021-07-09 21:07 ` [PATCH v2 6/8] drm/msm/dsi: stop setting clock parents manually Dmitry Baryshkov
` (2 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2021-07-09 21:07 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar,
Rob Herring
Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
linux-arm-msm, dri-devel, freedreno, devicetree
Assign DSI clock source parents to DSI PHY clocks.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 4c0de12aaba6..69bf2e90cbce 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2491,6 +2491,9 @@ dsi0: dsi@ae94000 {
"iface",
"bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
@@ -2558,6 +2561,9 @@ dsi1: dsi@ae96000 {
"iface",
"bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
--
2.30.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 6/8] drm/msm/dsi: stop setting clock parents manually
2021-07-09 21:07 [PATCH v2 0/8] dsi: rework clock parents and timing handling Dmitry Baryshkov
` (4 preceding siblings ...)
2021-07-09 21:07 ` [PATCH v2 5/8] arm64: dts: qcom: sm8250: " Dmitry Baryshkov
@ 2021-07-09 21:07 ` Dmitry Baryshkov
2021-10-03 2:13 ` Dmitry Baryshkov
2021-07-09 21:07 ` [PATCH v2 7/8] drm/msm/dsi: phy: use of_device_get_match_data Dmitry Baryshkov
2021-07-09 21:07 ` [PATCH v2 8/8] drm/msm/dsi: drop msm_dsi_phy_get_shared_timings Dmitry Baryshkov
7 siblings, 1 reply; 11+ messages in thread
From: Dmitry Baryshkov @ 2021-07-09 21:07 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar,
Rob Herring
Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
linux-arm-msm, dri-devel, freedreno, devicetree
There is no reason to set clock parents manually, use device tree to
assign DSI/display clock parents to DSI PHY clocks. Dropping this manual
setup allows us to drop repeating code and to move registration of hw
clock providers to generic place.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 2 --
drivers/gpu/drm/msm/dsi/dsi_host.c | 51 ---------------------------
drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 ---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 11 ------
4 files changed, 69 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 9b8e9b07eced..1f0ec78c6b05 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -170,8 +170,6 @@ void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
struct msm_dsi_phy_shared_timings *shared_timing);
void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
enum msm_dsi_phy_usecase uc);
-int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
- struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy);
int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy);
void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index ed504fe5074f..1fa6ee12395b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -2219,57 +2219,6 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
wmb();
}
-int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
- struct msm_dsi_phy *src_phy)
-{
- struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
- struct clk *byte_clk_provider, *pixel_clk_provider;
- int ret;
-
- ret = msm_dsi_phy_get_clk_provider(src_phy,
- &byte_clk_provider, &pixel_clk_provider);
- if (ret) {
- pr_info("%s: can't get provider from pll, don't set parent\n",
- __func__);
- return 0;
- }
-
- ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
- if (ret) {
- pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
- __func__, ret);
- goto exit;
- }
-
- ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
- if (ret) {
- pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
- __func__, ret);
- goto exit;
- }
-
- if (msm_host->dsi_clk_src) {
- ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
- if (ret) {
- pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
- __func__, ret);
- goto exit;
- }
- }
-
- if (msm_host->esc_clk_src) {
- ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
- if (ret) {
- pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
- __func__, ret);
- goto exit;
- }
- }
-
-exit:
- return ret;
-}
-
void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 4ebfedc4a9ac..4a17f12b9316 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -78,7 +78,6 @@ static int dsi_mgr_setup_components(int id)
return ret;
msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE);
- ret = msm_dsi_host_set_src_pll(msm_dsi->host, msm_dsi->phy);
} else if (!other_dsi) {
ret = 0;
} else {
@@ -105,10 +104,6 @@ static int dsi_mgr_setup_components(int id)
MSM_DSI_PHY_MASTER);
msm_dsi_phy_set_usecase(clk_slave_dsi->phy,
MSM_DSI_PHY_SLAVE);
- ret = msm_dsi_host_set_src_pll(msm_dsi->host, clk_master_dsi->phy);
- if (ret)
- return ret;
- ret = msm_dsi_host_set_src_pll(other_dsi->host, clk_master_dsi->phy);
}
return ret;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 6ca6bfd4809b..952fd0b95865 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -835,17 +835,6 @@ void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
phy->usecase = uc;
}
-int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
- struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
-{
- if (byte_clk_provider)
- *byte_clk_provider = phy->provided_clocks->hws[DSI_BYTE_PLL_CLK]->clk;
- if (pixel_clk_provider)
- *pixel_clk_provider = phy->provided_clocks->hws[DSI_PIXEL_PLL_CLK]->clk;
-
- return 0;
-}
-
void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy)
{
if (phy->cfg->ops.save_pll_state) {
--
2.30.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 6/8] drm/msm/dsi: stop setting clock parents manually
2021-07-09 21:07 ` [PATCH v2 6/8] drm/msm/dsi: stop setting clock parents manually Dmitry Baryshkov
@ 2021-10-03 2:13 ` Dmitry Baryshkov
0 siblings, 0 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2021-10-03 2:13 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar,
Rob Herring
Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
linux-arm-msm, dri-devel, freedreno, devicetree
On 10/07/2021 00:07, Dmitry Baryshkov wrote:
> There is no reason to set clock parents manually, use device tree to
> assign DSI/display clock parents to DSI PHY clocks. Dropping this manual
> setup allows us to drop repeating code and to move registration of hw
> clock providers to generic place.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
As the DTS changes were merged for the 5.15, would it be time to merge
the rest of this patch series for the 5.16?
> ---
> drivers/gpu/drm/msm/dsi/dsi.h | 2 --
> drivers/gpu/drm/msm/dsi/dsi_host.c | 51 ---------------------------
> drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 11 ------
> 4 files changed, 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index 9b8e9b07eced..1f0ec78c6b05 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -170,8 +170,6 @@ void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
> struct msm_dsi_phy_shared_timings *shared_timing);
> void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
> enum msm_dsi_phy_usecase uc);
> -int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
> - struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
> void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy);
> int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy);
> void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy);
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index ed504fe5074f..1fa6ee12395b 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2219,57 +2219,6 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
> wmb();
> }
>
> -int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
> - struct msm_dsi_phy *src_phy)
> -{
> - struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> - struct clk *byte_clk_provider, *pixel_clk_provider;
> - int ret;
> -
> - ret = msm_dsi_phy_get_clk_provider(src_phy,
> - &byte_clk_provider, &pixel_clk_provider);
> - if (ret) {
> - pr_info("%s: can't get provider from pll, don't set parent\n",
> - __func__);
> - return 0;
> - }
> -
> - ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
> - if (ret) {
> - pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
> - __func__, ret);
> - goto exit;
> - }
> -
> - ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
> - if (ret) {
> - pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
> - __func__, ret);
> - goto exit;
> - }
> -
> - if (msm_host->dsi_clk_src) {
> - ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
> - if (ret) {
> - pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
> - __func__, ret);
> - goto exit;
> - }
> - }
> -
> - if (msm_host->esc_clk_src) {
> - ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
> - if (ret) {
> - pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
> - __func__, ret);
> - goto exit;
> - }
> - }
> -
> -exit:
> - return ret;
> -}
> -
> void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> index 4ebfedc4a9ac..4a17f12b9316 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> @@ -78,7 +78,6 @@ static int dsi_mgr_setup_components(int id)
> return ret;
>
> msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE);
> - ret = msm_dsi_host_set_src_pll(msm_dsi->host, msm_dsi->phy);
> } else if (!other_dsi) {
> ret = 0;
> } else {
> @@ -105,10 +104,6 @@ static int dsi_mgr_setup_components(int id)
> MSM_DSI_PHY_MASTER);
> msm_dsi_phy_set_usecase(clk_slave_dsi->phy,
> MSM_DSI_PHY_SLAVE);
> - ret = msm_dsi_host_set_src_pll(msm_dsi->host, clk_master_dsi->phy);
> - if (ret)
> - return ret;
> - ret = msm_dsi_host_set_src_pll(other_dsi->host, clk_master_dsi->phy);
> }
>
> return ret;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 6ca6bfd4809b..952fd0b95865 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -835,17 +835,6 @@ void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
> phy->usecase = uc;
> }
>
> -int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
> - struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
> -{
> - if (byte_clk_provider)
> - *byte_clk_provider = phy->provided_clocks->hws[DSI_BYTE_PLL_CLK]->clk;
> - if (pixel_clk_provider)
> - *pixel_clk_provider = phy->provided_clocks->hws[DSI_PIXEL_PLL_CLK]->clk;
> -
> - return 0;
> -}
> -
> void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy)
> {
> if (phy->cfg->ops.save_pll_state) {
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 7/8] drm/msm/dsi: phy: use of_device_get_match_data
2021-07-09 21:07 [PATCH v2 0/8] dsi: rework clock parents and timing handling Dmitry Baryshkov
` (5 preceding siblings ...)
2021-07-09 21:07 ` [PATCH v2 6/8] drm/msm/dsi: stop setting clock parents manually Dmitry Baryshkov
@ 2021-07-09 21:07 ` Dmitry Baryshkov
2021-07-09 21:07 ` [PATCH v2 8/8] drm/msm/dsi: drop msm_dsi_phy_get_shared_timings Dmitry Baryshkov
7 siblings, 0 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2021-07-09 21:07 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar,
Rob Herring
Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
linux-arm-msm, dri-devel, freedreno, devicetree
Use of_device_get_match-data() instead of of_match_node().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 952fd0b95865..c76a6438ffb9 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -625,17 +625,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
{
struct msm_dsi_phy *phy;
struct device *dev = &pdev->dev;
- const struct of_device_id *match;
int ret;
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
if (!phy)
return -ENOMEM;
- match = of_match_node(dsi_phy_dt_match, dev->of_node);
- if (!match)
- return -ENODEV;
-
phy->provided_clocks = devm_kzalloc(dev,
struct_size(phy->provided_clocks, hws, NUM_PROVIDED_CLKS),
GFP_KERNEL);
@@ -644,7 +639,10 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
phy->provided_clocks->num = NUM_PROVIDED_CLKS;
- phy->cfg = match->data;
+ phy->cfg = of_device_get_match_data(&pdev->dev);
+ if (!phy->cfg)
+ return -ENODEV;
+
phy->pdev = pdev;
phy->id = dsi_phy_get_id(phy);
--
2.30.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 8/8] drm/msm/dsi: drop msm_dsi_phy_get_shared_timings
2021-07-09 21:07 [PATCH v2 0/8] dsi: rework clock parents and timing handling Dmitry Baryshkov
` (6 preceding siblings ...)
2021-07-09 21:07 ` [PATCH v2 7/8] drm/msm/dsi: phy: use of_device_get_match_data Dmitry Baryshkov
@ 2021-07-09 21:07 ` Dmitry Baryshkov
7 siblings, 0 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2021-07-09 21:07 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar,
Rob Herring
Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
linux-arm-msm, dri-devel, freedreno, devicetree
Instead of fetching shared timing through an extra function call, get
them directly from msm_dsi_phy_enable.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 5 ++---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 3 +--
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 13 +++++--------
3 files changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 1f0ec78c6b05..876053ba615b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -164,10 +164,9 @@ struct msm_dsi_phy_clk_request {
void msm_dsi_phy_driver_register(void);
void msm_dsi_phy_driver_unregister(void);
int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
- struct msm_dsi_phy_clk_request *clk_req);
+ struct msm_dsi_phy_clk_request *clk_req,
+ struct msm_dsi_phy_shared_timings *shared_timings);
void msm_dsi_phy_disable(struct msm_dsi_phy *phy);
-void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
- struct msm_dsi_phy_shared_timings *shared_timing);
void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
enum msm_dsi_phy_usecase uc);
void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 4a17f12b9316..6f90d9940e8b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -118,8 +118,7 @@ static int enable_phy(struct msm_dsi *msm_dsi,
msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req, is_dual_dsi);
- ret = msm_dsi_phy_enable(msm_dsi->phy, &clk_req);
- msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings);
+ ret = msm_dsi_phy_enable(msm_dsi->phy, &clk_req, shared_timings);
return ret;
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index c76a6438ffb9..f479e37d6428 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -752,7 +752,8 @@ void __exit msm_dsi_phy_driver_unregister(void)
}
int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
- struct msm_dsi_phy_clk_request *clk_req)
+ struct msm_dsi_phy_clk_request *clk_req,
+ struct msm_dsi_phy_shared_timings *shared_timings)
{
struct device *dev = &phy->pdev->dev;
int ret;
@@ -780,6 +781,9 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
goto phy_en_fail;
}
+ memcpy(shared_timings, &phy->timing.shared_timings,
+ sizeof(*shared_timings));
+
/*
* Resetting DSI PHY silently changes its PLL registers to reset status,
* which will confuse clock driver and result in wrong output rate of
@@ -819,13 +823,6 @@ void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
dsi_phy_disable_resource(phy);
}
-void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
- struct msm_dsi_phy_shared_timings *shared_timings)
-{
- memcpy(shared_timings, &phy->timing.shared_timings,
- sizeof(*shared_timings));
-}
-
void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
enum msm_dsi_phy_usecase uc)
{
--
2.30.2
^ permalink raw reply related [flat|nested] 11+ messages in thread