* [PATCH 0/7] Add Amlogic meson8b clock gates
@ 2016-07-05 17:56 Alexander Müller
2016-07-05 17:56 ` [PATCH 1/7] clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention Alexander Müller
` (6 more replies)
0 siblings, 7 replies; 24+ messages in thread
From: Alexander Müller @ 2016-07-05 17:56 UTC (permalink / raw)
To: mturquette, linux-clk, linux-amlogic
This patch series adds support for the Amlogic meson8b clock gates. The Amlogic
U-Boot disables most of them at boot. In order to enable ethernet, USB and other
components it's mandatory to enable the clock gates when loading the corresponding
drivers.
The meson8b clock gate support is based on the previous work done for Amlogic gxbb
currently available in clk-next.
Alexander Müller (7):
clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention
meson: clk: Move register definitions to meson8b.h
meson: clk: Rename register names according to Amlogic datasheet
meson: clk: Add CLKIDs for DT binding
gxbb: clk: Move MESON_GATE macro to gxbb
meson: clk: Add support for clock gates
arm: amlogic: select meson8b clk driver
arch/arm/mach-meson/Kconfig | 2 +
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/clkc.h | 14 -
drivers/clk/meson/gxbb.c | 176 ++++----
drivers/clk/meson/meson8b-clkc.c | 458 --------------------
drivers/clk/meson/meson8b.c | 706 +++++++++++++++++++++++++++++++
drivers/clk/meson/meson8b.h | 44 ++
include/dt-bindings/clock/meson8b-clkc.h | 79 +++-
8 files changed, 926 insertions(+), 555 deletions(-)
delete mode 100644 drivers/clk/meson/meson8b-clkc.c
create mode 100644 drivers/clk/meson/meson8b.c
create mode 100644 drivers/clk/meson/meson8b.h
--
2.5.0
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 1/7] clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention 2016-07-05 17:56 [PATCH 0/7] Add Amlogic meson8b clock gates Alexander Müller @ 2016-07-05 17:56 ` Alexander Müller 2016-07-05 18:55 ` Carlo Caione 2016-07-05 17:56 ` [PATCH 2/7] meson: clk: Move register definitions to meson8b.h Alexander Müller ` (5 subsequent siblings) 6 siblings, 1 reply; 24+ messages in thread From: Alexander Müller @ 2016-07-05 17:56 UTC (permalink / raw) To: mturquette, linux-clk, linux-amlogic Signed-off-by: Alexander Müller <serveralex@gmail.com> --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/meson8b-clkc.c | 458 --------------------------------------- drivers/clk/meson/meson8b.c | 458 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 459 insertions(+), 459 deletions(-) delete mode 100644 drivers/clk/meson/meson8b-clkc.c create mode 100644 drivers/clk/meson/meson8b.c diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 197e401..1a66799 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -3,5 +3,5 @@ # obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o -obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o +obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o diff --git a/drivers/clk/meson/meson8b-clkc.c b/drivers/clk/meson/meson8b-clkc.c deleted file mode 100644 index b1902e9..0000000 --- a/drivers/clk/meson/meson8b-clkc.c +++ /dev/null @@ -1,458 +0,0 @@ -/* - * Copyright (c) 2015 Endless Mobile, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - * Copyright (c) 2016 BayLibre, Inc. - * Michael Turquette <mturquette@baylibre.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <linux/clk.h> -#include <linux/clk-provider.h> -#include <linux/of_address.h> -#include <dt-bindings/clock/meson8b-clkc.h> -#include <linux/platform_device.h> -#include <linux/module.h> - -#include "clkc.h" - -/* - * Clock controller register offsets - * - * Register offsets from the HardKernel[0] data sheet are listed in comment - * blocks below. Those offsets must be multiplied by 4 before adding them to - * the base address to get the right value - * - * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf - */ -#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */ -#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */ -#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */ -#define MESON8B_REG_PLL_FIXED 0x0280 -#define MESON8B_REG_PLL_SYS 0x0300 -#define MESON8B_REG_PLL_VID 0x0320 - -static DEFINE_SPINLOCK(clk_lock); - -static const struct pll_rate_table sys_pll_rate_table[] = { - PLL_RATE(312000000, 52, 1, 2), - PLL_RATE(336000000, 56, 1, 2), - PLL_RATE(360000000, 60, 1, 2), - PLL_RATE(384000000, 64, 1, 2), - PLL_RATE(408000000, 68, 1, 2), - PLL_RATE(432000000, 72, 1, 2), - PLL_RATE(456000000, 76, 1, 2), - PLL_RATE(480000000, 80, 1, 2), - PLL_RATE(504000000, 84, 1, 2), - PLL_RATE(528000000, 88, 1, 2), - PLL_RATE(552000000, 92, 1, 2), - PLL_RATE(576000000, 96, 1, 2), - PLL_RATE(600000000, 50, 1, 1), - PLL_RATE(624000000, 52, 1, 1), - PLL_RATE(648000000, 54, 1, 1), - PLL_RATE(672000000, 56, 1, 1), - PLL_RATE(696000000, 58, 1, 1), - PLL_RATE(720000000, 60, 1, 1), - PLL_RATE(744000000, 62, 1, 1), - PLL_RATE(768000000, 64, 1, 1), - PLL_RATE(792000000, 66, 1, 1), - PLL_RATE(816000000, 68, 1, 1), - PLL_RATE(840000000, 70, 1, 1), - PLL_RATE(864000000, 72, 1, 1), - PLL_RATE(888000000, 74, 1, 1), - PLL_RATE(912000000, 76, 1, 1), - PLL_RATE(936000000, 78, 1, 1), - PLL_RATE(960000000, 80, 1, 1), - PLL_RATE(984000000, 82, 1, 1), - PLL_RATE(1008000000, 84, 1, 1), - PLL_RATE(1032000000, 86, 1, 1), - PLL_RATE(1056000000, 88, 1, 1), - PLL_RATE(1080000000, 90, 1, 1), - PLL_RATE(1104000000, 92, 1, 1), - PLL_RATE(1128000000, 94, 1, 1), - PLL_RATE(1152000000, 96, 1, 1), - PLL_RATE(1176000000, 98, 1, 1), - PLL_RATE(1200000000, 50, 1, 0), - PLL_RATE(1224000000, 51, 1, 0), - PLL_RATE(1248000000, 52, 1, 0), - PLL_RATE(1272000000, 53, 1, 0), - PLL_RATE(1296000000, 54, 1, 0), - PLL_RATE(1320000000, 55, 1, 0), - PLL_RATE(1344000000, 56, 1, 0), - PLL_RATE(1368000000, 57, 1, 0), - PLL_RATE(1392000000, 58, 1, 0), - PLL_RATE(1416000000, 59, 1, 0), - PLL_RATE(1440000000, 60, 1, 0), - PLL_RATE(1464000000, 61, 1, 0), - PLL_RATE(1488000000, 62, 1, 0), - PLL_RATE(1512000000, 63, 1, 0), - PLL_RATE(1536000000, 64, 1, 0), - { /* sentinel */ }, -}; - -static const struct clk_div_table cpu_div_table[] = { - { .val = 1, .div = 1 }, - { .val = 2, .div = 2 }, - { .val = 3, .div = 3 }, - { .val = 2, .div = 4 }, - { .val = 3, .div = 6 }, - { .val = 4, .div = 8 }, - { .val = 5, .div = 10 }, - { .val = 6, .div = 12 }, - { .val = 7, .div = 14 }, - { .val = 8, .div = 16 }, - { /* sentinel */ }, -}; - -static struct clk_fixed_rate meson8b_xtal = { - .fixed_rate = 24000000, - .hw.init = &(struct clk_init_data){ - .name = "xtal", - .num_parents = 0, - .ops = &clk_fixed_rate_ops, - }, -}; - -static struct meson_clk_pll meson8b_fixed_pll = { - .m = { - .reg_off = MESON8B_REG_PLL_FIXED, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = MESON8B_REG_PLL_FIXED, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = MESON8B_REG_PLL_FIXED, - .shift = 16, - .width = 2, - }, - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "fixed_pll", - .ops = &meson_clk_pll_ro_ops, - .parent_names = (const char *[]){ "xtal" }, - .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE, - }, -}; - -static struct meson_clk_pll meson8b_vid_pll = { - .m = { - .reg_off = MESON8B_REG_PLL_VID, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = MESON8B_REG_PLL_VID, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = MESON8B_REG_PLL_VID, - .shift = 16, - .width = 2, - }, - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll", - .ops = &meson_clk_pll_ro_ops, - .parent_names = (const char *[]){ "xtal" }, - .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE, - }, -}; - -static struct meson_clk_pll meson8b_sys_pll = { - .m = { - .reg_off = MESON8B_REG_PLL_SYS, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = MESON8B_REG_PLL_SYS, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = MESON8B_REG_PLL_SYS, - .shift = 16, - .width = 2, - }, - .rate_table = sys_pll_rate_table, - .rate_count = ARRAY_SIZE(sys_pll_rate_table), - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "sys_pll", - .ops = &meson_clk_pll_ops, - .parent_names = (const char *[]){ "xtal" }, - .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE, - }, -}; - -static struct clk_fixed_factor meson8b_fclk_div2 = { - .mult = 1, - .div = 2, - .hw.init = &(struct clk_init_data){ - .name = "fclk_div2", - .ops = &clk_fixed_factor_ops, - .parent_names = (const char *[]){ "fixed_pll" }, - .num_parents = 1, - }, -}; - -static struct clk_fixed_factor meson8b_fclk_div3 = { - .mult = 1, - .div = 3, - .hw.init = &(struct clk_init_data){ - .name = "fclk_div3", - .ops = &clk_fixed_factor_ops, - .parent_names = (const char *[]){ "fixed_pll" }, - .num_parents = 1, - }, -}; - -static struct clk_fixed_factor meson8b_fclk_div4 = { - .mult = 1, - .div = 4, - .hw.init = &(struct clk_init_data){ - .name = "fclk_div4", - .ops = &clk_fixed_factor_ops, - .parent_names = (const char *[]){ "fixed_pll" }, - .num_parents = 1, - }, -}; - -static struct clk_fixed_factor meson8b_fclk_div5 = { - .mult = 1, - .div = 5, - .hw.init = &(struct clk_init_data){ - .name = "fclk_div5", - .ops = &clk_fixed_factor_ops, - .parent_names = (const char *[]){ "fixed_pll" }, - .num_parents = 1, - }, -}; - -static struct clk_fixed_factor meson8b_fclk_div7 = { - .mult = 1, - .div = 7, - .hw.init = &(struct clk_init_data){ - .name = "fclk_div7", - .ops = &clk_fixed_factor_ops, - .parent_names = (const char *[]){ "fixed_pll" }, - .num_parents = 1, - }, -}; - -/* - * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL - * post-dividers and should be modeled with their respective PLLs via the - * forthcoming coordinated clock rates feature - */ -static struct meson_clk_cpu meson8b_cpu_clk = { - .reg_off = MESON8B_REG_SYS_CPU_CNTL1, - .div_table = cpu_div_table, - .clk_nb.notifier_call = meson_clk_cpu_notifier_cb, - .hw.init = &(struct clk_init_data){ - .name = "cpu_clk", - .ops = &meson_clk_cpu_ops, - .parent_names = (const char *[]){ "sys_pll" }, - .num_parents = 1, - }, -}; - -static u32 mux_table_clk81[] = { 6, 5, 7 }; - -struct clk_mux meson8b_mpeg_clk_sel = { - .reg = (void *)MESON8B_REG_HHI_MPEG, - .mask = 0x7, - .shift = 12, - .flags = CLK_MUX_READ_ONLY, - .table = mux_table_clk81, - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "mpeg_clk_sel", - .ops = &clk_mux_ro_ops, - /* - * FIXME bits 14:12 selects from 8 possible parents: - * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, - * fclk_div4, fclk_div3, fclk_div5 - */ - .parent_names = (const char *[]){ "fclk_div3", "fclk_div4", - "fclk_div5" }, - .num_parents = 3, - .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), - }, -}; - -struct clk_divider meson8b_mpeg_clk_div = { - .reg = (void *)MESON8B_REG_HHI_MPEG, - .shift = 0, - .width = 7, - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "mpeg_clk_div", - .ops = &clk_divider_ops, - .parent_names = (const char *[]){ "mpeg_clk_sel" }, - .num_parents = 1, - .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), - }, -}; - -struct clk_gate meson8b_clk81 = { - .reg = (void *)MESON8B_REG_HHI_MPEG, - .bit_idx = 7, - .lock = &clk_lock, - .hw.init = &(struct clk_init_data){ - .name = "clk81", - .ops = &clk_gate_ops, - .parent_names = (const char *[]){ "mpeg_clk_div" }, - .num_parents = 1, - .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), - }, -}; - -static struct clk_hw_onecell_data meson8b_hw_onecell_data = { - .hws = { - [CLKID_XTAL] = &meson8b_xtal.hw, - [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, - [CLKID_PLL_VID] = &meson8b_vid_pll.hw, - [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, - [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, - [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, - [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, - [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, - [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, - [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, - [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, - [CLKID_CLK81] = &meson8b_clk81.hw, - }, - .num = CLK_NR_CLKS, -}; - -static struct meson_clk_pll *const meson8b_clk_plls[] = { - &meson8b_fixed_pll, - &meson8b_vid_pll, - &meson8b_sys_pll, -}; - -static int meson8b_clkc_probe(struct platform_device *pdev) -{ - void __iomem *clk_base; - int ret, clkid, i; - struct clk_hw *parent_hw; - struct clk *parent_clk; - struct device *dev = &pdev->dev; - - /* Generic clocks and PLLs */ - clk_base = of_iomap(dev->of_node, 1); - if (!clk_base) { - pr_err("%s: Unable to map clk base\n", __func__); - return -ENXIO; - } - - /* Populate base address for PLLs */ - for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++) - meson8b_clk_plls[i]->base = clk_base; - - /* Populate the base address for CPU clk */ - meson8b_cpu_clk.base = clk_base; - - /* Populate the base address for the MPEG clks */ - meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg; - meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg; - meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg; - - /* - * register all clks - * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 - */ - for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) { - /* array might be sparse */ - if (!meson8b_hw_onecell_data.hws[clkid]) - continue; - - /* FIXME convert to devm_clk_register */ - ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]); - if (ret) - goto iounmap; - } - - /* - * Register CPU clk notifier - * - * FIXME this is wrong for a lot of reasons. First, the muxes should be - * struct clk_hw objects. Second, we shouldn't program the muxes in - * notifier handlers. The tricky programming sequence will be handled - * by the forthcoming coordinated clock rates mechanism once that - * feature is released. - * - * Furthermore, looking up the parent this way is terrible. At some - * point we will stop allocating a default struct clk when registering - * a new clk_hw, and this hack will no longer work. Releasing the ccr - * feature before that time solves the problem :-) - */ - parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw); - parent_clk = parent_hw->clk; - ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb); - if (ret) { - pr_err("%s: failed to register clock notifier for cpu_clk\n", - __func__); - goto iounmap; - } - - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - &meson8b_hw_onecell_data); - -iounmap: - iounmap(clk_base); - return ret; -} - -static const struct of_device_id meson8b_clkc_match_table[] = { - { .compatible = "amlogic,meson8b-clkc" }, - { } -}; -MODULE_DEVICE_TABLE(of, meson8b_match_table); - -static struct platform_driver meson8b_driver = { - .probe = meson8b_clkc_probe, - .driver = { - .name = "meson8b-clkc", - .of_match_table = meson8b_clkc_match_table, - }, -}; - -static int __init meson8b_clkc_init(void) -{ - return platform_driver_register(&meson8b_driver); -} -module_init(meson8b_clkc_init); - -static void __exit meson8b_clkc_exit(void) -{ - platform_driver_unregister(&meson8b_driver); -} -module_exit(meson8b_clkc_exit); - -MODULE_DESCRIPTION("AmLogic S805 / Meson8b Clock Controller Driver"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:meson8b-clkc"); -MODULE_AUTHOR("Michael Turquette <mturquette@baylibre.com>"); -MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>"); diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c new file mode 100644 index 0000000..b1902e9 --- /dev/null +++ b/drivers/clk/meson/meson8b.c @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2015 Endless Mobile, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * Copyright (c) 2016 BayLibre, Inc. + * Michael Turquette <mturquette@baylibre.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <dt-bindings/clock/meson8b-clkc.h> +#include <linux/platform_device.h> +#include <linux/module.h> + +#include "clkc.h" + +/* + * Clock controller register offsets + * + * Register offsets from the HardKernel[0] data sheet are listed in comment + * blocks below. Those offsets must be multiplied by 4 before adding them to + * the base address to get the right value + * + * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf + */ +#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */ +#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */ +#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */ +#define MESON8B_REG_PLL_FIXED 0x0280 +#define MESON8B_REG_PLL_SYS 0x0300 +#define MESON8B_REG_PLL_VID 0x0320 + +static DEFINE_SPINLOCK(clk_lock); + +static const struct pll_rate_table sys_pll_rate_table[] = { + PLL_RATE(312000000, 52, 1, 2), + PLL_RATE(336000000, 56, 1, 2), + PLL_RATE(360000000, 60, 1, 2), + PLL_RATE(384000000, 64, 1, 2), + PLL_RATE(408000000, 68, 1, 2), + PLL_RATE(432000000, 72, 1, 2), + PLL_RATE(456000000, 76, 1, 2), + PLL_RATE(480000000, 80, 1, 2), + PLL_RATE(504000000, 84, 1, 2), + PLL_RATE(528000000, 88, 1, 2), + PLL_RATE(552000000, 92, 1, 2), + PLL_RATE(576000000, 96, 1, 2), + PLL_RATE(600000000, 50, 1, 1), + PLL_RATE(624000000, 52, 1, 1), + PLL_RATE(648000000, 54, 1, 1), + PLL_RATE(672000000, 56, 1, 1), + PLL_RATE(696000000, 58, 1, 1), + PLL_RATE(720000000, 60, 1, 1), + PLL_RATE(744000000, 62, 1, 1), + PLL_RATE(768000000, 64, 1, 1), + PLL_RATE(792000000, 66, 1, 1), + PLL_RATE(816000000, 68, 1, 1), + PLL_RATE(840000000, 70, 1, 1), + PLL_RATE(864000000, 72, 1, 1), + PLL_RATE(888000000, 74, 1, 1), + PLL_RATE(912000000, 76, 1, 1), + PLL_RATE(936000000, 78, 1, 1), + PLL_RATE(960000000, 80, 1, 1), + PLL_RATE(984000000, 82, 1, 1), + PLL_RATE(1008000000, 84, 1, 1), + PLL_RATE(1032000000, 86, 1, 1), + PLL_RATE(1056000000, 88, 1, 1), + PLL_RATE(1080000000, 90, 1, 1), + PLL_RATE(1104000000, 92, 1, 1), + PLL_RATE(1128000000, 94, 1, 1), + PLL_RATE(1152000000, 96, 1, 1), + PLL_RATE(1176000000, 98, 1, 1), + PLL_RATE(1200000000, 50, 1, 0), + PLL_RATE(1224000000, 51, 1, 0), + PLL_RATE(1248000000, 52, 1, 0), + PLL_RATE(1272000000, 53, 1, 0), + PLL_RATE(1296000000, 54, 1, 0), + PLL_RATE(1320000000, 55, 1, 0), + PLL_RATE(1344000000, 56, 1, 0), + PLL_RATE(1368000000, 57, 1, 0), + PLL_RATE(1392000000, 58, 1, 0), + PLL_RATE(1416000000, 59, 1, 0), + PLL_RATE(1440000000, 60, 1, 0), + PLL_RATE(1464000000, 61, 1, 0), + PLL_RATE(1488000000, 62, 1, 0), + PLL_RATE(1512000000, 63, 1, 0), + PLL_RATE(1536000000, 64, 1, 0), + { /* sentinel */ }, +}; + +static const struct clk_div_table cpu_div_table[] = { + { .val = 1, .div = 1 }, + { .val = 2, .div = 2 }, + { .val = 3, .div = 3 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 6 }, + { .val = 4, .div = 8 }, + { .val = 5, .div = 10 }, + { .val = 6, .div = 12 }, + { .val = 7, .div = 14 }, + { .val = 8, .div = 16 }, + { /* sentinel */ }, +}; + +static struct clk_fixed_rate meson8b_xtal = { + .fixed_rate = 24000000, + .hw.init = &(struct clk_init_data){ + .name = "xtal", + .num_parents = 0, + .ops = &clk_fixed_rate_ops, + }, +}; + +static struct meson_clk_pll meson8b_fixed_pll = { + .m = { + .reg_off = MESON8B_REG_PLL_FIXED, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = MESON8B_REG_PLL_FIXED, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = MESON8B_REG_PLL_FIXED, + .shift = 16, + .width = 2, + }, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "fixed_pll", + .ops = &meson_clk_pll_ro_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct meson_clk_pll meson8b_vid_pll = { + .m = { + .reg_off = MESON8B_REG_PLL_VID, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = MESON8B_REG_PLL_VID, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = MESON8B_REG_PLL_VID, + .shift = 16, + .width = 2, + }, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "vid_pll", + .ops = &meson_clk_pll_ro_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct meson_clk_pll meson8b_sys_pll = { + .m = { + .reg_off = MESON8B_REG_PLL_SYS, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = MESON8B_REG_PLL_SYS, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = MESON8B_REG_PLL_SYS, + .shift = 16, + .width = 2, + }, + .rate_table = sys_pll_rate_table, + .rate_count = ARRAY_SIZE(sys_pll_rate_table), + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "sys_pll", + .ops = &meson_clk_pll_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_fixed_factor meson8b_fclk_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div2", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_fclk_div3 = { + .mult = 1, + .div = 3, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div3", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_fclk_div4 = { + .mult = 1, + .div = 4, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div4", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_fclk_div5 = { + .mult = 1, + .div = 5, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div5", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_fclk_div7 = { + .mult = 1, + .div = 7, + .hw.init = &(struct clk_init_data){ + .name = "fclk_div7", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "fixed_pll" }, + .num_parents = 1, + }, +}; + +/* + * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL + * post-dividers and should be modeled with their respective PLLs via the + * forthcoming coordinated clock rates feature + */ +static struct meson_clk_cpu meson8b_cpu_clk = { + .reg_off = MESON8B_REG_SYS_CPU_CNTL1, + .div_table = cpu_div_table, + .clk_nb.notifier_call = meson_clk_cpu_notifier_cb, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk", + .ops = &meson_clk_cpu_ops, + .parent_names = (const char *[]){ "sys_pll" }, + .num_parents = 1, + }, +}; + +static u32 mux_table_clk81[] = { 6, 5, 7 }; + +struct clk_mux meson8b_mpeg_clk_sel = { + .reg = (void *)MESON8B_REG_HHI_MPEG, + .mask = 0x7, + .shift = 12, + .flags = CLK_MUX_READ_ONLY, + .table = mux_table_clk81, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mpeg_clk_sel", + .ops = &clk_mux_ro_ops, + /* + * FIXME bits 14:12 selects from 8 possible parents: + * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, + * fclk_div4, fclk_div3, fclk_div5 + */ + .parent_names = (const char *[]){ "fclk_div3", "fclk_div4", + "fclk_div5" }, + .num_parents = 3, + .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), + }, +}; + +struct clk_divider meson8b_mpeg_clk_div = { + .reg = (void *)MESON8B_REG_HHI_MPEG, + .shift = 0, + .width = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "mpeg_clk_div", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "mpeg_clk_sel" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + }, +}; + +struct clk_gate meson8b_clk81 = { + .reg = (void *)MESON8B_REG_HHI_MPEG, + .bit_idx = 7, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "clk81", + .ops = &clk_gate_ops, + .parent_names = (const char *[]){ "mpeg_clk_div" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + }, +}; + +static struct clk_hw_onecell_data meson8b_hw_onecell_data = { + .hws = { + [CLKID_XTAL] = &meson8b_xtal.hw, + [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, + [CLKID_PLL_VID] = &meson8b_vid_pll.hw, + [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, + [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, + [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, + [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, + [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, + [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, + [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, + [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, + [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, + [CLKID_CLK81] = &meson8b_clk81.hw, + }, + .num = CLK_NR_CLKS, +}; + +static struct meson_clk_pll *const meson8b_clk_plls[] = { + &meson8b_fixed_pll, + &meson8b_vid_pll, + &meson8b_sys_pll, +}; + +static int meson8b_clkc_probe(struct platform_device *pdev) +{ + void __iomem *clk_base; + int ret, clkid, i; + struct clk_hw *parent_hw; + struct clk *parent_clk; + struct device *dev = &pdev->dev; + + /* Generic clocks and PLLs */ + clk_base = of_iomap(dev->of_node, 1); + if (!clk_base) { + pr_err("%s: Unable to map clk base\n", __func__); + return -ENXIO; + } + + /* Populate base address for PLLs */ + for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++) + meson8b_clk_plls[i]->base = clk_base; + + /* Populate the base address for CPU clk */ + meson8b_cpu_clk.base = clk_base; + + /* Populate the base address for the MPEG clks */ + meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg; + meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg; + meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg; + + /* + * register all clks + * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 + */ + for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) { + /* array might be sparse */ + if (!meson8b_hw_onecell_data.hws[clkid]) + continue; + + /* FIXME convert to devm_clk_register */ + ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]); + if (ret) + goto iounmap; + } + + /* + * Register CPU clk notifier + * + * FIXME this is wrong for a lot of reasons. First, the muxes should be + * struct clk_hw objects. Second, we shouldn't program the muxes in + * notifier handlers. The tricky programming sequence will be handled + * by the forthcoming coordinated clock rates mechanism once that + * feature is released. + * + * Furthermore, looking up the parent this way is terrible. At some + * point we will stop allocating a default struct clk when registering + * a new clk_hw, and this hack will no longer work. Releasing the ccr + * feature before that time solves the problem :-) + */ + parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw); + parent_clk = parent_hw->clk; + ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb); + if (ret) { + pr_err("%s: failed to register clock notifier for cpu_clk\n", + __func__); + goto iounmap; + } + + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + &meson8b_hw_onecell_data); + +iounmap: + iounmap(clk_base); + return ret; +} + +static const struct of_device_id meson8b_clkc_match_table[] = { + { .compatible = "amlogic,meson8b-clkc" }, + { } +}; +MODULE_DEVICE_TABLE(of, meson8b_match_table); + +static struct platform_driver meson8b_driver = { + .probe = meson8b_clkc_probe, + .driver = { + .name = "meson8b-clkc", + .of_match_table = meson8b_clkc_match_table, + }, +}; + +static int __init meson8b_clkc_init(void) +{ + return platform_driver_register(&meson8b_driver); +} +module_init(meson8b_clkc_init); + +static void __exit meson8b_clkc_exit(void) +{ + platform_driver_unregister(&meson8b_driver); +} +module_exit(meson8b_clkc_exit); + +MODULE_DESCRIPTION("AmLogic S805 / Meson8b Clock Controller Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:meson8b-clkc"); +MODULE_AUTHOR("Michael Turquette <mturquette@baylibre.com>"); +MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>"); -- 2.5.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention 2016-07-05 17:56 ` [PATCH 1/7] clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention Alexander Müller @ 2016-07-05 18:55 ` Carlo Caione 2016-07-05 19:15 ` Alexander Müller 0 siblings, 1 reply; 24+ messages in thread From: Carlo Caione @ 2016-07-05 18:55 UTC (permalink / raw) To: Alexander Müller; +Cc: mturquette, linux-clk, linux-amlogic On 05/07/16 19:56, Alexander Müller wrote: > Signed-off-by: Alexander Müller <serveralex@gmail.com> > --- > drivers/clk/meson/Makefile | 2 +- > drivers/clk/meson/meson8b-clkc.c | 458 --------------------------------------- > drivers/clk/meson/meson8b.c | 458 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 459 insertions(+), 459 deletions(-) > delete mode 100644 drivers/clk/meson/meson8b-clkc.c > create mode 100644 drivers/clk/meson/meson8b.c Can you create the patch passing the '-M' parameter to git-format-patch to detect renames? Thanks, -- Carlo Caione ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/7] clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention 2016-07-05 18:55 ` Carlo Caione @ 2016-07-05 19:15 ` Alexander Müller 0 siblings, 0 replies; 24+ messages in thread From: Alexander Müller @ 2016-07-05 19:15 UTC (permalink / raw) To: mturquette, linux-clk, linux-amlogic Signed-off-by: Alexander Müller <serveralex@gmail.com> --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/{meson8b-clkc.c => meson8b.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/clk/meson/{meson8b-clkc.c => meson8b.c} (100%) diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 197e401..1a66799 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -3,5 +3,5 @@ # obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o -obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o +obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o diff --git a/drivers/clk/meson/meson8b-clkc.c b/drivers/clk/meson/meson8b.c similarity index 100% rename from drivers/clk/meson/meson8b-clkc.c rename to drivers/clk/meson/meson8b.c -- 2.5.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 2/7] meson: clk: Move register definitions to meson8b.h 2016-07-05 17:56 [PATCH 0/7] Add Amlogic meson8b clock gates Alexander Müller 2016-07-05 17:56 ` [PATCH 1/7] clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention Alexander Müller @ 2016-07-05 17:56 ` Alexander Müller 2016-07-05 17:56 ` [PATCH 3/7] meson: clk: Rename register names according to Amlogic datasheet Alexander Müller ` (4 subsequent siblings) 6 siblings, 0 replies; 24+ messages in thread From: Alexander Müller @ 2016-07-05 17:56 UTC (permalink / raw) To: mturquette, linux-clk, linux-amlogic Signed-off-by: Alexander Müller <serveralex@gmail.com> --- drivers/clk/meson/meson8b.c | 17 +---------------- drivers/clk/meson/meson8b.h | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+), 16 deletions(-) create mode 100644 drivers/clk/meson/meson8b.h diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index b1902e9..537cc53 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -26,22 +26,7 @@ #include <linux/module.h> #include "clkc.h" - -/* - * Clock controller register offsets - * - * Register offsets from the HardKernel[0] data sheet are listed in comment - * blocks below. Those offsets must be multiplied by 4 before adding them to - * the base address to get the right value - * - * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf - */ -#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */ -#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */ -#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */ -#define MESON8B_REG_PLL_FIXED 0x0280 -#define MESON8B_REG_PLL_SYS 0x0300 -#define MESON8B_REG_PLL_VID 0x0320 +#include "meson8b.h" static DEFINE_SPINLOCK(clk_lock); diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h new file mode 100644 index 0000000..5b9cb9f --- /dev/null +++ b/drivers/clk/meson/meson8b.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015 Endless Mobile, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * Copyright (c) 2016 BayLibre, Inc. + * Michael Turquette <mturquette@baylibre.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __MESON8B_H +#define __MESON8B_H + +/* + * Clock controller register offsets + * + * Register offsets from the HardKernel[0] data sheet are listed in comment + * blocks below. Those offsets must be multiplied by 4 before adding them to + * the base address to get the right value + * + * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf + */ +#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */ +#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */ +#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */ +#define MESON8B_REG_PLL_FIXED 0x0280 +#define MESON8B_REG_PLL_SYS 0x0300 +#define MESON8B_REG_PLL_VID 0x0320 + +#endif /* __MESON8B_H */ -- 2.5.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 3/7] meson: clk: Rename register names according to Amlogic datasheet 2016-07-05 17:56 [PATCH 0/7] Add Amlogic meson8b clock gates Alexander Müller 2016-07-05 17:56 ` [PATCH 1/7] clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention Alexander Müller 2016-07-05 17:56 ` [PATCH 2/7] meson: clk: Move register definitions to meson8b.h Alexander Müller @ 2016-07-05 17:56 ` Alexander Müller 2016-07-06 0:28 ` Michael Turquette 2016-07-05 17:56 ` [PATCH 4/7] meson: clk: Add CLKIDs for DT binding Alexander Müller ` (3 subsequent siblings) 6 siblings, 1 reply; 24+ messages in thread From: Alexander Müller @ 2016-07-05 17:56 UTC (permalink / raw) To: mturquette, linux-clk, linux-amlogic Signed-off-by: Alexander Müller <serveralex@gmail.com> --- drivers/clk/meson/meson8b.c | 26 +++++++++++++------------- drivers/clk/meson/meson8b.h | 11 +++++------ 2 files changed, 18 insertions(+), 19 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 537cc53..0c6e26f 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -111,17 +111,17 @@ static struct clk_fixed_rate meson8b_xtal = { static struct meson_clk_pll meson8b_fixed_pll = { .m = { - .reg_off = MESON8B_REG_PLL_FIXED, + .reg_off = HHI_MPLL_CNTL, .shift = 0, .width = 9, }, .n = { - .reg_off = MESON8B_REG_PLL_FIXED, + .reg_off = HHI_MPLL_CNTL, .shift = 9, .width = 5, }, .od = { - .reg_off = MESON8B_REG_PLL_FIXED, + .reg_off = HHI_MPLL_CNTL, .shift = 16, .width = 2, }, @@ -137,17 +137,17 @@ static struct meson_clk_pll meson8b_fixed_pll = { static struct meson_clk_pll meson8b_vid_pll = { .m = { - .reg_off = MESON8B_REG_PLL_VID, + .reg_off = HHI_VID_PLL_CNTL, .shift = 0, .width = 9, }, .n = { - .reg_off = MESON8B_REG_PLL_VID, + .reg_off = HHI_VID_PLL_CNTL, .shift = 9, .width = 5, }, .od = { - .reg_off = MESON8B_REG_PLL_VID, + .reg_off = HHI_VID_PLL_CNTL, .shift = 16, .width = 2, }, @@ -163,17 +163,17 @@ static struct meson_clk_pll meson8b_vid_pll = { static struct meson_clk_pll meson8b_sys_pll = { .m = { - .reg_off = MESON8B_REG_PLL_SYS, + .reg_off = HHI_SYS_PLL_CNTL, .shift = 0, .width = 9, }, .n = { - .reg_off = MESON8B_REG_PLL_SYS, + .reg_off = HHI_SYS_PLL_CNTL, .shift = 9, .width = 5, }, .od = { - .reg_off = MESON8B_REG_PLL_SYS, + .reg_off = HHI_SYS_PLL_CNTL, .shift = 16, .width = 2, }, @@ -250,7 +250,7 @@ static struct clk_fixed_factor meson8b_fclk_div7 = { * forthcoming coordinated clock rates feature */ static struct meson_clk_cpu meson8b_cpu_clk = { - .reg_off = MESON8B_REG_SYS_CPU_CNTL1, + .reg_off = HHI_SYS_CPU_CLK_CNTL1, .div_table = cpu_div_table, .clk_nb.notifier_call = meson_clk_cpu_notifier_cb, .hw.init = &(struct clk_init_data){ @@ -264,7 +264,7 @@ static struct meson_clk_cpu meson8b_cpu_clk = { static u32 mux_table_clk81[] = { 6, 5, 7 }; struct clk_mux meson8b_mpeg_clk_sel = { - .reg = (void *)MESON8B_REG_HHI_MPEG, + .reg = (void *)HHI_MPEG_CLK_CNTL, .mask = 0x7, .shift = 12, .flags = CLK_MUX_READ_ONLY, @@ -286,7 +286,7 @@ struct clk_mux meson8b_mpeg_clk_sel = { }; struct clk_divider meson8b_mpeg_clk_div = { - .reg = (void *)MESON8B_REG_HHI_MPEG, + .reg = (void *)HHI_MPEG_CLK_CNTL, .shift = 0, .width = 7, .lock = &clk_lock, @@ -300,7 +300,7 @@ struct clk_divider meson8b_mpeg_clk_div = { }; struct clk_gate meson8b_clk81 = { - .reg = (void *)MESON8B_REG_HHI_MPEG, + .reg = (void *)HHI_MPEG_CLK_CNTL, .bit_idx = 7, .lock = &clk_lock, .hw.init = &(struct clk_init_data){ diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 5b9cb9f..b2f29f7 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -30,11 +30,10 @@ * * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf */ -#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */ -#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */ -#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */ -#define MESON8B_REG_PLL_FIXED 0x0280 -#define MESON8B_REG_PLL_SYS 0x0300 -#define MESON8B_REG_PLL_VID 0x0320 +#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ +#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ +#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ +#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ +#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ #endif /* __MESON8B_H */ -- 2.5.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 3/7] meson: clk: Rename register names according to Amlogic datasheet 2016-07-05 17:56 ` [PATCH 3/7] meson: clk: Rename register names according to Amlogic datasheet Alexander Müller @ 2016-07-06 0:28 ` Michael Turquette 0 siblings, 0 replies; 24+ messages in thread From: Michael Turquette @ 2016-07-06 0:28 UTC (permalink / raw) To: Alexander Müller, linux-clk, linux-amlogic Quoting Alexander M=C3=BCller (2016-07-05 10:56:27) > Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com> > +#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data shee= t */ > +#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data shee= t */ > +#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data shee= t */ Nitpick: these three regs are not present in the data sheet, which is why I did not include the comment for these three addresses originally. Regards, Mike ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 4/7] meson: clk: Add CLKIDs for DT binding 2016-07-05 17:56 [PATCH 0/7] Add Amlogic meson8b clock gates Alexander Müller ` (2 preceding siblings ...) 2016-07-05 17:56 ` [PATCH 3/7] meson: clk: Rename register names according to Amlogic datasheet Alexander Müller @ 2016-07-05 17:56 ` Alexander Müller 2016-07-06 0:33 ` Michael Turquette 2016-07-05 17:56 ` [PATCH 5/7] gxbb: clk: Move MESON_GATE macro to gxbb Alexander Müller ` (2 subsequent siblings) 6 siblings, 1 reply; 24+ messages in thread From: Alexander Müller @ 2016-07-05 17:56 UTC (permalink / raw) To: mturquette, linux-clk, linux-amlogic Add clock ids for the clock gates to be used for DT bindings. Signed-off-by: Alexander Müller <serveralex@gmail.com> --- include/dt-bindings/clock/meson8b-clkc.h | 79 +++++++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index 595a58d..d8a9d53 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -21,7 +21,84 @@ #define CLKID_ZERO 13 #define CLKID_MPEG_SEL 14 #define CLKID_MPEG_DIV 15 +#define CLKID_DDR 16 +#define CLKID_DOS 17 +#define CLKID_ISA 18 +#define CLKID_PL301 19 +#define CLKID_PERIPHS 20 +#define CLKID_SPICC 21 +#define CLKID_I2C 22 +#define CLKID_SAR_ADC 23 +#define CLKID_SMART_CARD 24 +#define CLKID_RNG0 25 +#define CLKID_UART0 26 +#define CLKID_SDHC 27 +#define CLKID_STREAM 28 +#define CLKID_ASYNC_FIFO 29 +#define CLKID_SDIO 30 +#define CLKID_ABUF 31 +#define CLKID_HIU_IFACE 32 +#define CLKID_ASSIST_MISC 33 +#define CLKID_SPI 34 +#define CLKID_I2S_SPDIF 35 +#define CLKID_ETH 36 +#define CLKID_DEMUX 37 +#define CLKID_AIU_GLUE 38 +#define CLKID_IEC958 39 +#define CLKID_I2S_OUT 40 +#define CLKID_AMCLK 41 +#define CLKID_AIFIFO2 42 +#define CLKID_MIXER 43 +#define CLKID_MIXER_IFACE 44 +#define CLKID_ADC 45 +#define CLKID_BLKMV 46 +#define CLKID_AIU 47 +#define CLKID_UART1 48 +#define CLKID_G2D 49 +#define CLKID_USB0 50 +#define CLKID_USB1 51 +#define CLKID_RESET 52 +#define CLKID_NAND 53 +#define CLKID_DOS_PARSER 54 +#define CLKID_USB 55 +#define CLKID_VDIN1 56 +#define CLKID_AHB_ARB0 57 +#define CLKID_EFUSE 58 +#define CLKID_BOOT_ROM 59 +#define CLKID_AHB_DATA_BUS 60 +#define CLKID_AHB_CTRL_BUS 61 +#define CLKID_HDMI_INTR_SYNC 62 +#define CLKID_HDMI_PCLK 63 +#define CLKID_USB1_DDR_BRIDGE 64 +#define CLKID_USB0_DDR_BRIDGE 65 +#define CLKID_MMC_PCLK 66 +#define CLKID_DVIN 67 +#define CLKID_UART2 68 +#define CLKID_SANA 69 +#define CLKID_VPU_INTR 70 +#define CLKID_SEC_AHB_AHB3_BRIDGE 71 +#define CLKID_CLK81_A9 72 +#define CLKID_VCLK2_VENCI0 73 +#define CLKID_VCLK2_VENCI1 74 +#define CLKID_VCLK2_VENCP0 75 +#define CLKID_VCLK2_VENCP1 76 +#define CLKID_GCLK_VENCI_INT 77 +#define CLKID_GCLK_VENCP_INT 78 +#define CLKID_DAC_CLK 79 +#define CLKID_AOCLK_GATE 80 +#define CLKID_IEC958_GATE 81 +#define CLKID_ENC480P 82 +#define CLKID_RNG1 83 +#define CLKID_GCLK_VENCL_INT 84 +#define CLKID_VCLK2_VENCLMCC 85 +#define CLKID_VCLK2_VENCL 86 +#define CLKID_VCLK2_OTHER 87 +#define CLKID_EDP 88 +#define CLKID_AO_MEDIA_CPU 89 +#define CLKID_AO_AHB_SRAM 90 +#define CLKID_AO_AHB_BUS 91 +#define CLKID_AO_IFACE 92 -#define CLK_NR_CLKS (CLKID_MPEG_DIV + 1) +#define CLK_NR_CLKS (CLKID_AO_IFACE + 1) #endif /* __MESON8B_CLKC_H */ -- 2.5.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 4/7] meson: clk: Add CLKIDs for DT binding 2016-07-05 17:56 ` [PATCH 4/7] meson: clk: Add CLKIDs for DT binding Alexander Müller @ 2016-07-06 0:33 ` Michael Turquette 0 siblings, 0 replies; 24+ messages in thread From: Michael Turquette @ 2016-07-06 0:33 UTC (permalink / raw) To: Alexander Müller, linux-clk, linux-amlogic Hi Alexander, Quoting Alexander M=C3=BCller (2016-07-05 10:56:28) > +#define CLKID_AO_AHB_BUS 91 > +#define CLKID_AO_IFACE 92 > = > -#define CLK_NR_CLKS (CLKID_MPEG_DIV + 1) > +#define CLK_NR_CLKS (CLKID_AO_IFACE + 1) Did you take a look at how I did this for gxbb? I like to limit the number of clocks exposed in DT as much as possible. This is because a DT binding (of which this header is a part) constitutes an immutable ABI which shall only be relinquished when the Sun burns out and our solar system dies. Also, putting NR_CLKS inside of the binding is kind of gross, since the binding doesn't care about that value, but the driver does. The GXBB clk driver has two headers: one internal to Linux with the bulk of the clks and NR_CLKS, and a second one in the shared DT header chroot that only exposes the bare minimum necessary. Regards, Mike ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 5/7] gxbb: clk: Move MESON_GATE macro to gxbb 2016-07-05 17:56 [PATCH 0/7] Add Amlogic meson8b clock gates Alexander Müller ` (3 preceding siblings ...) 2016-07-05 17:56 ` [PATCH 4/7] meson: clk: Add CLKIDs for DT binding Alexander Müller @ 2016-07-05 17:56 ` Alexander Müller 2016-07-06 0:36 ` Michael Turquette 2016-07-05 17:56 ` [PATCH 6/7] meson: clk: Add support for clock gates Alexander Müller 2016-07-05 17:56 ` [PATCH 7/7] arm: amlogic: select meson8b clk driver Alexander Müller 6 siblings, 1 reply; 24+ messages in thread From: Alexander Müller @ 2016-07-05 17:56 UTC (permalink / raw) To: mturquette, linux-clk, linux-amlogic Signed-off-by: Alexander Müller <serveralex@gmail.com> --- drivers/clk/meson/clkc.h | 14 ---- drivers/clk/meson/gxbb.c | 176 +++++++++++++++++++++++++---------------------- 2 files changed, 95 insertions(+), 95 deletions(-) diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 53326c3..061a01e 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -97,20 +97,6 @@ struct meson_clk_mpll { spinlock_t *lock; }; -#define MESON_GATE(_name, _reg, _bit) \ -struct clk_gate gxbb_##_name = { \ - .reg = (void __iomem *) _reg, \ - .bit_idx = (_bit), \ - .lock = &clk_lock, \ - .hw.init = &(struct clk_init_data) { \ - .name = #_name, \ - .ops = &clk_gate_ops, \ - .parent_names = (const char *[]){ "clk81" }, \ - .num_parents = 1, \ - .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ - }, \ -}; - /* clk_ops */ extern const struct clk_ops meson_clk_pll_ro_ops; extern const struct clk_ops meson_clk_pll_ops; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 007b715..0ea71be 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -24,6 +24,20 @@ #include "clkc.h" #include "gxbb.h" +#define GBXX_GATE(_name, _reg, _bit) \ +struct clk_gate gxbb_##_name = { \ + .reg = (void __iomem *) _reg, \ + .bit_idx = (_bit), \ + .lock = &clk_lock, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_gate_ops, \ + .parent_names = (const char *[]){ "clk81" }, \ + .num_parents = 1, \ + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ + }, \ +}; + static DEFINE_SPINLOCK(clk_lock); static const struct pll_rate_table sys_pll_rate_table[] = { @@ -563,90 +577,90 @@ static struct clk_gate gxbb_clk81 = { }; /* Everything Else (EE) domain gates */ -static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0); -static MESON_GATE(dos, HHI_GCLK_MPEG0, 1); -static MESON_GATE(isa, HHI_GCLK_MPEG0, 5); -static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6); -static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7); -static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8); -static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9); -static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10); -static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11); -static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12); -static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13); -static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14); -static MESON_GATE(stream, HHI_GCLK_MPEG0, 15); -static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16); -static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17); -static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18); -static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19); -static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23); -static MESON_GATE(spi, HHI_GCLK_MPEG0, 30); - -static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2); -static MESON_GATE(eth, HHI_GCLK_MPEG1, 3); -static MESON_GATE(demux, HHI_GCLK_MPEG1, 4); -static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6); -static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7); -static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8); -static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9); -static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10); -static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11); -static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12); -static MESON_GATE(adc, HHI_GCLK_MPEG1, 13); -static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14); -static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15); -static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16); -static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20); -static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21); -static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22); -static MESON_GATE(reset, HHI_GCLK_MPEG1, 23); -static MESON_GATE(nand, HHI_GCLK_MPEG1, 24); -static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25); -static MESON_GATE(usb, HHI_GCLK_MPEG1, 26); -static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28); -static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29); -static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30); -static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31); - -static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1); -static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3); -static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4); -static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); -static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); -static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11); -static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12); -static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15); -static MESON_GATE(sana, HHI_GCLK_MPEG2, 22); -static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25); -static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); -static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29); - -static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1); -static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2); -static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3); -static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4); -static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8); -static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9); -static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10); -static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14); -static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16); -static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20); -static MESON_GATE(rng1, HHI_GCLK_OTHER, 21); -static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22); -static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24); -static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25); -static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26); -static MESON_GATE(edp, HHI_GCLK_OTHER, 31); +static GBXX_GATE(ddr, HHI_GCLK_MPEG0, 0); +static GBXX_GATE(dos, HHI_GCLK_MPEG0, 1); +static GBXX_GATE(isa, HHI_GCLK_MPEG0, 5); +static GBXX_GATE(pl301, HHI_GCLK_MPEG0, 6); +static GBXX_GATE(periphs, HHI_GCLK_MPEG0, 7); +static GBXX_GATE(spicc, HHI_GCLK_MPEG0, 8); +static GBXX_GATE(i2c, HHI_GCLK_MPEG0, 9); +static GBXX_GATE(sar_adc, HHI_GCLK_MPEG0, 10); +static GBXX_GATE(smart_card, HHI_GCLK_MPEG0, 11); +static GBXX_GATE(rng0, HHI_GCLK_MPEG0, 12); +static GBXX_GATE(uart0, HHI_GCLK_MPEG0, 13); +static GBXX_GATE(sdhc, HHI_GCLK_MPEG0, 14); +static GBXX_GATE(stream, HHI_GCLK_MPEG0, 15); +static GBXX_GATE(async_fifo, HHI_GCLK_MPEG0, 16); +static GBXX_GATE(sdio, HHI_GCLK_MPEG0, 17); +static GBXX_GATE(abuf, HHI_GCLK_MPEG0, 18); +static GBXX_GATE(hiu_iface, HHI_GCLK_MPEG0, 19); +static GBXX_GATE(assist_misc, HHI_GCLK_MPEG0, 23); +static GBXX_GATE(spi, HHI_GCLK_MPEG0, 30); + +static GBXX_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2); +static GBXX_GATE(eth, HHI_GCLK_MPEG1, 3); +static GBXX_GATE(demux, HHI_GCLK_MPEG1, 4); +static GBXX_GATE(aiu_glue, HHI_GCLK_MPEG1, 6); +static GBXX_GATE(iec958, HHI_GCLK_MPEG1, 7); +static GBXX_GATE(i2s_out, HHI_GCLK_MPEG1, 8); +static GBXX_GATE(amclk, HHI_GCLK_MPEG1, 9); +static GBXX_GATE(aififo2, HHI_GCLK_MPEG1, 10); +static GBXX_GATE(mixer, HHI_GCLK_MPEG1, 11); +static GBXX_GATE(mixer_iface, HHI_GCLK_MPEG1, 12); +static GBXX_GATE(adc, HHI_GCLK_MPEG1, 13); +static GBXX_GATE(blkmv, HHI_GCLK_MPEG1, 14); +static GBXX_GATE(aiu, HHI_GCLK_MPEG1, 15); +static GBXX_GATE(uart1, HHI_GCLK_MPEG1, 16); +static GBXX_GATE(g2d, HHI_GCLK_MPEG1, 20); +static GBXX_GATE(usb0, HHI_GCLK_MPEG1, 21); +static GBXX_GATE(usb1, HHI_GCLK_MPEG1, 22); +static GBXX_GATE(reset, HHI_GCLK_MPEG1, 23); +static GBXX_GATE(nand, HHI_GCLK_MPEG1, 24); +static GBXX_GATE(dos_parser, HHI_GCLK_MPEG1, 25); +static GBXX_GATE(usb, HHI_GCLK_MPEG1, 26); +static GBXX_GATE(vdin1, HHI_GCLK_MPEG1, 28); +static GBXX_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29); +static GBXX_GATE(efuse, HHI_GCLK_MPEG1, 30); +static GBXX_GATE(boot_rom, HHI_GCLK_MPEG1, 31); + +static GBXX_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1); +static GBXX_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); +static GBXX_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3); +static GBXX_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4); +static GBXX_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); +static GBXX_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); +static GBXX_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11); +static GBXX_GATE(dvin, HHI_GCLK_MPEG2, 12); +static GBXX_GATE(uart2, HHI_GCLK_MPEG2, 15); +static GBXX_GATE(sana, HHI_GCLK_MPEG2, 22); +static GBXX_GATE(vpu_intr, HHI_GCLK_MPEG2, 25); +static GBXX_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); +static GBXX_GATE(clk81_a53, HHI_GCLK_MPEG2, 29); + +static GBXX_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1); +static GBXX_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2); +static GBXX_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3); +static GBXX_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4); +static GBXX_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8); +static GBXX_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9); +static GBXX_GATE(dac_clk, HHI_GCLK_OTHER, 10); +static GBXX_GATE(aoclk_gate, HHI_GCLK_OTHER, 14); +static GBXX_GATE(iec958_gate, HHI_GCLK_OTHER, 16); +static GBXX_GATE(enc480p, HHI_GCLK_OTHER, 20); +static GBXX_GATE(rng1, HHI_GCLK_OTHER, 21); +static GBXX_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22); +static GBXX_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24); +static GBXX_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25); +static GBXX_GATE(vclk_other, HHI_GCLK_OTHER, 26); +static GBXX_GATE(edp, HHI_GCLK_OTHER, 31); /* Always On (AO) domain gates */ -static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0); -static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1); -static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2); -static MESON_GATE(ao_iface, HHI_GCLK_AO, 3); -static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4); +static GBXX_GATE(ao_media_cpu, HHI_GCLK_AO, 0); +static GBXX_GATE(ao_ahb_sram, HHI_GCLK_AO, 1); +static GBXX_GATE(ao_ahb_bus, HHI_GCLK_AO, 2); +static GBXX_GATE(ao_iface, HHI_GCLK_AO, 3); +static GBXX_GATE(ao_i2c, HHI_GCLK_AO, 4); /* Array of all clocks provided by this provider */ -- 2.5.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 5/7] gxbb: clk: Move MESON_GATE macro to gxbb 2016-07-05 17:56 ` [PATCH 5/7] gxbb: clk: Move MESON_GATE macro to gxbb Alexander Müller @ 2016-07-06 0:36 ` Michael Turquette 2016-07-13 17:43 ` Alexander Müller 0 siblings, 1 reply; 24+ messages in thread From: Michael Turquette @ 2016-07-06 0:36 UTC (permalink / raw) To: Alexander Müller, linux-clk, linux-amlogic Hi Alexander, Quoting Alexander M=C3=BCller (2016-07-05 10:56:29) > Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com> > --- > drivers/clk/meson/clkc.h | 14 ---- > drivers/clk/meson/gxbb.c | 176 +++++++++++++++++++++++++----------------= ------ > 2 files changed, 95 insertions(+), 95 deletions(-) > = > diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h > index 53326c3..061a01e 100644 > --- a/drivers/clk/meson/clkc.h > +++ b/drivers/clk/meson/clkc.h > @@ -97,20 +97,6 @@ struct meson_clk_mpll { > spinlock_t *lock; > }; > = > -#define MESON_GATE(_name, _reg, _bit) \ > -struct clk_gate gxbb_##_name =3D { = \ > - .reg =3D (void __iomem *) _reg, = \ > - .bit_idx =3D (_bit), = \ > - .lock =3D &clk_lock, = \ > - .hw.init =3D &(struct clk_init_data) { = \ > - .name =3D #_name, \ > - .ops =3D &clk_gate_ops, = \ > - .parent_names =3D (const char *[]){ "clk81" }, = \ > - .num_parents =3D 1, = \ > - .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), = \ > - }, \ > -}; Why can't this macro be shared between meson8b and gxbb? Looks identical to me, but maybe I missed something. > - > /* clk_ops */ > extern const struct clk_ops meson_clk_pll_ro_ops; > extern const struct clk_ops meson_clk_pll_ops; > diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c > index 007b715..0ea71be 100644 > --- a/drivers/clk/meson/gxbb.c > +++ b/drivers/clk/meson/gxbb.c > @@ -24,6 +24,20 @@ > #include "clkc.h" > #include "gxbb.h" > = > +#define GBXX_GATE(_name, _reg, _bit) \ s/GBXX/GXBB/g Including all of the static data further below ;-) Regards, Mike > +struct clk_gate gxbb_##_name =3D { = \ > + .reg =3D (void __iomem *) _reg, = \ > + .bit_idx =3D (_bit), = \ > + .lock =3D &clk_lock, = \ > + .hw.init =3D &(struct clk_init_data) { = \ > + .name =3D #_name, \ > + .ops =3D &clk_gate_ops, = \ > + .parent_names =3D (const char *[]){ "clk81" }, = \ > + .num_parents =3D 1, = \ > + .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), = \ > + }, \ > +}; > + > static DEFINE_SPINLOCK(clk_lock); > = > static const struct pll_rate_table sys_pll_rate_table[] =3D { > @@ -563,90 +577,90 @@ static struct clk_gate gxbb_clk81 =3D { > }; > = > /* Everything Else (EE) domain gates */ > -static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0); > -static MESON_GATE(dos, HHI_GCLK_MPEG0, 1); > -static MESON_GATE(isa, HHI_GCLK_MPEG0, 5); > -static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6); > -static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7); > -static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8); > -static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9); > -static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10); > -static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11); > -static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12); > -static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13); > -static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14); > -static MESON_GATE(stream, HHI_GCLK_MPEG0, 15); > -static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16); > -static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17); > -static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18); > -static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19); > -static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23); > -static MESON_GATE(spi, HHI_GCLK_MPEG0, 30); > - > -static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2); > -static MESON_GATE(eth, HHI_GCLK_MPEG1, 3); > -static MESON_GATE(demux, HHI_GCLK_MPEG1, 4); > -static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6); > -static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7); > -static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8); > -static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9); > -static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10); > -static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11); > -static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12); > -static MESON_GATE(adc, HHI_GCLK_MPEG1, 13); > -static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14); > -static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15); > -static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16); > -static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20); > -static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21); > -static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22); > -static MESON_GATE(reset, HHI_GCLK_MPEG1, 23); > -static MESON_GATE(nand, HHI_GCLK_MPEG1, 24); > -static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25); > -static MESON_GATE(usb, HHI_GCLK_MPEG1, 26); > -static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28); > -static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29); > -static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30); > -static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31); > - > -static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1); > -static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); > -static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3); > -static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4); > -static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); > -static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); > -static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11); > -static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12); > -static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15); > -static MESON_GATE(sana, HHI_GCLK_MPEG2, 22); > -static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25); > -static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); > -static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29); > - > -static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1); > -static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2); > -static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3); > -static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4); > -static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8); > -static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9); > -static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10); > -static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14); > -static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16); > -static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20); > -static MESON_GATE(rng1, HHI_GCLK_OTHER, 21); > -static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22); > -static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24); > -static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25); > -static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26); > -static MESON_GATE(edp, HHI_GCLK_OTHER, 31); > +static GBXX_GATE(ddr, HHI_GCLK_MPEG0, 0); > +static GBXX_GATE(dos, HHI_GCLK_MPEG0, 1); > +static GBXX_GATE(isa, HHI_GCLK_MPEG0, 5); > +static GBXX_GATE(pl301, HHI_GCLK_MPEG0, 6); > +static GBXX_GATE(periphs, HHI_GCLK_MPEG0, 7); > +static GBXX_GATE(spicc, HHI_GCLK_MPEG0, 8); > +static GBXX_GATE(i2c, HHI_GCLK_MPEG0, 9); > +static GBXX_GATE(sar_adc, HHI_GCLK_MPEG0, 10); > +static GBXX_GATE(smart_card, HHI_GCLK_MPEG0, 11); > +static GBXX_GATE(rng0, HHI_GCLK_MPEG0, 12); > +static GBXX_GATE(uart0, HHI_GCLK_MPEG0, 13); > +static GBXX_GATE(sdhc, HHI_GCLK_MPEG0, 14); > +static GBXX_GATE(stream, HHI_GCLK_MPEG0, 15); > +static GBXX_GATE(async_fifo, HHI_GCLK_MPEG0, 16); > +static GBXX_GATE(sdio, HHI_GCLK_MPEG0, 17); > +static GBXX_GATE(abuf, HHI_GCLK_MPEG0, 18); > +static GBXX_GATE(hiu_iface, HHI_GCLK_MPEG0, 19); > +static GBXX_GATE(assist_misc, HHI_GCLK_MPEG0, 23); > +static GBXX_GATE(spi, HHI_GCLK_MPEG0, 30); > + > +static GBXX_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2); > +static GBXX_GATE(eth, HHI_GCLK_MPEG1, 3); > +static GBXX_GATE(demux, HHI_GCLK_MPEG1, 4); > +static GBXX_GATE(aiu_glue, HHI_GCLK_MPEG1, 6); > +static GBXX_GATE(iec958, HHI_GCLK_MPEG1, 7); > +static GBXX_GATE(i2s_out, HHI_GCLK_MPEG1, 8); > +static GBXX_GATE(amclk, HHI_GCLK_MPEG1, 9); > +static GBXX_GATE(aififo2, HHI_GCLK_MPEG1, 10); > +static GBXX_GATE(mixer, HHI_GCLK_MPEG1, 11); > +static GBXX_GATE(mixer_iface, HHI_GCLK_MPEG1, 12); > +static GBXX_GATE(adc, HHI_GCLK_MPEG1, 13); > +static GBXX_GATE(blkmv, HHI_GCLK_MPEG1, 14); > +static GBXX_GATE(aiu, HHI_GCLK_MPEG1, 15); > +static GBXX_GATE(uart1, HHI_GCLK_MPEG1, 16); > +static GBXX_GATE(g2d, HHI_GCLK_MPEG1, 20); > +static GBXX_GATE(usb0, HHI_GCLK_MPEG1, 21); > +static GBXX_GATE(usb1, HHI_GCLK_MPEG1, 22); > +static GBXX_GATE(reset, HHI_GCLK_MPEG1, 23); > +static GBXX_GATE(nand, HHI_GCLK_MPEG1, 24); > +static GBXX_GATE(dos_parser, HHI_GCLK_MPEG1, 25); > +static GBXX_GATE(usb, HHI_GCLK_MPEG1, 26); > +static GBXX_GATE(vdin1, HHI_GCLK_MPEG1, 28); > +static GBXX_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29); > +static GBXX_GATE(efuse, HHI_GCLK_MPEG1, 30); > +static GBXX_GATE(boot_rom, HHI_GCLK_MPEG1, 31); > + > +static GBXX_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1); > +static GBXX_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); > +static GBXX_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3); > +static GBXX_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4); > +static GBXX_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); > +static GBXX_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); > +static GBXX_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11); > +static GBXX_GATE(dvin, HHI_GCLK_MPEG2, 12); > +static GBXX_GATE(uart2, HHI_GCLK_MPEG2, 15); > +static GBXX_GATE(sana, HHI_GCLK_MPEG2, 22); > +static GBXX_GATE(vpu_intr, HHI_GCLK_MPEG2, 25); > +static GBXX_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); > +static GBXX_GATE(clk81_a53, HHI_GCLK_MPEG2, 29); > + > +static GBXX_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1); > +static GBXX_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2); > +static GBXX_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3); > +static GBXX_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4); > +static GBXX_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8); > +static GBXX_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9); > +static GBXX_GATE(dac_clk, HHI_GCLK_OTHER, 10); > +static GBXX_GATE(aoclk_gate, HHI_GCLK_OTHER, 14); > +static GBXX_GATE(iec958_gate, HHI_GCLK_OTHER, 16); > +static GBXX_GATE(enc480p, HHI_GCLK_OTHER, 20); > +static GBXX_GATE(rng1, HHI_GCLK_OTHER, 21); > +static GBXX_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22); > +static GBXX_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24); > +static GBXX_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25); > +static GBXX_GATE(vclk_other, HHI_GCLK_OTHER, 26); > +static GBXX_GATE(edp, HHI_GCLK_OTHER, 31); > = > /* Always On (AO) domain gates */ > = > -static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0); > -static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1); > -static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2); > -static MESON_GATE(ao_iface, HHI_GCLK_AO, 3); > -static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4); > +static GBXX_GATE(ao_media_cpu, HHI_GCLK_AO, 0); > +static GBXX_GATE(ao_ahb_sram, HHI_GCLK_AO, 1); > +static GBXX_GATE(ao_ahb_bus, HHI_GCLK_AO, 2); > +static GBXX_GATE(ao_iface, HHI_GCLK_AO, 3); > +static GBXX_GATE(ao_i2c, HHI_GCLK_AO, 4); > = > /* Array of all clocks provided by this provider */ > = > -- = > 2.5.0 >=20 ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 5/7] gxbb: clk: Move MESON_GATE macro to gxbb 2016-07-06 0:36 ` Michael Turquette @ 2016-07-13 17:43 ` Alexander Müller 2016-07-13 21:25 ` Michael Turquette 0 siblings, 1 reply; 24+ messages in thread From: Alexander Müller @ 2016-07-13 17:43 UTC (permalink / raw) To: Michael Turquette; +Cc: linux-clk, linux-amlogic I moved the macro because of the struct variable name which is = gxbb_##_name here. > On 06 Jul 2016, at 02:36, Michael Turquette <mturquette@baylibre.com> = wrote: >=20 > Hi Alexander, >=20 > Quoting Alexander M=C3=BCller (2016-07-05 10:56:29) >> Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com> >> --- >> drivers/clk/meson/clkc.h | 14 ---- >> drivers/clk/meson/gxbb.c | 176 = +++++++++++++++++++++++++---------------------- >> 2 files changed, 95 insertions(+), 95 deletions(-) >>=20 >> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h >> index 53326c3..061a01e 100644 >> --- a/drivers/clk/meson/clkc.h >> +++ b/drivers/clk/meson/clkc.h >> @@ -97,20 +97,6 @@ struct meson_clk_mpll { >> spinlock_t *lock; >> }; >>=20 >> -#define MESON_GATE(_name, _reg, _bit) = \ >> -struct clk_gate gxbb_##_name =3D { = \ >> - .reg =3D (void __iomem *) _reg, = \ >> - .bit_idx =3D (_bit), = \ >> - .lock =3D &clk_lock, = \ >> - .hw.init =3D &(struct clk_init_data) { = \ >> - .name =3D #_name, \ >> - .ops =3D &clk_gate_ops, = \ >> - .parent_names =3D (const char *[]){ "clk81" }, = \ >> - .num_parents =3D 1, = \ >> - .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), = \ >> - }, = \ >> -}; >=20 > Why can't this macro be shared between meson8b and gxbb? Looks = identical > to me, but maybe I missed something. >=20 >> - >> /* clk_ops */ >> extern const struct clk_ops meson_clk_pll_ro_ops; >> extern const struct clk_ops meson_clk_pll_ops; >> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c >> index 007b715..0ea71be 100644 >> --- a/drivers/clk/meson/gxbb.c >> +++ b/drivers/clk/meson/gxbb.c >> @@ -24,6 +24,20 @@ >> #include "clkc.h" >> #include "gxbb.h" >>=20 >> +#define GBXX_GATE(_name, _reg, _bit) = \ >=20 > s/GBXX/GXBB/g >=20 > Including all of the static data further below ;-) >=20 > Regards, > Mike >=20 >> +struct clk_gate gxbb_##_name =3D { = \ >> + .reg =3D (void __iomem *) _reg, = \ >> + .bit_idx =3D (_bit), = \ >> + .lock =3D &clk_lock, = \ >> + .hw.init =3D &(struct clk_init_data) { = \ >> + .name =3D #_name, \ >> + .ops =3D &clk_gate_ops, = \ >> + .parent_names =3D (const char *[]){ "clk81" }, = \ >> + .num_parents =3D 1, = \ >> + .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), = \ >> + }, = \ >> +}; >> + >> static DEFINE_SPINLOCK(clk_lock); >>=20 >> static const struct pll_rate_table sys_pll_rate_table[] =3D { >> @@ -563,90 +577,90 @@ static struct clk_gate gxbb_clk81 =3D { >> }; >>=20 >> /* Everything Else (EE) domain gates */ >> -static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0); >> -static MESON_GATE(dos, HHI_GCLK_MPEG0, 1); >> -static MESON_GATE(isa, HHI_GCLK_MPEG0, 5); >> -static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6); >> -static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7); >> -static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8); >> -static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9); >> -static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10); >> -static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11); >> -static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12); >> -static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13); >> -static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14); >> -static MESON_GATE(stream, HHI_GCLK_MPEG0, 15); >> -static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16); >> -static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17); >> -static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18); >> -static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19); >> -static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23); >> -static MESON_GATE(spi, HHI_GCLK_MPEG0, 30); >> - >> -static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2); >> -static MESON_GATE(eth, HHI_GCLK_MPEG1, 3); >> -static MESON_GATE(demux, HHI_GCLK_MPEG1, 4); >> -static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6); >> -static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7); >> -static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8); >> -static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9); >> -static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10); >> -static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11); >> -static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12); >> -static MESON_GATE(adc, HHI_GCLK_MPEG1, 13); >> -static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14); >> -static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15); >> -static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16); >> -static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20); >> -static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21); >> -static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22); >> -static MESON_GATE(reset, HHI_GCLK_MPEG1, 23); >> -static MESON_GATE(nand, HHI_GCLK_MPEG1, 24); >> -static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25); >> -static MESON_GATE(usb, HHI_GCLK_MPEG1, 26); >> -static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28); >> -static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29); >> -static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30); >> -static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31); >> - >> -static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1); >> -static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); >> -static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3); >> -static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4); >> -static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); >> -static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); >> -static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11); >> -static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12); >> -static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15); >> -static MESON_GATE(sana, HHI_GCLK_MPEG2, 22); >> -static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25); >> -static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); >> -static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29); >> - >> -static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1); >> -static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2); >> -static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3); >> -static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4); >> -static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8); >> -static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9); >> -static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10); >> -static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14); >> -static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16); >> -static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20); >> -static MESON_GATE(rng1, HHI_GCLK_OTHER, 21); >> -static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22); >> -static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24); >> -static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25); >> -static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26); >> -static MESON_GATE(edp, HHI_GCLK_OTHER, 31); >> +static GBXX_GATE(ddr, HHI_GCLK_MPEG0, 0); >> +static GBXX_GATE(dos, HHI_GCLK_MPEG0, 1); >> +static GBXX_GATE(isa, HHI_GCLK_MPEG0, 5); >> +static GBXX_GATE(pl301, HHI_GCLK_MPEG0, 6); >> +static GBXX_GATE(periphs, HHI_GCLK_MPEG0, 7); >> +static GBXX_GATE(spicc, HHI_GCLK_MPEG0, 8); >> +static GBXX_GATE(i2c, HHI_GCLK_MPEG0, 9); >> +static GBXX_GATE(sar_adc, HHI_GCLK_MPEG0, 10); >> +static GBXX_GATE(smart_card, HHI_GCLK_MPEG0, 11); >> +static GBXX_GATE(rng0, HHI_GCLK_MPEG0, 12); >> +static GBXX_GATE(uart0, HHI_GCLK_MPEG0, 13); >> +static GBXX_GATE(sdhc, HHI_GCLK_MPEG0, 14); >> +static GBXX_GATE(stream, HHI_GCLK_MPEG0, 15); >> +static GBXX_GATE(async_fifo, HHI_GCLK_MPEG0, 16); >> +static GBXX_GATE(sdio, HHI_GCLK_MPEG0, 17); >> +static GBXX_GATE(abuf, HHI_GCLK_MPEG0, 18); >> +static GBXX_GATE(hiu_iface, HHI_GCLK_MPEG0, 19); >> +static GBXX_GATE(assist_misc, HHI_GCLK_MPEG0, 23); >> +static GBXX_GATE(spi, HHI_GCLK_MPEG0, 30); >> + >> +static GBXX_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2); >> +static GBXX_GATE(eth, HHI_GCLK_MPEG1, 3); >> +static GBXX_GATE(demux, HHI_GCLK_MPEG1, 4); >> +static GBXX_GATE(aiu_glue, HHI_GCLK_MPEG1, 6); >> +static GBXX_GATE(iec958, HHI_GCLK_MPEG1, 7); >> +static GBXX_GATE(i2s_out, HHI_GCLK_MPEG1, 8); >> +static GBXX_GATE(amclk, HHI_GCLK_MPEG1, 9); >> +static GBXX_GATE(aififo2, HHI_GCLK_MPEG1, 10); >> +static GBXX_GATE(mixer, HHI_GCLK_MPEG1, 11); >> +static GBXX_GATE(mixer_iface, HHI_GCLK_MPEG1, 12); >> +static GBXX_GATE(adc, HHI_GCLK_MPEG1, 13); >> +static GBXX_GATE(blkmv, HHI_GCLK_MPEG1, 14); >> +static GBXX_GATE(aiu, HHI_GCLK_MPEG1, 15); >> +static GBXX_GATE(uart1, HHI_GCLK_MPEG1, 16); >> +static GBXX_GATE(g2d, HHI_GCLK_MPEG1, 20); >> +static GBXX_GATE(usb0, HHI_GCLK_MPEG1, 21); >> +static GBXX_GATE(usb1, HHI_GCLK_MPEG1, 22); >> +static GBXX_GATE(reset, HHI_GCLK_MPEG1, 23); >> +static GBXX_GATE(nand, HHI_GCLK_MPEG1, 24); >> +static GBXX_GATE(dos_parser, HHI_GCLK_MPEG1, 25); >> +static GBXX_GATE(usb, HHI_GCLK_MPEG1, 26); >> +static GBXX_GATE(vdin1, HHI_GCLK_MPEG1, 28); >> +static GBXX_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29); >> +static GBXX_GATE(efuse, HHI_GCLK_MPEG1, 30); >> +static GBXX_GATE(boot_rom, HHI_GCLK_MPEG1, 31); >> + >> +static GBXX_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1); >> +static GBXX_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); >> +static GBXX_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3); >> +static GBXX_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4); >> +static GBXX_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); >> +static GBXX_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); >> +static GBXX_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11); >> +static GBXX_GATE(dvin, HHI_GCLK_MPEG2, 12); >> +static GBXX_GATE(uart2, HHI_GCLK_MPEG2, 15); >> +static GBXX_GATE(sana, HHI_GCLK_MPEG2, 22); >> +static GBXX_GATE(vpu_intr, HHI_GCLK_MPEG2, 25); >> +static GBXX_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); >> +static GBXX_GATE(clk81_a53, HHI_GCLK_MPEG2, 29); >> + >> +static GBXX_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1); >> +static GBXX_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2); >> +static GBXX_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3); >> +static GBXX_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4); >> +static GBXX_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8); >> +static GBXX_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9); >> +static GBXX_GATE(dac_clk, HHI_GCLK_OTHER, 10); >> +static GBXX_GATE(aoclk_gate, HHI_GCLK_OTHER, 14); >> +static GBXX_GATE(iec958_gate, HHI_GCLK_OTHER, 16); >> +static GBXX_GATE(enc480p, HHI_GCLK_OTHER, 20); >> +static GBXX_GATE(rng1, HHI_GCLK_OTHER, 21); >> +static GBXX_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22); >> +static GBXX_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24); >> +static GBXX_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25); >> +static GBXX_GATE(vclk_other, HHI_GCLK_OTHER, 26); >> +static GBXX_GATE(edp, HHI_GCLK_OTHER, 31); >>=20 >> /* Always On (AO) domain gates */ >>=20 >> -static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0); >> -static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1); >> -static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2); >> -static MESON_GATE(ao_iface, HHI_GCLK_AO, 3); >> -static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4); >> +static GBXX_GATE(ao_media_cpu, HHI_GCLK_AO, 0); >> +static GBXX_GATE(ao_ahb_sram, HHI_GCLK_AO, 1); >> +static GBXX_GATE(ao_ahb_bus, HHI_GCLK_AO, 2); >> +static GBXX_GATE(ao_iface, HHI_GCLK_AO, 3); >> +static GBXX_GATE(ao_i2c, HHI_GCLK_AO, 4); >>=20 >> /* Array of all clocks provided by this provider */ >>=20 >> --=20 >> 2.5.0 ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 5/7] gxbb: clk: Move MESON_GATE macro to gxbb 2016-07-13 17:43 ` Alexander Müller @ 2016-07-13 21:25 ` Michael Turquette 0 siblings, 0 replies; 24+ messages in thread From: Michael Turquette @ 2016-07-13 21:25 UTC (permalink / raw) To: Alexander Müller; +Cc: linux-clk, linux-amlogic Hi Alexander, Quoting Alexander M=C3=BCller (2016-07-13 10:43:51) > I moved the macro because of the struct variable name which is gxbb_##_na= me here. Do you mind not top-posting? It makes it easier to maintain context when reviewing 74927432 mails. Thanks, Mike > = > > On 06 Jul 2016, at 02:36, Michael Turquette <mturquette@baylibre.com> w= rote: > > = > > Hi Alexander, > > = > > Quoting Alexander M=C3=BCller (2016-07-05 10:56:29) > >> Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com> > >> --- > >> drivers/clk/meson/clkc.h | 14 ---- > >> drivers/clk/meson/gxbb.c | 176 +++++++++++++++++++++++++--------------= -------- > >> 2 files changed, 95 insertions(+), 95 deletions(-) > >> = > >> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h > >> index 53326c3..061a01e 100644 > >> --- a/drivers/clk/meson/clkc.h > >> +++ b/drivers/clk/meson/clkc.h > >> @@ -97,20 +97,6 @@ struct meson_clk_mpll { > >> spinlock_t *lock; > >> }; > >> = > >> -#define MESON_GATE(_name, _reg, _bit) = \ > >> -struct clk_gate gxbb_##_name =3D { = \ > >> - .reg =3D (void __iomem *) _reg, = \ > >> - .bit_idx =3D (_bit), = \ > >> - .lock =3D &clk_lock, = \ > >> - .hw.init =3D &(struct clk_init_data) { = \ > >> - .name =3D #_name, \ > >> - .ops =3D &clk_gate_ops, = \ > >> - .parent_names =3D (const char *[]){ "clk81" }, = \ > >> - .num_parents =3D 1, = \ > >> - .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), = \ > >> - }, = \ > >> -}; > > = > > Why can't this macro be shared between meson8b and gxbb? Looks identical > > to me, but maybe I missed something. > > = > >> - > >> /* clk_ops */ > >> extern const struct clk_ops meson_clk_pll_ro_ops; > >> extern const struct clk_ops meson_clk_pll_ops; > >> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c > >> index 007b715..0ea71be 100644 > >> --- a/drivers/clk/meson/gxbb.c > >> +++ b/drivers/clk/meson/gxbb.c > >> @@ -24,6 +24,20 @@ > >> #include "clkc.h" > >> #include "gxbb.h" > >> = > >> +#define GBXX_GATE(_name, _reg, _bit) = \ > > = > > s/GBXX/GXBB/g > > = > > Including all of the static data further below ;-) > > = > > Regards, > > Mike > > = > >> +struct clk_gate gxbb_##_name =3D { = \ > >> + .reg =3D (void __iomem *) _reg, = \ > >> + .bit_idx =3D (_bit), = \ > >> + .lock =3D &clk_lock, = \ > >> + .hw.init =3D &(struct clk_init_data) { = \ > >> + .name =3D #_name, \ > >> + .ops =3D &clk_gate_ops, = \ > >> + .parent_names =3D (const char *[]){ "clk81" }, = \ > >> + .num_parents =3D 1, = \ > >> + .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), = \ > >> + }, = \ > >> +}; > >> + > >> static DEFINE_SPINLOCK(clk_lock); > >> = > >> static const struct pll_rate_table sys_pll_rate_table[] =3D { > >> @@ -563,90 +577,90 @@ static struct clk_gate gxbb_clk81 =3D { > >> }; > >> = > >> /* Everything Else (EE) domain gates */ > >> -static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0); > >> -static MESON_GATE(dos, HHI_GCLK_MPEG0, 1); > >> -static MESON_GATE(isa, HHI_GCLK_MPEG0, 5); > >> -static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6); > >> -static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7); > >> -static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8); > >> -static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9); > >> -static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10); > >> -static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11); > >> -static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12); > >> -static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13); > >> -static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14); > >> -static MESON_GATE(stream, HHI_GCLK_MPEG0, 15); > >> -static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16); > >> -static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17); > >> -static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18); > >> -static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19); > >> -static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23); > >> -static MESON_GATE(spi, HHI_GCLK_MPEG0, 30); > >> - > >> -static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2); > >> -static MESON_GATE(eth, HHI_GCLK_MPEG1, 3); > >> -static MESON_GATE(demux, HHI_GCLK_MPEG1, 4); > >> -static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6); > >> -static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7); > >> -static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8); > >> -static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9); > >> -static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10); > >> -static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11); > >> -static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12); > >> -static MESON_GATE(adc, HHI_GCLK_MPEG1, 13); > >> -static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14); > >> -static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15); > >> -static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16); > >> -static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20); > >> -static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21); > >> -static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22); > >> -static MESON_GATE(reset, HHI_GCLK_MPEG1, 23); > >> -static MESON_GATE(nand, HHI_GCLK_MPEG1, 24); > >> -static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25); > >> -static MESON_GATE(usb, HHI_GCLK_MPEG1, 26); > >> -static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28); > >> -static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29); > >> -static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30); > >> -static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31); > >> - > >> -static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1); > >> -static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); > >> -static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3); > >> -static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4); > >> -static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); > >> -static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); > >> -static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11); > >> -static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12); > >> -static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15); > >> -static MESON_GATE(sana, HHI_GCLK_MPEG2, 22); > >> -static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25); > >> -static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); > >> -static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29); > >> - > >> -static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1); > >> -static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2); > >> -static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3); > >> -static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4); > >> -static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8); > >> -static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9); > >> -static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10); > >> -static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14); > >> -static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16); > >> -static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20); > >> -static MESON_GATE(rng1, HHI_GCLK_OTHER, 21); > >> -static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22); > >> -static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24); > >> -static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25); > >> -static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26); > >> -static MESON_GATE(edp, HHI_GCLK_OTHER, 31); > >> +static GBXX_GATE(ddr, HHI_GCLK_MPEG0, 0); > >> +static GBXX_GATE(dos, HHI_GCLK_MPEG0, 1); > >> +static GBXX_GATE(isa, HHI_GCLK_MPEG0, 5); > >> +static GBXX_GATE(pl301, HHI_GCLK_MPEG0, 6); > >> +static GBXX_GATE(periphs, HHI_GCLK_MPEG0, 7); > >> +static GBXX_GATE(spicc, HHI_GCLK_MPEG0, 8); > >> +static GBXX_GATE(i2c, HHI_GCLK_MPEG0, 9); > >> +static GBXX_GATE(sar_adc, HHI_GCLK_MPEG0, 10); > >> +static GBXX_GATE(smart_card, HHI_GCLK_MPEG0, 11); > >> +static GBXX_GATE(rng0, HHI_GCLK_MPEG0, 12); > >> +static GBXX_GATE(uart0, HHI_GCLK_MPEG0, 13); > >> +static GBXX_GATE(sdhc, HHI_GCLK_MPEG0, 14); > >> +static GBXX_GATE(stream, HHI_GCLK_MPEG0, 15); > >> +static GBXX_GATE(async_fifo, HHI_GCLK_MPEG0, 16); > >> +static GBXX_GATE(sdio, HHI_GCLK_MPEG0, 17); > >> +static GBXX_GATE(abuf, HHI_GCLK_MPEG0, 18); > >> +static GBXX_GATE(hiu_iface, HHI_GCLK_MPEG0, 19); > >> +static GBXX_GATE(assist_misc, HHI_GCLK_MPEG0, 23); > >> +static GBXX_GATE(spi, HHI_GCLK_MPEG0, 30); > >> + > >> +static GBXX_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2); > >> +static GBXX_GATE(eth, HHI_GCLK_MPEG1, 3); > >> +static GBXX_GATE(demux, HHI_GCLK_MPEG1, 4); > >> +static GBXX_GATE(aiu_glue, HHI_GCLK_MPEG1, 6); > >> +static GBXX_GATE(iec958, HHI_GCLK_MPEG1, 7); > >> +static GBXX_GATE(i2s_out, HHI_GCLK_MPEG1, 8); > >> +static GBXX_GATE(amclk, HHI_GCLK_MPEG1, 9); > >> +static GBXX_GATE(aififo2, HHI_GCLK_MPEG1, 10); > >> +static GBXX_GATE(mixer, HHI_GCLK_MPEG1, 11); > >> +static GBXX_GATE(mixer_iface, HHI_GCLK_MPEG1, 12); > >> +static GBXX_GATE(adc, HHI_GCLK_MPEG1, 13); > >> +static GBXX_GATE(blkmv, HHI_GCLK_MPEG1, 14); > >> +static GBXX_GATE(aiu, HHI_GCLK_MPEG1, 15); > >> +static GBXX_GATE(uart1, HHI_GCLK_MPEG1, 16); > >> +static GBXX_GATE(g2d, HHI_GCLK_MPEG1, 20); > >> +static GBXX_GATE(usb0, HHI_GCLK_MPEG1, 21); > >> +static GBXX_GATE(usb1, HHI_GCLK_MPEG1, 22); > >> +static GBXX_GATE(reset, HHI_GCLK_MPEG1, 23); > >> +static GBXX_GATE(nand, HHI_GCLK_MPEG1, 24); > >> +static GBXX_GATE(dos_parser, HHI_GCLK_MPEG1, 25); > >> +static GBXX_GATE(usb, HHI_GCLK_MPEG1, 26); > >> +static GBXX_GATE(vdin1, HHI_GCLK_MPEG1, 28); > >> +static GBXX_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29); > >> +static GBXX_GATE(efuse, HHI_GCLK_MPEG1, 30); > >> +static GBXX_GATE(boot_rom, HHI_GCLK_MPEG1, 31); > >> + > >> +static GBXX_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1); > >> +static GBXX_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); > >> +static GBXX_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3); > >> +static GBXX_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4); > >> +static GBXX_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); > >> +static GBXX_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); > >> +static GBXX_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11); > >> +static GBXX_GATE(dvin, HHI_GCLK_MPEG2, 12); > >> +static GBXX_GATE(uart2, HHI_GCLK_MPEG2, 15); > >> +static GBXX_GATE(sana, HHI_GCLK_MPEG2, 22); > >> +static GBXX_GATE(vpu_intr, HHI_GCLK_MPEG2, 25); > >> +static GBXX_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); > >> +static GBXX_GATE(clk81_a53, HHI_GCLK_MPEG2, 29); > >> + > >> +static GBXX_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1); > >> +static GBXX_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2); > >> +static GBXX_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3); > >> +static GBXX_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4); > >> +static GBXX_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8); > >> +static GBXX_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9); > >> +static GBXX_GATE(dac_clk, HHI_GCLK_OTHER, 10); > >> +static GBXX_GATE(aoclk_gate, HHI_GCLK_OTHER, 14); > >> +static GBXX_GATE(iec958_gate, HHI_GCLK_OTHER, 16); > >> +static GBXX_GATE(enc480p, HHI_GCLK_OTHER, 20); > >> +static GBXX_GATE(rng1, HHI_GCLK_OTHER, 21); > >> +static GBXX_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22); > >> +static GBXX_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24); > >> +static GBXX_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25); > >> +static GBXX_GATE(vclk_other, HHI_GCLK_OTHER, 26); > >> +static GBXX_GATE(edp, HHI_GCLK_OTHER, 31); > >> = > >> /* Always On (AO) domain gates */ > >> = > >> -static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0); > >> -static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1); > >> -static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2); > >> -static MESON_GATE(ao_iface, HHI_GCLK_AO, 3); > >> -static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4); > >> +static GBXX_GATE(ao_media_cpu, HHI_GCLK_AO, 0); > >> +static GBXX_GATE(ao_ahb_sram, HHI_GCLK_AO, 1); > >> +static GBXX_GATE(ao_ahb_bus, HHI_GCLK_AO, 2); > >> +static GBXX_GATE(ao_iface, HHI_GCLK_AO, 3); > >> +static GBXX_GATE(ao_i2c, HHI_GCLK_AO, 4); > >> = > >> /* Array of all clocks provided by this provider */ > >> = > >> -- = > >> 2.5.0 >=20 ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 6/7] meson: clk: Add support for clock gates 2016-07-05 17:56 [PATCH 0/7] Add Amlogic meson8b clock gates Alexander Müller ` (4 preceding siblings ...) 2016-07-05 17:56 ` [PATCH 5/7] gxbb: clk: Move MESON_GATE macro to gxbb Alexander Müller @ 2016-07-05 17:56 ` Alexander Müller 2016-07-05 18:01 ` Ben Dooks 2016-07-05 17:56 ` [PATCH 7/7] arm: amlogic: select meson8b clk driver Alexander Müller 6 siblings, 1 reply; 24+ messages in thread From: Alexander Müller @ 2016-07-05 17:56 UTC (permalink / raw) To: mturquette, linux-clk, linux-amlogic This patch adds support for the meson8b clock gates. Most of them are disabled by Amlogic U-Boot, but need to be enabled for ethernet, USB and many other components. Signed-off-by: Alexander Müller <serveralex@gmail.com> --- drivers/clk/meson/meson8b.c | 263 ++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/meson8b.h | 5 + 2 files changed, 268 insertions(+) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 0c6e26f..9a2d0c1 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -28,6 +28,20 @@ #include "clkc.h" #include "meson8b.h" +#define MESON8B_GATE(_name, _reg, _bit) \ +struct clk_gate meson8b_##_name = { \ + .reg = (void __iomem *) _reg, \ + .bit_idx = (_bit), \ + .lock = &clk_lock, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_gate_ops, \ + .parent_names = (const char *[]){ "clk81" }, \ + .num_parents = 1, \ + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ + }, \ +}; + static DEFINE_SPINLOCK(clk_lock); static const struct pll_rate_table sys_pll_rate_table[] = { @@ -312,6 +326,92 @@ struct clk_gate meson8b_clk81 = { }, }; +/* Everything Else (EE) domain gates */ + +static MESON8B_GATE(ddr, HHI_GCLK_MPEG0, 0); +static MESON8B_GATE(dos, HHI_GCLK_MPEG0, 1); +static MESON8B_GATE(isa, HHI_GCLK_MPEG0, 5); +static MESON8B_GATE(pl301, HHI_GCLK_MPEG0, 6); +static MESON8B_GATE(periphs, HHI_GCLK_MPEG0, 7); +static MESON8B_GATE(spicc, HHI_GCLK_MPEG0, 8); +static MESON8B_GATE(i2c, HHI_GCLK_MPEG0, 9); +static MESON8B_GATE(sar_adc, HHI_GCLK_MPEG0, 10); +static MESON8B_GATE(smart_card, HHI_GCLK_MPEG0, 11); +static MESON8B_GATE(rng0, HHI_GCLK_MPEG0, 12); +static MESON8B_GATE(uart0, HHI_GCLK_MPEG0, 13); +static MESON8B_GATE(sdhc, HHI_GCLK_MPEG0, 14); +static MESON8B_GATE(stream, HHI_GCLK_MPEG0, 15); +static MESON8B_GATE(async_fifo, HHI_GCLK_MPEG0, 16); +static MESON8B_GATE(sdio, HHI_GCLK_MPEG0, 17); +static MESON8B_GATE(abuf, HHI_GCLK_MPEG0, 18); +static MESON8B_GATE(hiu_iface, HHI_GCLK_MPEG0, 19); +static MESON8B_GATE(assist_misc, HHI_GCLK_MPEG0, 23); +static MESON8B_GATE(spi, HHI_GCLK_MPEG0, 30); + +static MESON8B_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2); +static MESON8B_GATE(eth, HHI_GCLK_MPEG1, 3); +static MESON8B_GATE(demux, HHI_GCLK_MPEG1, 4); +static MESON8B_GATE(aiu_glue, HHI_GCLK_MPEG1, 6); +static MESON8B_GATE(iec958, HHI_GCLK_MPEG1, 7); +static MESON8B_GATE(i2s_out, HHI_GCLK_MPEG1, 8); +static MESON8B_GATE(amclk, HHI_GCLK_MPEG1, 9); +static MESON8B_GATE(aififo2, HHI_GCLK_MPEG1, 10); +static MESON8B_GATE(mixer, HHI_GCLK_MPEG1, 11); +static MESON8B_GATE(mixer_iface, HHI_GCLK_MPEG1, 12); +static MESON8B_GATE(adc, HHI_GCLK_MPEG1, 13); +static MESON8B_GATE(blkmv, HHI_GCLK_MPEG1, 14); +static MESON8B_GATE(aiu, HHI_GCLK_MPEG1, 15); +static MESON8B_GATE(uart1, HHI_GCLK_MPEG1, 16); +static MESON8B_GATE(g2d, HHI_GCLK_MPEG1, 20); +static MESON8B_GATE(usb0, HHI_GCLK_MPEG1, 21); +static MESON8B_GATE(usb1, HHI_GCLK_MPEG1, 22); +static MESON8B_GATE(reset, HHI_GCLK_MPEG1, 23); +static MESON8B_GATE(nand, HHI_GCLK_MPEG1, 24); +static MESON8B_GATE(dos_parser, HHI_GCLK_MPEG1, 25); +static MESON8B_GATE(usb, HHI_GCLK_MPEG1, 26); +static MESON8B_GATE(vdin1, HHI_GCLK_MPEG1, 28); +static MESON8B_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29); +static MESON8B_GATE(efuse, HHI_GCLK_MPEG1, 30); +static MESON8B_GATE(boot_rom, HHI_GCLK_MPEG1, 31); + +static MESON8B_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1); +static MESON8B_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); +static MESON8B_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3); +static MESON8B_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4); +static MESON8B_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); +static MESON8B_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); +static MESON8B_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11); +static MESON8B_GATE(dvin, HHI_GCLK_MPEG2, 12); +static MESON8B_GATE(uart2, HHI_GCLK_MPEG2, 15); +static MESON8B_GATE(sana, HHI_GCLK_MPEG2, 22); +static MESON8B_GATE(vpu_intr, HHI_GCLK_MPEG2, 25); +static MESON8B_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); +static MESON8B_GATE(clk81_a9, HHI_GCLK_MPEG2, 29); + +static MESON8B_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1); +static MESON8B_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2); +static MESON8B_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3); +static MESON8B_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4); +static MESON8B_GATE(gclk_venci_int, HHI_GCLK_OTHER, 8); +static MESON8B_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9); +static MESON8B_GATE(dac_clk, HHI_GCLK_OTHER, 10); +static MESON8B_GATE(aoclk_gate, HHI_GCLK_OTHER, 14); +static MESON8B_GATE(iec958_gate, HHI_GCLK_OTHER, 16); +static MESON8B_GATE(enc480p, HHI_GCLK_OTHER, 20); +static MESON8B_GATE(rng1, HHI_GCLK_OTHER, 21); +static MESON8B_GATE(gclk_vencl_int, HHI_GCLK_OTHER, 22); +static MESON8B_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24); +static MESON8B_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25); +static MESON8B_GATE(vclk2_other, HHI_GCLK_OTHER, 26); +static MESON8B_GATE(edp, HHI_GCLK_OTHER, 31); + +/* Always On (AO) domain gates */ + +static MESON8B_GATE(ao_media_cpu, HHI_GCLK_AO, 0); +static MESON8B_GATE(ao_ahb_sram, HHI_GCLK_AO, 1); +static MESON8B_GATE(ao_ahb_bus, HHI_GCLK_AO, 2); +static MESON8B_GATE(ao_iface, HHI_GCLK_AO, 3); + static struct clk_hw_onecell_data meson8b_hw_onecell_data = { .hws = { [CLKID_XTAL] = &meson8b_xtal.hw, @@ -327,6 +427,83 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, [CLKID_CLK81] = &meson8b_clk81.hw, + [CLKID_DDR] = &meson8b_ddr.hw, + [CLKID_DOS] = &meson8b_dos.hw, + [CLKID_ISA] = &meson8b_isa.hw, + [CLKID_PL301] = &meson8b_pl301.hw, + [CLKID_PERIPHS] = &meson8b_periphs.hw, + [CLKID_SPICC] = &meson8b_spicc.hw, + [CLKID_I2C] = &meson8b_i2c.hw, + [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, + [CLKID_SMART_CARD] = &meson8b_smart_card.hw, + [CLKID_RNG0] = &meson8b_rng0.hw, + [CLKID_UART0] = &meson8b_uart0.hw, + [CLKID_SDHC] = &meson8b_sdhc.hw, + [CLKID_STREAM] = &meson8b_stream.hw, + [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, + [CLKID_SDIO] = &meson8b_sdio.hw, + [CLKID_ABUF] = &meson8b_abuf.hw, + [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, + [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, + [CLKID_SPI] = &meson8b_spi.hw, + [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, + [CLKID_ETH] = &meson8b_eth.hw, + [CLKID_DEMUX] = &meson8b_demux.hw, + [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, + [CLKID_IEC958] = &meson8b_iec958.hw, + [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, + [CLKID_AMCLK] = &meson8b_amclk.hw, + [CLKID_AIFIFO2] = &meson8b_aififo2.hw, + [CLKID_MIXER] = &meson8b_mixer.hw, + [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, + [CLKID_ADC] = &meson8b_adc.hw, + [CLKID_BLKMV] = &meson8b_blkmv.hw, + [CLKID_AIU] = &meson8b_aiu.hw, + [CLKID_UART1] = &meson8b_uart1.hw, + [CLKID_G2D] = &meson8b_g2d.hw, + [CLKID_USB0] = &meson8b_usb0.hw, + [CLKID_USB1] = &meson8b_usb1.hw, + [CLKID_RESET] = &meson8b_reset.hw, + [CLKID_NAND] = &meson8b_nand.hw, + [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, + [CLKID_USB] = &meson8b_usb.hw, + [CLKID_VDIN1] = &meson8b_vdin1.hw, + [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, + [CLKID_EFUSE] = &meson8b_efuse.hw, + [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, + [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, + [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, + [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, + [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, + [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, + [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, + [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, + [CLKID_DVIN] = &meson8b_dvin.hw, + [CLKID_UART2] = &meson8b_uart2.hw, + [CLKID_SANA] = &meson8b_sana.hw, + [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, + [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, + [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, + [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, + [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, + [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, + [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, + [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, + [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_vencp_int.hw, + [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, + [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, + [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, + [CLKID_ENC480P] = &meson8b_enc480p.hw, + [CLKID_RNG1] = &meson8b_rng1.hw, + [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, + [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, + [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, + [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, + [CLKID_EDP] = &meson8b_edp.hw, + [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, + [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, + [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, + [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, }, .num = CLK_NR_CLKS, }; @@ -337,6 +514,87 @@ static struct meson_clk_pll *const meson8b_clk_plls[] = { &meson8b_sys_pll, }; +static struct clk_gate *meson8b_clk_gates[] = { + &meson8b_clk81, + &meson8b_ddr, + &meson8b_dos, + &meson8b_isa, + &meson8b_pl301, + &meson8b_periphs, + &meson8b_spicc, + &meson8b_i2c, + &meson8b_sar_adc, + &meson8b_smart_card, + &meson8b_rng0, + &meson8b_uart0, + &meson8b_sdhc, + &meson8b_stream, + &meson8b_async_fifo, + &meson8b_sdio, + &meson8b_abuf, + &meson8b_hiu_iface, + &meson8b_assist_misc, + &meson8b_spi, + &meson8b_i2s_spdif, + &meson8b_eth, + &meson8b_demux, + &meson8b_aiu_glue, + &meson8b_iec958, + &meson8b_i2s_out, + &meson8b_amclk, + &meson8b_aififo2, + &meson8b_mixer, + &meson8b_mixer_iface, + &meson8b_adc, + &meson8b_blkmv, + &meson8b_aiu, + &meson8b_uart1, + &meson8b_g2d, + &meson8b_usb0, + &meson8b_usb1, + &meson8b_reset, + &meson8b_nand, + &meson8b_dos_parser, + &meson8b_usb, + &meson8b_vdin1, + &meson8b_ahb_arb0, + &meson8b_efuse, + &meson8b_boot_rom, + &meson8b_ahb_data_bus, + &meson8b_ahb_ctrl_bus, + &meson8b_hdmi_intr_sync, + &meson8b_hdmi_pclk, + &meson8b_usb1_ddr_bridge, + &meson8b_usb0_ddr_bridge, + &meson8b_mmc_pclk, + &meson8b_dvin, + &meson8b_uart2, + &meson8b_sana, + &meson8b_vpu_intr, + &meson8b_sec_ahb_ahb3_bridge, + &meson8b_clk81_a9, + &meson8b_vclk2_venci0, + &meson8b_vclk2_venci1, + &meson8b_vclk2_vencp0, + &meson8b_vclk2_vencp1, + &meson8b_gclk_venci_int, + &meson8b_gclk_vencp_int, + &meson8b_dac_clk, + &meson8b_aoclk_gate, + &meson8b_iec958_gate, + &meson8b_enc480p, + &meson8b_rng1, + &meson8b_gclk_vencl_int, + &meson8b_vclk2_venclmcc, + &meson8b_vclk2_vencl, + &meson8b_vclk2_other, + &meson8b_edp, + &meson8b_ao_media_cpu, + &meson8b_ao_ahb_sram, + &meson8b_ao_ahb_bus, + &meson8b_ao_iface, +}; + static int meson8b_clkc_probe(struct platform_device *pdev) { void __iomem *clk_base; @@ -364,6 +622,11 @@ static int meson8b_clkc_probe(struct platform_device *pdev) meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg; meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg; + /* Populate base address for gates */ + for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++) + meson8b_clk_gates[i]->reg = clk_base + + (u32)meson8b_clk_gates[i]->reg; + /* * register all clks * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index b2f29f7..8dffae0 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -30,6 +30,11 @@ * * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf */ +#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ +#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ +#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ +#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ +#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ -- 2.5.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] meson: clk: Add support for clock gates 2016-07-05 17:56 ` [PATCH 6/7] meson: clk: Add support for clock gates Alexander Müller @ 2016-07-05 18:01 ` Ben Dooks 2016-07-06 0:51 ` Michael Turquette 0 siblings, 1 reply; 24+ messages in thread From: Ben Dooks @ 2016-07-05 18:01 UTC (permalink / raw) To: Alexander Müller, mturquette, linux-clk, linux-amlogic On 05/07/16 18:56, Alexander Müller wrote: > This patch adds support for the meson8b clock gates. Most of > them are disabled by Amlogic U-Boot, but need to be enabled > for ethernet, USB and many other components. > > Signed-off-by: Alexander Müller <serveralex@gmail.com> > --- This seems to be a lot of structures for clocks that may never be use. I think it would be better to provide a custom lookup function that creates these as needed and use the ID in the dt as a offset+bit id. -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] meson: clk: Add support for clock gates 2016-07-05 18:01 ` Ben Dooks @ 2016-07-06 0:51 ` Michael Turquette 2016-07-06 7:35 ` Ben Dooks 0 siblings, 1 reply; 24+ messages in thread From: Michael Turquette @ 2016-07-06 0:51 UTC (permalink / raw) To: Ben Dooks, Alexander Müller, linux-clk, linux-amlogic Hi Ben, Quoting Ben Dooks (2016-07-05 11:01:14) > On 05/07/16 18:56, Alexander M=C3=BCller wrote: > > This patch adds support for the meson8b clock gates. Most of > > them are disabled by Amlogic U-Boot, but need to be enabled > > for ethernet, USB and many other components. > > = > > Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com> > > --- > = > This seems to be a lot of structures for clocks that may > never be use. I think it would be better to provide a custom > lookup function that creates these as needed and use the ID > in the dt as a offset+bit id. We want the real clocks registered so that we can disable spuriously enabled at late_initcall time with clk_disable_unused. Furthermore, I'd like to not represent all of these gates in the DT binding description (see my response to the earlier patches in this series), since it becomes ABI (and a maintenance nightmare). Regards, Mike > = > -- = > Ben Dooks http://www.codethink.co.uk/ > Senior Engineer Codethink - Providing Genius ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] meson: clk: Add support for clock gates 2016-07-06 0:51 ` Michael Turquette @ 2016-07-06 7:35 ` Ben Dooks 2016-07-06 8:11 ` Michael Turquette 0 siblings, 1 reply; 24+ messages in thread From: Ben Dooks @ 2016-07-06 7:35 UTC (permalink / raw) To: Michael Turquette, Alexander Müller, linux-clk, linux-amlogic On 06/07/16 01:51, Michael Turquette wrote: > Hi Ben, > > Quoting Ben Dooks (2016-07-05 11:01:14) >> On 05/07/16 18:56, Alexander Müller wrote: >>> This patch adds support for the meson8b clock gates. Most of >>> them are disabled by Amlogic U-Boot, but need to be enabled >>> for ethernet, USB and many other components. >>> >>> Signed-off-by: Alexander Müller <serveralex@gmail.com> >>> --- >> >> This seems to be a lot of structures for clocks that may >> never be use. I think it would be better to provide a custom >> lookup function that creates these as needed and use the ID >> in the dt as a offset+bit id. > > We want the real clocks registered so that we can disable spuriously > enabled at late_initcall time with clk_disable_unused. > > Furthermore, I'd like to not represent all of these gates in the DT > binding description (see my response to the earlier patches in this > series), since it becomes ABI (and a maintenance nightmare). Erm, so writing /more/ code and having them defined in /two/ places is a nightmare? Sounds more of a nightmare of having the ID in the DT represent the register/bit offset and then having them created at lookup time. -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] meson: clk: Add support for clock gates 2016-07-06 7:35 ` Ben Dooks @ 2016-07-06 8:11 ` Michael Turquette 2016-07-06 8:50 ` Ben Dooks 0 siblings, 1 reply; 24+ messages in thread From: Michael Turquette @ 2016-07-06 8:11 UTC (permalink / raw) To: Ben Dooks, Alexander Müller, linux-clk, linux-amlogic Quoting Ben Dooks (2016-07-06 00:35:28) > On 06/07/16 01:51, Michael Turquette wrote: > > Hi Ben, > > = > > Quoting Ben Dooks (2016-07-05 11:01:14) > >> On 05/07/16 18:56, Alexander M=C3=BCller wrote: > >>> This patch adds support for the meson8b clock gates. Most of > >>> them are disabled by Amlogic U-Boot, but need to be enabled > >>> for ethernet, USB and many other components. > >>> > >>> Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com> > >>> --- > >> > >> This seems to be a lot of structures for clocks that may > >> never be use. I think it would be better to provide a custom > >> lookup function that creates these as needed and use the ID > >> in the dt as a offset+bit id. > > = > > We want the real clocks registered so that we can disable spuriously > > enabled at late_initcall time with clk_disable_unused. > > = > > Furthermore, I'd like to not represent all of these gates in the DT > > binding description (see my response to the earlier patches in this > > series), since it becomes ABI (and a maintenance nightmare). > = > Erm, so writing /more/ code and having them defined in /two/ places > is a nightmare? Sounds more of a nightmare of having the ID in the DT > represent the register/bit offset and then having them created at > lookup time. I apologize, but I really don't understand what side of the argument that you are pushing for based on the above text. Something is a nightmare, but I'm not sure which design pattern you are attributing nightmare status too. Anyways, clock string name is required always, so even if you encode register and bitfield in DT cleverly, you've still got data in C, assuming your point was to remove stuff from C. That might change some day, but not today. Memory footprint should remain the same with either implementation. If you have an alternative implementation, patches are always welcome. Best regards, Mike > = > = > = > = > -- = > Ben Dooks http://www.codethink.co.uk/ > Senior Engineer Codethink - Providing Genius ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] meson: clk: Add support for clock gates 2016-07-06 8:11 ` Michael Turquette @ 2016-07-06 8:50 ` Ben Dooks 2016-07-06 20:36 ` Michael Turquette 0 siblings, 1 reply; 24+ messages in thread From: Ben Dooks @ 2016-07-06 8:50 UTC (permalink / raw) To: Michael Turquette, Alexander Müller, linux-clk, linux-amlogic On 06/07/16 09:11, Michael Turquette wrote: > Quoting Ben Dooks (2016-07-06 00:35:28) >> On 06/07/16 01:51, Michael Turquette wrote: >>> Hi Ben, >>> >>> Quoting Ben Dooks (2016-07-05 11:01:14) >>>> On 05/07/16 18:56, Alexander Müller wrote: >>>>> This patch adds support for the meson8b clock gates. Most of >>>>> them are disabled by Amlogic U-Boot, but need to be enabled >>>>> for ethernet, USB and many other components. >>>>> >>>>> Signed-off-by: Alexander Müller <serveralex@gmail.com> >>>>> --- >>>> >>>> This seems to be a lot of structures for clocks that may >>>> never be use. I think it would be better to provide a custom >>>> lookup function that creates these as needed and use the ID >>>> in the dt as a offset+bit id. >>> >>> We want the real clocks registered so that we can disable spuriously >>> enabled at late_initcall time with clk_disable_unused. >>> >>> Furthermore, I'd like to not represent all of these gates in the DT >>> binding description (see my response to the earlier patches in this >>> series), since it becomes ABI (and a maintenance nightmare). >> >> Erm, so writing /more/ code and having them defined in /two/ places >> is a nightmare? Sounds more of a nightmare of having the ID in the DT >> represent the register/bit offset and then having them created at >> lookup time. > > I apologize, but I really don't understand what side of the argument > that you are pushing for based on the above text. Something is a > nightmare, but I'm not sure which design pattern you are attributing > nightmare status too. > > Anyways, clock string name is required always, so even if you encode > register and bitfield in DT cleverly, you've still got data in C, > assuming your point was to remove stuff from C. That might change some > day, but not today. Memory footprint should remain the same with either > implementation. Is that actually useful for anything other than debug? > If you have an alternative implementation, patches are always welcome. I can think of a few ways we could do this, depending on how much code is to be added either to the meson-clk driver or to something that is more generic. If we add gate support to the meson clkock driver, we could have two implementations, we can either encode the reg/bit into the ID and have a valid bitmask fro the clock registers to define which are valid: #define CLK81_GATE_BASE (0x10000) #define CLK81_GATE(__reg, __bit) (CLK81_GATE_BASE + ((__reg) * 32) + (__bit)) clks: meson-clock-driver@xxx { valid-clk-masks = <...>, <...>, <...>; }; We could even have one sub-node for each 32bit gate clks: meson-clock-driver@xxx { clk81_gate0: { compatible = "meson,meson-gate-reg"; valid-clk-mask = <0x1f1>; } }; Both of these allow easy changing of the bitmask or number of clock gates in the DT. It also means the work is done in one place, and is re-usable by other operating systems. In this case, you could also have a generic clock gate driver which could be define. I'll try and dig out my previous implementation of this which may need a bit of updating. clk81_gate0: clk-gate@regaddr { reg = <regaddr>; compatible = "clock,clock-32git-gate"; valid-clocks = <0x1f1>; clk-parent = <&clk81>; has-single-parent; }; Note, all these could be extended with a clk-names = "a", "b", "c"; and there is already precedent for having a list of valid clock as an array of integers if bitmasks are not acceptable. My side comes down to: 1) We end up with an ID to register mapping which is not clear to see from the DT to the actual register and bit combination being used. 2) If the DT is updated, then we have to update the kernel too if we are using the ID scheme suggested originally. 3) Some of the drivers would provide a generic solution to other SoCs 4) We could even re-use a generic clk-gate driver outside of AMLogic 5) This makes it easier to port to other operating systems as all the data is available in the DT. See also #1 A second note, if we don't want to register n*32 clocks then adding a clk_unused callback called at the end of the initcalls could use the mask/list of clocks to mask out the unused clocks so we don't end up with unused clk structures lying aroudn (could even be a cmdline or kconfig config) -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 6/7] meson: clk: Add support for clock gates 2016-07-06 8:50 ` Ben Dooks @ 2016-07-06 20:36 ` Michael Turquette 0 siblings, 0 replies; 24+ messages in thread From: Michael Turquette @ 2016-07-06 20:36 UTC (permalink / raw) To: Ben Dooks, Alexander Müller, linux-clk, linux-amlogic Quoting Ben Dooks (2016-07-06 01:50:49) > On 06/07/16 09:11, Michael Turquette wrote: > > Quoting Ben Dooks (2016-07-06 00:35:28) > >> On 06/07/16 01:51, Michael Turquette wrote: > >>> Hi Ben, > >>> > >>> Quoting Ben Dooks (2016-07-05 11:01:14) > >>>> On 05/07/16 18:56, Alexander M=C3=BCller wrote: > >>>>> This patch adds support for the meson8b clock gates. Most of > >>>>> them are disabled by Amlogic U-Boot, but need to be enabled > >>>>> for ethernet, USB and many other components. > >>>>> > >>>>> Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com> > >>>>> --- > >>>> > >>>> This seems to be a lot of structures for clocks that may > >>>> never be use. I think it would be better to provide a custom > >>>> lookup function that creates these as needed and use the ID > >>>> in the dt as a offset+bit id. > >>> > >>> We want the real clocks registered so that we can disable spuriously > >>> enabled at late_initcall time with clk_disable_unused. > >>> > >>> Furthermore, I'd like to not represent all of these gates in the DT > >>> binding description (see my response to the earlier patches in this > >>> series), since it becomes ABI (and a maintenance nightmare). > >> > >> Erm, so writing /more/ code and having them defined in /two/ places > >> is a nightmare? Sounds more of a nightmare of having the ID in the DT > >> represent the register/bit offset and then having them created at > >> lookup time. > > = > > I apologize, but I really don't understand what side of the argument > > that you are pushing for based on the above text. Something is a > > nightmare, but I'm not sure which design pattern you are attributing > > nightmare status too. > > = > > Anyways, clock string name is required always, so even if you encode > > register and bitfield in DT cleverly, you've still got data in C, > > assuming your point was to remove stuff from C. That might change some > > day, but not today. Memory footprint should remain the same with either > > implementation. > = > Is that actually useful for anything other than debug? It predates DT adoption by ARM, and we use it internally in the framework to resolve parent-child relationships. We have better possible ways to do this now after 5 years of development, but the legacy drivers will still need this. And so will current drivers, without a replacement mechanism (which I'm working on in my spare time). > = > > If you have an alternative implementation, patches are always welcome. > = > I can think of a few ways we could do this, depending on how much > code is to be added either to the meson-clk driver or to something > that is more generic. > = > If we add gate support to the meson clkock driver, we could have > two implementations, we can either encode the reg/bit into the ID > and have a valid bitmask fro the clock registers to define which > are valid: > = > #define CLK81_GATE_BASE (0x10000) > #define CLK81_GATE(__reg, __bit) (CLK81_GATE_BASE + ((__reg) * 32)= + > (__bit)) > = > clks: meson-clock-driver@xxx { > valid-clk-masks =3D <...>, <...>, <...>; > }; > = > We could even have one sub-node for each 32bit gate > = > = > clks: meson-clock-driver@xxx { > clk81_gate0: { > compatible =3D "meson,meson-gate-reg"; > valid-clk-mask =3D <0x1f1>; > } > }; > = > Both of these allow easy changing of the bitmask or number of clock > gates in the DT. It also means the work is done in one place, and > is re-usable by other operating systems. > = > In this case, you could also have a generic clock gate driver which > could be define. I'll try and dig out my previous implementation of > this which may need a bit of updating. > = > clk81_gate0: clk-gate@regaddr { > reg =3D <regaddr>; > compatible =3D "clock,clock-32git-gate"; > valid-clocks =3D <0x1f1>; > clk-parent =3D <&clk81>; > has-single-parent; > }; Nak. We've worked hard to move away from defining individual clock nodes in DT. We want to express clock controllers as nodes, not individual clock signals. Putting per-clock data into DT is literally the opposite of the direction that we've been trying to go. This kind of stuff always sounds good until you start to have quirks, and then you either need to put Linux-specific flags into DT (bad) or come up with dozens of compatible strings to handle those quirks (not good). Regards, Mike > = > Note, all these could be extended with a clk-names =3D "a", "b", "c"; > and there is already precedent for having a list of valid clock > as an array of integers if bitmasks are not acceptable. > = > My side comes down to: > = > 1) We end up with an ID to register mapping which is not clear to > see from the DT to the actual register and bit combination being > used. > = > 2) If the DT is updated, then we have to update the kernel too if we > are using the ID scheme suggested originally. > = > 3) Some of the drivers would provide a generic solution to other SoCs > = > 4) We could even re-use a generic clk-gate driver outside of AMLogic > = > 5) This makes it easier to port to other operating systems as all the > data is available in the DT. See also #1 > = > A second note, if we don't want to register n*32 clocks then adding > a clk_unused callback called at the end of the initcalls could use > the mask/list of clocks to mask out the unused clocks so we don't > end up with unused clk structures lying aroudn (could even be a > cmdline or kconfig config) > = > -- = > Ben Dooks http://www.codethink.co.uk/ > Senior Engineer Codethink - Providing Genius ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 7/7] arm: amlogic: select meson8b clk driver 2016-07-05 17:56 [PATCH 0/7] Add Amlogic meson8b clock gates Alexander Müller ` (5 preceding siblings ...) 2016-07-05 17:56 ` [PATCH 6/7] meson: clk: Add support for clock gates Alexander Müller @ 2016-07-05 17:56 ` Alexander Müller 2016-07-06 0:54 ` Michael Turquette 6 siblings, 1 reply; 24+ messages in thread From: Alexander Müller @ 2016-07-05 17:56 UTC (permalink / raw) To: mturquette, linux-clk, linux-amlogic Select the Amlogic clk code for meson SoCs and the more specific meson8b clk driver for Amlogic meson8b. Signed-off-by: Alexander Müller <serveralex@gmail.com> --- arch/arm/mach-meson/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 31bdd91..b3add39 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -7,6 +7,7 @@ menuconfig ARCH_MESON select CACHE_L2X0 select PINCTRL select PINCTRL_MESON + select COMMON_CLK_AMLOGIC if ARCH_MESON @@ -24,5 +25,6 @@ config MACH_MESON8B bool "Amlogic Meson8b SoCs support" default ARCH_MESON select MESON6_TIMER + select COMMON_CLK_MESON8B endif -- 2.5.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 7/7] arm: amlogic: select meson8b clk driver 2016-07-05 17:56 ` [PATCH 7/7] arm: amlogic: select meson8b clk driver Alexander Müller @ 2016-07-06 0:54 ` Michael Turquette 2016-07-06 21:41 ` Kevin Hilman 0 siblings, 1 reply; 24+ messages in thread From: Michael Turquette @ 2016-07-06 0:54 UTC (permalink / raw) To: Alexander Müller, linux-clk, linux-amlogic Hi Alex, Quoting Alexander M=C3=BCller (2016-07-05 10:56:31) > Select the Amlogic clk code for meson SoCs and the more specific meson8b = clk > driver for Amlogic meson8b. > = > Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com> This patch isn't necessary as an alternative is already queued. See: https://git.kernel.org/cgit/linux/kernel/git/mturquette/linux.git/commit/?h= =3Dgxbb-dt-clk&id=3Dbae5d70ba6f8726ea6306aa07b7d2eb4357d3c81 However, if you're basing on top of clk-next (or clk-s905) then you won't see the three patches linked above because they are queued through Kevin & Carlo via the amlogic tree. Regards, Mike > --- > arch/arm/mach-meson/Kconfig | 2 ++ > 1 file changed, 2 insertions(+) > = > diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig > index 31bdd91..b3add39 100644 > --- a/arch/arm/mach-meson/Kconfig > +++ b/arch/arm/mach-meson/Kconfig > @@ -7,6 +7,7 @@ menuconfig ARCH_MESON > select CACHE_L2X0 > select PINCTRL > select PINCTRL_MESON > + select COMMON_CLK_AMLOGIC > = > if ARCH_MESON > = > @@ -24,5 +25,6 @@ config MACH_MESON8B > bool "Amlogic Meson8b SoCs support" > default ARCH_MESON > select MESON6_TIMER > + select COMMON_CLK_MESON8B > = > endif > -- = > 2.5.0 >=20 ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 7/7] arm: amlogic: select meson8b clk driver 2016-07-06 0:54 ` Michael Turquette @ 2016-07-06 21:41 ` Kevin Hilman 2016-07-13 17:53 ` Alexander Müller 0 siblings, 1 reply; 24+ messages in thread From: Kevin Hilman @ 2016-07-06 21:41 UTC (permalink / raw) To: Michael Turquette; +Cc: Alexander Müller, linux-clk, linux-amlogic Michael Turquette <mturquette@baylibre.com> writes: > Hi Alex, > > Quoting Alexander M=C3=BCller (2016-07-05 10:56:31) >> Select the Amlogic clk code for meson SoCs and the more specific meson8b= clk >> driver for Amlogic meson8b. >>=20 >> Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com> > > This patch isn't necessary as an alternative is already queued. See: > https://git.kernel.org/cgit/linux/kernel/git/mturquette/linux.git/commit/= ?h=3Dgxbb-dt-clk&id=3Dbae5d70ba6f8726ea6306aa07b7d2eb4357d3c81 > > However, if you're basing on top of clk-next (or clk-s905) then you > won't see the three patches linked above because they are queued through > Kevin & Carlo via the amlogic tree. ...which you can find here[1] and specifically, the "integ" branch where I'm keeping the latest queued versions of various things merged together for easier testing. Kevin [1] https://git.kernel.org/cgit/linux/kernel/git/khilman/linux-amlogic.git/ ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 7/7] arm: amlogic: select meson8b clk driver 2016-07-06 21:41 ` Kevin Hilman @ 2016-07-13 17:53 ` Alexander Müller 0 siblings, 0 replies; 24+ messages in thread From: Alexander Müller @ 2016-07-13 17:53 UTC (permalink / raw) To: Kevin Hilman; +Cc: Michael Turquette, linux-clk, linux-amlogic Hi Kevin,=20 I did the proposed changes and rebased to integ.=20 Please review and let me know if I missed something. Alex > On 06 Jul 2016, at 23:41, Kevin Hilman <khilman@baylibre.com> wrote: >=20 > Michael Turquette <mturquette@baylibre.com> writes: >=20 >> Hi Alex, >>=20 >> Quoting Alexander M=C3=BCller (2016-07-05 10:56:31) >>> Select the Amlogic clk code for meson SoCs and the more specific = meson8b clk >>> driver for Amlogic meson8b. >>>=20 >>> Signed-off-by: Alexander M=C3=BCller <serveralex@gmail.com> >>=20 >> This patch isn't necessary as an alternative is already queued. See: >> = https://git.kernel.org/cgit/linux/kernel/git/mturquette/linux.git/commit/?= h=3Dgxbb-dt-clk&id=3Dbae5d70ba6f8726ea6306aa07b7d2eb4357d3c81 >>=20 >> However, if you're basing on top of clk-next (or clk-s905) then you >> won't see the three patches linked above because they are queued = through >> Kevin & Carlo via the amlogic tree. >=20 > ...which you can find here[1] and specifically, the "integ" branch = where > I'm keeping the latest queued versions of various things merged = together > for easier testing. >=20 > Kevin >=20 > [1] = https://git.kernel.org/cgit/linux/kernel/git/khilman/linux-amlogic.git/ ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2016-07-13 21:25 UTC | newest] Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-07-05 17:56 [PATCH 0/7] Add Amlogic meson8b clock gates Alexander Müller 2016-07-05 17:56 ` [PATCH 1/7] clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention Alexander Müller 2016-07-05 18:55 ` Carlo Caione 2016-07-05 19:15 ` Alexander Müller 2016-07-05 17:56 ` [PATCH 2/7] meson: clk: Move register definitions to meson8b.h Alexander Müller 2016-07-05 17:56 ` [PATCH 3/7] meson: clk: Rename register names according to Amlogic datasheet Alexander Müller 2016-07-06 0:28 ` Michael Turquette 2016-07-05 17:56 ` [PATCH 4/7] meson: clk: Add CLKIDs for DT binding Alexander Müller 2016-07-06 0:33 ` Michael Turquette 2016-07-05 17:56 ` [PATCH 5/7] gxbb: clk: Move MESON_GATE macro to gxbb Alexander Müller 2016-07-06 0:36 ` Michael Turquette 2016-07-13 17:43 ` Alexander Müller 2016-07-13 21:25 ` Michael Turquette 2016-07-05 17:56 ` [PATCH 6/7] meson: clk: Add support for clock gates Alexander Müller 2016-07-05 18:01 ` Ben Dooks 2016-07-06 0:51 ` Michael Turquette 2016-07-06 7:35 ` Ben Dooks 2016-07-06 8:11 ` Michael Turquette 2016-07-06 8:50 ` Ben Dooks 2016-07-06 20:36 ` Michael Turquette 2016-07-05 17:56 ` [PATCH 7/7] arm: amlogic: select meson8b clk driver Alexander Müller 2016-07-06 0:54 ` Michael Turquette 2016-07-06 21:41 ` Kevin Hilman 2016-07-13 17:53 ` Alexander Müller
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