* [PATCH V9 0/7] clk: imx: add imx8qxp clock support
@ 2018-12-04 14:39 Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 1/7] clk: imx: add configuration option for mmio clks Aisheng DONG
` (7 more replies)
0 siblings, 8 replies; 22+ messages in thread
From: Aisheng DONG @ 2018-12-04 14:39 UTC (permalink / raw)
To: linux-clk
Cc: linux-arm-kernel, sboyd, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel, Aisheng DONG
This patch series adds i.MX8QXP clock support which is based
on the clock service provided by SCU firmware.
Note: It depends on SCU driver which has already been merged by Shawn.
So this patch series could go through Shawn's tree as well.
ChangeLog:
v8->v9:
* add __le32 and __le16 for SCU message structure members as it's little endian
* use readl_relaxed() as it does not need insert barrier
* a small code logic improvement suggested by Stephen
v7->v8:
* add more kernel doc for lpcg and scu clock structures
* remove one unneccessry reg checking
v6->v7:
* use struct_size()
* remove MODULE_ macros
* add more kernel docs/code comments
* other small improvements
* update reviewed-by tags
* add the missing PATCH 1 in V6
v5->v6:
* simply the driver a lot by re-orgnizing the driver into a few clock types:
scu clock (merge scu divider/gate/mux) and scu gpr lock which accessing is
through SCU protocol and LPCG clock which is directly accessible by CPU.
* LPCG clock is separate from SCU clock, gpr clock is still not used
and will be added later.
* remove old year license as the code is totally rewritten
* scu mux support will be added later as it's also still not used.
v4->v5:
Address all Stephen and Sascha's review comments, see details in each patch
v3->v4:
* scu headfile path update
* no functionality change
v2->v3:
* structures/enums name update with imx_sc prefix
* no functionality change
v1->v2:
* structure and enums name update
* api usage update due to api change
* no functionality change
Dong Aisheng (7):
clk: imx: add configuration option for mmio clks
clk: imx: add scu clock common part
dt-bindings: clock: imx8qxp: add SCU clock IDs
clk: imx: add imx8qxp clk driver
dt-bindings: clock: add imx8qxp lpcg clock binding
clk: imx: add lpcg clock support
clk: imx: add imx8qxp lpcg driver
.../devicetree/bindings/clock/imx8qxp-lpcg.txt | 51 ++++
arch/arm/mach-imx/Kconfig | 11 +
drivers/clk/Kconfig | 1 +
drivers/clk/imx/Kconfig | 9 +
drivers/clk/imx/Makefile | 8 +-
drivers/clk/imx/clk-imx8qxp-lpcg.c | 216 +++++++++++++++
drivers/clk/imx/clk-imx8qxp-lpcg.h | 102 ++++++++
drivers/clk/imx/clk-imx8qxp.c | 153 +++++++++++
drivers/clk/imx/clk-lpcg-scu.c | 114 ++++++++
drivers/clk/imx/clk-scu.c | 265 +++++++++++++++++++
drivers/clk/imx/clk-scu.h | 24 ++
include/dt-bindings/clock/imx8qxp-clock.h | 289 +++++++++++++++++++++
12 files changed, 1242 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
create mode 100644 drivers/clk/imx/Kconfig
create mode 100644 drivers/clk/imx/clk-imx8qxp-lpcg.c
create mode 100644 drivers/clk/imx/clk-imx8qxp-lpcg.h
create mode 100644 drivers/clk/imx/clk-imx8qxp.c
create mode 100644 drivers/clk/imx/clk-lpcg-scu.c
create mode 100644 drivers/clk/imx/clk-scu.c
create mode 100644 drivers/clk/imx/clk-scu.h
create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h
--
2.7.4
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V9 1/7] clk: imx: add configuration option for mmio clks
2018-12-04 14:39 [PATCH V9 0/7] clk: imx: add imx8qxp clock support Aisheng DONG
@ 2018-12-04 14:39 ` Aisheng DONG
2018-12-10 20:55 ` Stephen Boyd
2018-12-04 14:39 ` [PATCH V9 2/7] clk: imx: add scu clock common part Aisheng DONG
` (6 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Aisheng DONG @ 2018-12-04 14:39 UTC (permalink / raw)
To: linux-clk
Cc: linux-arm-kernel, sboyd, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel, Aisheng DONG
The patch introduces CONFIG_MXC_CLK option for legacy MMIO clocks,
this is required to compile legacy MMIO clock conditionally when adding
SCU based clocks for MX8 platforms later.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
arch/arm/mach-imx/Kconfig | 11 +++++++++++
drivers/clk/Kconfig | 1 +
drivers/clk/imx/Kconfig | 5 +++++
drivers/clk/imx/Makefile | 2 +-
4 files changed, 18 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/imx/Kconfig
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c12a05c..303082c 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -57,23 +57,27 @@ config SOC_IMX21
select CPU_ARM926T
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
+ select MXC_CLK
config SOC_IMX27
bool
select CPU_ARM926T
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
+ select MXC_CLK
select PINCTRL_IMX27
config SOC_IMX31
bool
select CPU_V6
select MXC_AVIC
+ select MXC_CLK
config SOC_IMX35
bool
select ARCH_MXC_IOMUX_V3
select MXC_AVIC
+ select MXC_CLK
select PINCTRL_IMX35
if ARCH_MULTI_V5
@@ -417,6 +421,7 @@ config SOC_IMX1
bool "i.MX1 support"
select CPU_ARM920T
select MXC_AVIC
+ select MXC_CLK
select PINCTRL_IMX1
help
This enables support for Freescale i.MX1 processor
@@ -430,6 +435,7 @@ config SOC_IMX25
select ARCH_MXC_IOMUX_V3
select CPU_ARM926T
select MXC_AVIC
+ select MXC_CLK
select PINCTRL_IMX25
help
This enables support for Freescale i.MX25 processor
@@ -442,6 +448,7 @@ comment "Cortex-A platforms"
config SOC_IMX5
bool
select HAVE_IMX_SRC
+ select MXC_CLK
select MXC_TZIC
config SOC_IMX50
@@ -478,6 +485,7 @@ config SOC_IMX6
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select MFD_SYSCON
+ select MXC_CLK
select PL310_ERRATA_769419 if CACHE_L2X0
config SOC_IMX6Q
@@ -545,10 +553,12 @@ config SOC_IMX7D_CA7
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select IMX_GPCV2
+ select MXC_CLK
config SOC_IMX7D_CM4
bool
select ARMV7M_SYSTICK
+ select MXC_CLK
config SOC_IMX7D
bool "i.MX7 Dual support"
@@ -570,6 +580,7 @@ config SOC_IMX7ULP
config SOC_VF610
bool "Vybrid Family VF610 support"
select ARM_GIC if ARCH_MULTI_V7
+ select MXC_CLK
select PINCTRL_VF610
help
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 81cdb4e..1dbfcc2 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -287,6 +287,7 @@ source "drivers/clk/actions/Kconfig"
source "drivers/clk/bcm/Kconfig"
source "drivers/clk/hisilicon/Kconfig"
source "drivers/clk/imgtec/Kconfig"
+source "drivers/clk/imx/Kconfig"
source "drivers/clk/ingenic/Kconfig"
source "drivers/clk/keystone/Kconfig"
source "drivers/clk/mediatek/Kconfig"
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
new file mode 100644
index 0000000..43a3ecc
--- /dev/null
+++ b/drivers/clk/imx/Kconfig
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+# common clock support for NXP i.MX SoC family.
+config MXC_CLK
+ bool
+ depends on ARCH_MXC
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 5c0b11e..f850424 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
-obj-y += \
+obj-$(CONFIG_MXC_CLK) += \
clk.o \
clk-busy.o \
clk-composite-8m.o \
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V9 2/7] clk: imx: add scu clock common part
2018-12-04 14:39 [PATCH V9 0/7] clk: imx: add imx8qxp clock support Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 1/7] clk: imx: add configuration option for mmio clks Aisheng DONG
@ 2018-12-04 14:39 ` Aisheng DONG
2018-12-10 21:56 ` Stephen Boyd
2018-12-04 14:39 ` [PATCH V9 3/7] dt-bindings: clock: imx8qxp: add SCU clock IDs Aisheng DONG
` (5 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Aisheng DONG @ 2018-12-04 14:39 UTC (permalink / raw)
To: linux-clk
Cc: linux-arm-kernel, sboyd, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel, Aisheng DONG
Add SCU clock common part which will be used by client clock drivers.
SCU clocks are totally different from the legacy clocks (No much
legacy things can be reused), it's using a firmware interface now based
on SCU protocol. So a new configuration option CONFIG_MXC_CLK_SCU is added.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/clk/imx/Kconfig | 4 +
drivers/clk/imx/Makefile | 3 +
drivers/clk/imx/clk-scu.c | 265 ++++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk-scu.h | 21 ++++
4 files changed, 293 insertions(+)
create mode 100644 drivers/clk/imx/clk-scu.c
create mode 100644 drivers/clk/imx/clk-scu.h
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 43a3ecc..63e7b01 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -3,3 +3,7 @@
config MXC_CLK
bool
depends on ARCH_MXC
+
+config MXC_CLK_SCU
+ bool
+ depends on ARCH_MXC && ARM64
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index f850424..4abed37 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -20,6 +20,9 @@ obj-$(CONFIG_MXC_CLK) += \
clk-pllv4.o \
clk-sccg-pll.o
+obj-$(CONFIG_MXC_CLK_SCU) += \
+ clk-scu.o
+
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
obj-$(CONFIG_SOC_IMX25) += clk-imx25.o
diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
new file mode 100644
index 0000000..ec8a471
--- /dev/null
+++ b/drivers/clk/imx/clk-scu.c
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include "clk-scu.h"
+
+struct imx_sc_ipc *ccm_ipc_handle;
+
+/*
+ * struct clk_scu - Description of one SCU clock
+ * @hw: the common clk_hw
+ * @rsrc_id: resource ID of this SCU clock
+ * @clk_type: type of this clock resource
+ */
+struct clk_scu {
+ struct clk_hw hw;
+ u16 rsrc_id;
+ u8 clk_type;
+};
+
+/*
+ * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
+ * @hdr: SCU protocol header
+ * @rate: rate to set
+ * @resource: clock resource to set rate
+ * @clk: clk type of this resource
+ *
+ * This structure describes the SCU protocol of clock rate set
+ */
+struct imx_sc_msg_req_set_clock_rate {
+ struct imx_sc_rpc_msg hdr;
+ __le32 rate;
+ __le16 resource;
+ u8 clk;
+} __packed;
+
+struct req_get_clock_rate {
+ __le16 resource;
+ u8 clk;
+} __packed;
+
+struct resp_get_clock_rate {
+ __le32 rate;
+};
+
+/*
+ * struct imx_sc_msg_get_clock_rate - clock get rate protocol
+ * @hdr: SCU protocol header
+ * @req: get rate request protocol
+ * @resp: get rate response protocol
+ *
+ * This structure describes the SCU protocol of clock rate get
+ */
+struct imx_sc_msg_get_clock_rate {
+ struct imx_sc_rpc_msg hdr;
+ union {
+ struct req_get_clock_rate req;
+ struct resp_get_clock_rate resp;
+ } data;
+};
+
+/*
+ * struct imx_sc_msg_req_clock_enable - clock gate protocol
+ * @hdr: SCU protocol header
+ * @resource: clock resource to gate
+ * @clk: clk type of this resource
+ * @enable: whether gate off the clock
+ * @autog: HW auto gate enable
+ *
+ * This structure describes the SCU protocol of clock gate
+ */
+struct imx_sc_msg_req_clock_enable {
+ struct imx_sc_rpc_msg hdr;
+ __le16 resource;
+ u8 clk;
+ u8 enable;
+ u8 autog;
+} __packed;
+
+static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
+{
+ return container_of(hw, struct clk_scu, hw);
+}
+
+/*
+ * clk_scu_recalc_rate - Get clock rate for a SCU clock
+ * @hw: clock to get rate for
+ * @parent_rate: parent rate provided by common clock framework, not used
+ *
+ * Gets the current clock rate of a SCU clock. Returns the current
+ * clock rate, or zero in failure.
+ */
+static unsigned long clk_scu_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_scu *clk = to_clk_scu(hw);
+ struct imx_sc_msg_get_clock_rate msg;
+ struct imx_sc_rpc_msg *hdr = &msg.hdr;
+ int ret;
+
+ hdr->ver = IMX_SC_RPC_VERSION;
+ hdr->svc = IMX_SC_RPC_SVC_PM;
+ hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_RATE;
+ hdr->size = 2;
+
+ msg.data.req.resource = cpu_to_le16(clk->rsrc_id);
+ msg.data.req.clk = clk->clk_type;
+
+ ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
+ if (ret) {
+ pr_err("%s: failed to get clock rate %d\n",
+ clk_hw_get_name(hw), ret);
+ return 0;
+ }
+
+ return le32_to_cpu(msg.data.resp.rate);
+}
+
+/*
+ * clk_scu_round_rate - Round clock rate for a SCU clock
+ * @hw: clock to round rate for
+ * @rate: rate to round
+ * @parent_rate: parent rate provided by common clock framework, not used
+ *
+ * Returns the current clock rate, or zero in failure.
+ */
+static long clk_scu_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ /*
+ * Assume we support all the requested rate and let the SCU firmware
+ * to handle the left work
+ */
+ return rate;
+}
+
+/*
+ * clk_scu_set_rate - Set rate for a SCU clock
+ * @hw: clock to change rate for
+ * @rate: target rate for the clock
+ * @parent_rate: rate of the clock parent, not used for SCU clocks
+ *
+ * Sets a clock frequency for a SCU clock. Returns the SCU
+ * protocol status.
+ */
+static int clk_scu_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_scu *clk = to_clk_scu(hw);
+ struct imx_sc_msg_req_set_clock_rate msg;
+ struct imx_sc_rpc_msg *hdr = &msg.hdr;
+
+ hdr->ver = IMX_SC_RPC_VERSION;
+ hdr->svc = IMX_SC_RPC_SVC_PM;
+ hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_RATE;
+ hdr->size = 3;
+
+ msg.rate = cpu_to_le32(rate);
+ msg.resource = cpu_to_le16(clk->rsrc_id);
+ msg.clk = clk->clk_type;
+
+ return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
+}
+
+static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource,
+ u8 clk, bool enable, bool autog)
+{
+ struct imx_sc_msg_req_clock_enable msg;
+ struct imx_sc_rpc_msg *hdr = &msg.hdr;
+
+ hdr->ver = IMX_SC_RPC_VERSION;
+ hdr->svc = IMX_SC_RPC_SVC_PM;
+ hdr->func = IMX_SC_PM_FUNC_CLOCK_ENABLE;
+ hdr->size = 3;
+
+ msg.resource = cpu_to_le16(resource);
+ msg.clk = clk;
+ msg.enable = enable;
+ msg.autog = autog;
+
+ return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
+}
+
+/*
+ * clk_scu_prepare - Enable a SCU clock
+ * @hw: clock to enable
+ *
+ * Enable the clock at the DSC slice level
+ */
+static int clk_scu_prepare(struct clk_hw *hw)
+{
+ struct clk_scu *clk = to_clk_scu(hw);
+
+ return sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,
+ clk->clk_type, true, false);
+}
+
+/*
+ * clk_scu_unprepare - Disable a SCU clock
+ * @hw: clock to enable
+ *
+ * Disable the clock at the DSC slice level
+ */
+static void clk_scu_unprepare(struct clk_hw *hw)
+{
+ struct clk_scu *clk = to_clk_scu(hw);
+ int ret;
+
+ ret = sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,
+ clk->clk_type, false, false);
+ if (ret)
+ pr_warn("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
+ ret);
+}
+
+static const struct clk_ops clk_scu_ops = {
+ .recalc_rate = clk_scu_recalc_rate,
+ .round_rate = clk_scu_round_rate,
+ .set_rate = clk_scu_set_rate,
+ .prepare = clk_scu_prepare,
+ .unprepare = clk_scu_unprepare,
+};
+
+struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id, u8 clk_type)
+{
+ struct clk_init_data init;
+ struct clk_scu *clk;
+ struct clk_hw *hw;
+ int ret;
+
+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+ if (!clk)
+ return ERR_PTR(-ENOMEM);
+
+ clk->rsrc_id = rsrc_id;
+ clk->clk_type = clk_type;
+
+ init.name = name;
+ init.ops = &clk_scu_ops;
+ init.num_parents = 0;
+ /*
+ * Note on MX8, the clocks are tightly coupled with power domain
+ * that once the power domain is off, the clock status may be
+ * lost. So we make it NOCACHE to let user to retrieve the real
+ * clock status from HW instead of using the possible invalid
+ * cached rate.
+ */
+ init.flags = CLK_GET_RATE_NOCACHE;
+ clk->hw.init = &init;
+
+ hw = &clk->hw;
+ ret = clk_hw_register(NULL, hw);
+ if (ret) {
+ kfree(clk);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
new file mode 100644
index 0000000..09f381b
--- /dev/null
+++ b/drivers/clk/imx/clk-scu.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#ifndef __IMX_CLK_SCU_H
+#define __IMX_CLK_SCU_H
+
+#include <linux/firmware/imx/sci.h>
+
+extern struct imx_sc_ipc *ccm_ipc_handle;
+
+static inline int imx_clk_scu_init(void)
+{
+ return imx_scu_get_handle(&ccm_ipc_handle);
+}
+
+struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id, u8 clk_type);
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V9 3/7] dt-bindings: clock: imx8qxp: add SCU clock IDs
2018-12-04 14:39 [PATCH V9 0/7] clk: imx: add imx8qxp clock support Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 1/7] clk: imx: add configuration option for mmio clks Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 2/7] clk: imx: add scu clock common part Aisheng DONG
@ 2018-12-04 14:39 ` Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 4/7] clk: imx: add imx8qxp clk driver Aisheng DONG
` (4 subsequent siblings)
7 siblings, 0 replies; 22+ messages in thread
From: Aisheng DONG @ 2018-12-04 14:39 UTC (permalink / raw)
To: linux-clk
Cc: linux-arm-kernel, sboyd, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel, Aisheng DONG, devicetree
Add IMX8QXP SCU clock IDs.
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
include/dt-bindings/clock/imx8qxp-clock.h | 136 ++++++++++++++++++++++++++++++
1 file changed, 136 insertions(+)
create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h
diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h
new file mode 100644
index 0000000..d72a39c
--- /dev/null
+++ b/include/dt-bindings/clock/imx8qxp-clock.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H
+#define __DT_BINDINGS_CLOCK_IMX8QXP_H
+
+/* SCU Clocks */
+
+#define IMX8QXP_CLK_DUMMY 0
+
+/* CPU */
+#define IMX8QXP_A35_CLK 1
+
+/* LSIO SS */
+#define IMX8QXP_LSIO_MEM_CLK 2
+#define IMX8QXP_LSIO_BUS_CLK 3
+#define IMX8QXP_LSIO_PWM0_CLK 10
+#define IMX8QXP_LSIO_PWM1_CLK 11
+#define IMX8QXP_LSIO_PWM2_CLK 12
+#define IMX8QXP_LSIO_PWM3_CLK 13
+#define IMX8QXP_LSIO_PWM4_CLK 14
+#define IMX8QXP_LSIO_PWM5_CLK 15
+#define IMX8QXP_LSIO_PWM6_CLK 16
+#define IMX8QXP_LSIO_PWM7_CLK 17
+#define IMX8QXP_LSIO_GPT0_CLK 18
+#define IMX8QXP_LSIO_GPT1_CLK 19
+#define IMX8QXP_LSIO_GPT2_CLK 20
+#define IMX8QXP_LSIO_GPT3_CLK 21
+#define IMX8QXP_LSIO_GPT4_CLK 22
+#define IMX8QXP_LSIO_FSPI0_CLK 23
+#define IMX8QXP_LSIO_FSPI1_CLK 24
+
+/* Connectivity SS */
+#define IMX8QXP_CONN_AXI_CLK_ROOT 30
+#define IMX8QXP_CONN_AHB_CLK_ROOT 31
+#define IMX8QXP_CONN_IPG_CLK_ROOT 32
+#define IMX8QXP_CONN_SDHC0_CLK 40
+#define IMX8QXP_CONN_SDHC1_CLK 41
+#define IMX8QXP_CONN_SDHC2_CLK 42
+#define IMX8QXP_CONN_ENET0_ROOT_CLK 43
+#define IMX8QXP_CONN_ENET0_BYPASS_CLK 44
+#define IMX8QXP_CONN_ENET0_RGMII_CLK 45
+#define IMX8QXP_CONN_ENET1_ROOT_CLK 46
+#define IMX8QXP_CONN_ENET1_BYPASS_CLK 47
+#define IMX8QXP_CONN_ENET1_RGMII_CLK 48
+#define IMX8QXP_CONN_GPMI_BCH_IO_CLK 49
+#define IMX8QXP_CONN_GPMI_BCH_CLK 50
+#define IMX8QXP_CONN_USB2_ACLK 51
+#define IMX8QXP_CONN_USB2_BUS_CLK 52
+#define IMX8QXP_CONN_USB2_LPM_CLK 53
+
+/* HSIO SS */
+#define IMX8QXP_HSIO_AXI_CLK 60
+#define IMX8QXP_HSIO_PER_CLK 61
+
+/* Display controller SS */
+#define IMX8QXP_DC_AXI_EXT_CLK 70
+#define IMX8QXP_DC_AXI_INT_CLK 71
+#define IMX8QXP_DC_CFG_CLK 72
+#define IMX8QXP_DC0_PLL0_CLK 80
+#define IMX8QXP_DC0_PLL1_CLK 81
+#define IMX8QXP_DC0_DISP0_CLK 82
+#define IMX8QXP_DC0_DISP1_CLK 83
+
+/* MIPI-LVDS SS */
+#define IMX8QXP_MIPI_IPG_CLK 90
+#define IMX8QXP_MIPI0_PIXEL_CLK 100
+#define IMX8QXP_MIPI0_BYPASS_CLK 101
+#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK 102
+#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK 103
+#define IMX8QXP_MIPI0_LVDS_PHY_CLK 104
+#define IMX8QXP_MIPI0_I2C0_CLK 105
+#define IMX8QXP_MIPI0_I2C1_CLK 106
+#define IMX8QXP_MIPI0_PWM0_CLK 107
+#define IMX8QXP_MIPI1_PIXEL_CLK 108
+#define IMX8QXP_MIPI1_BYPASS_CLK 109
+#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK 110
+#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK 111
+#define IMX8QXP_MIPI1_LVDS_PHY_CLK 112
+#define IMX8QXP_MIPI1_I2C0_CLK 113
+#define IMX8QXP_MIPI1_I2C1_CLK 114
+#define IMX8QXP_MIPI1_PWM0_CLK 115
+
+/* IMG SS */
+#define IMX8QXP_IMG_AXI_CLK 120
+#define IMX8QXP_IMG_IPG_CLK 121
+#define IMX8QXP_IMG_PXL_CLK 122
+
+/* MIPI-CSI SS */
+#define IMX8QXP_CSI0_CORE_CLK 130
+#define IMX8QXP_CSI0_ESC_CLK 131
+#define IMX8QXP_CSI0_PWM0_CLK 132
+#define IMX8QXP_CSI0_I2C0_CLK 133
+
+/* PARALLER CSI SS */
+#define IMX8QXP_PARALLEL_CSI_DPLL_CLK 140
+#define IMX8QXP_PARALLEL_CSI_PIXEL_CLK 141
+#define IMX8QXP_PARALLEL_CSI_MCLK_CLK 142
+
+/* VPU SS */
+#define IMX8QXP_VPU_ENC_CLK 150
+#define IMX8QXP_VPU_DEC_CLK 151
+
+/* GPU SS */
+#define IMX8QXP_GPU0_CORE_CLK 160
+#define IMX8QXP_GPU0_SHADER_CLK 161
+
+/* ADMA SS */
+#define IMX8QXP_ADMA_IPG_CLK_ROOT 165
+#define IMX8QXP_ADMA_UART0_CLK 170
+#define IMX8QXP_ADMA_UART1_CLK 171
+#define IMX8QXP_ADMA_UART2_CLK 172
+#define IMX8QXP_ADMA_UART3_CLK 173
+#define IMX8QXP_ADMA_SPI0_CLK 174
+#define IMX8QXP_ADMA_SPI1_CLK 175
+#define IMX8QXP_ADMA_SPI2_CLK 176
+#define IMX8QXP_ADMA_SPI3_CLK 177
+#define IMX8QXP_ADMA_CAN0_CLK 178
+#define IMX8QXP_ADMA_CAN1_CLK 179
+#define IMX8QXP_ADMA_CAN2_CLK 180
+#define IMX8QXP_ADMA_I2C0_CLK 181
+#define IMX8QXP_ADMA_I2C1_CLK 182
+#define IMX8QXP_ADMA_I2C2_CLK 183
+#define IMX8QXP_ADMA_I2C3_CLK 184
+#define IMX8QXP_ADMA_FTM0_CLK 185
+#define IMX8QXP_ADMA_FTM1_CLK 186
+#define IMX8QXP_ADMA_ADC0_CLK 187
+#define IMX8QXP_ADMA_PWM_CLK 188
+#define IMX8QXP_ADMA_LCD_CLK 189
+
+#define IMX8QXP_SCU_CLK_END 190
+
+#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V9 4/7] clk: imx: add imx8qxp clk driver
2018-12-04 14:39 [PATCH V9 0/7] clk: imx: add imx8qxp clock support Aisheng DONG
` (2 preceding siblings ...)
2018-12-04 14:39 ` [PATCH V9 3/7] dt-bindings: clock: imx8qxp: add SCU clock IDs Aisheng DONG
@ 2018-12-04 14:39 ` Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 5/7] dt-bindings: clock: add imx8qxp lpcg clock binding Aisheng DONG
` (3 subsequent siblings)
7 siblings, 0 replies; 22+ messages in thread
From: Aisheng DONG @ 2018-12-04 14:39 UTC (permalink / raw)
To: linux-clk
Cc: linux-arm-kernel, sboyd, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel, Aisheng DONG
Add imx8qxp clk driver which is based on SCU firmware clock service.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/clk/imx/Makefile | 2 +
drivers/clk/imx/clk-imx8qxp.c | 153 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 155 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8qxp.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 4abed37..75312fb 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -39,3 +39,5 @@ obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
obj-$(CONFIG_SOC_IMX7ULP) += clk-imx7ulp.o
obj-$(CONFIG_SOC_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o
+
+obj-$(CONFIG_SOC_IMX8QXP) += clk-imx8qxp.o
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
new file mode 100644
index 0000000..a957704
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk-scu.h"
+
+#include <dt-bindings/clock/imx8qxp-clock.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+static int imx8qxp_clk_probe(struct platform_device *pdev)
+{
+ struct device_node *ccm_node = pdev->dev.of_node;
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_hw **clks;
+ int ret, i;
+
+ ret = imx_clk_scu_init();
+ if (ret)
+ return ret;
+
+ clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
+ IMX8QXP_SCU_CLK_END), GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
+ clk_data->num = IMX8QXP_SCU_CLK_END;
+ clks = clk_data->hws;
+
+ /* Fixed clocks */
+ clks[IMX8QXP_CLK_DUMMY] = clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
+ clks[IMX8QXP_ADMA_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "dma_ipg_clk_root", NULL, 0, 120000000);
+ clks[IMX8QXP_CONN_AXI_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_axi_clk_root", NULL, 0, 333333333);
+ clks[IMX8QXP_CONN_AHB_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ahb_clk_root", NULL, 0, 166666666);
+ clks[IMX8QXP_CONN_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ipg_clk_root", NULL, 0, 83333333);
+ clks[IMX8QXP_DC_AXI_EXT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_ext_clk_root", NULL, 0, 800000000);
+ clks[IMX8QXP_DC_AXI_INT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_int_clk_root", NULL, 0, 400000000);
+ clks[IMX8QXP_DC_CFG_CLK] = clk_hw_register_fixed_rate(NULL, "dc_cfg_clk_root", NULL, 0, 100000000);
+ clks[IMX8QXP_MIPI_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "mipi_ipg_clk_root", NULL, 0, 120000000);
+ clks[IMX8QXP_IMG_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "img_axi_clk_root", NULL, 0, 400000000);
+ clks[IMX8QXP_IMG_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "img_ipg_clk_root", NULL, 0, 200000000);
+ clks[IMX8QXP_IMG_PXL_CLK] = clk_hw_register_fixed_rate(NULL, "img_pxl_clk_root", NULL, 0, 600000000);
+ clks[IMX8QXP_HSIO_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_axi_clk_root", NULL, 0, 400000000);
+ clks[IMX8QXP_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
+ clks[IMX8QXP_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 100000000);
+ clks[IMX8QXP_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 200000000);
+
+ /* ARM core */
+ clks[IMX8QXP_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
+
+ /* LSIO SS */
+ clks[IMX8QXP_LSIO_PWM0_CLK] = imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_PWM1_CLK] = imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_PWM2_CLK] = imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_PWM3_CLK] = imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_PWM4_CLK] = imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_PWM5_CLK] = imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_PWM6_CLK] = imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_PWM7_CLK] = imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_GPT0_CLK] = imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_GPT1_CLK] = imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_GPT2_CLK] = imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_GPT3_CLK] = imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_GPT4_CLK] = imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_FSPI0_CLK] = imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_LSIO_FSPI1_CLK] = imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER);
+
+ /* ADMA SS */
+ clks[IMX8QXP_ADMA_UART0_CLK] = imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_UART1_CLK] = imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_UART2_CLK] = imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_UART3_CLK] = imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_SPI0_CLK] = imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_SPI1_CLK] = imx_clk_scu("spi1_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_SPI2_CLK] = imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_SPI3_CLK] = imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_CAN0_CLK] = imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_I2C0_CLK] = imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_I2C1_CLK] = imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_I2C2_CLK] = imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_I2C3_CLK] = imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_FTM0_CLK] = imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_FTM1_CLK] = imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_ADC0_CLK] = imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_PWM_CLK] = imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_ADMA_LCD_CLK] = imx_clk_scu("lcd_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER);
+
+ /* Connectivity */
+ clks[IMX8QXP_CONN_SDHC0_CLK] = imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_CONN_SDHC1_CLK] = imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_CONN_SDHC2_CLK] = imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_CONN_ENET0_ROOT_CLK] = imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_CONN_ENET0_BYPASS_CLK] = imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
+ clks[IMX8QXP_CONN_ENET0_RGMII_CLK] = imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
+ clks[IMX8QXP_CONN_ENET1_ROOT_CLK] = imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_CONN_ENET1_BYPASS_CLK] = imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
+ clks[IMX8QXP_CONN_ENET1_RGMII_CLK] = imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
+ clks[IMX8QXP_CONN_GPMI_BCH_IO_CLK] = imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
+ clks[IMX8QXP_CONN_GPMI_BCH_CLK] = imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_CONN_USB2_ACLK] = imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_CONN_USB2_BUS_CLK] = imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS);
+ clks[IMX8QXP_CONN_USB2_LPM_CLK] = imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC);
+
+ /* Display controller SS */
+ clks[IMX8QXP_DC0_DISP0_CLK] = imx_clk_scu("dc0_disp0_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0);
+ clks[IMX8QXP_DC0_DISP1_CLK] = imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1);
+
+ /* MIPI-LVDS SS */
+ clks[IMX8QXP_MIPI0_I2C0_CLK] = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2);
+ clks[IMX8QXP_MIPI0_I2C1_CLK] = imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2);
+
+ /* MIPI CSI SS */
+ clks[IMX8QXP_CSI0_CORE_CLK] = imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_CSI0_ESC_CLK] = imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC);
+ clks[IMX8QXP_CSI0_I2C0_CLK] = imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_CSI0_PWM0_CLK] = imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER);
+
+ /* GPU SS */
+ clks[IMX8QXP_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
+ clks[IMX8QXP_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
+
+ for (i = 0; i < clk_data->num; i++) {
+ if (IS_ERR(clks[i]))
+ pr_warn("i.MX clk %u: register failed with %ld\n",
+ i, PTR_ERR(clks[i]));
+ }
+
+ return of_clk_add_hw_provider(ccm_node, of_clk_hw_onecell_get, clk_data);
+}
+
+static const struct of_device_id imx8qxp_match[] = {
+ { .compatible = "fsl,imx8qxp-clk", },
+ { /* sentinel */ }
+};
+
+static struct platform_driver imx8qxp_clk_driver = {
+ .driver = {
+ .name = "imx8qxp-clk",
+ .of_match_table = imx8qxp_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = imx8qxp_clk_probe,
+};
+builtin_platform_driver(imx8qxp_clk_driver);
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V9 5/7] dt-bindings: clock: add imx8qxp lpcg clock binding
2018-12-04 14:39 [PATCH V9 0/7] clk: imx: add imx8qxp clock support Aisheng DONG
` (3 preceding siblings ...)
2018-12-04 14:39 ` [PATCH V9 4/7] clk: imx: add imx8qxp clk driver Aisheng DONG
@ 2018-12-04 14:39 ` Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 6/7] clk: imx: add lpcg clock support Aisheng DONG
` (2 subsequent siblings)
7 siblings, 0 replies; 22+ messages in thread
From: Aisheng DONG @ 2018-12-04 14:39 UTC (permalink / raw)
To: linux-clk
Cc: linux-arm-kernel, sboyd, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel, Aisheng DONG, devicetree
The Low-Power Clock Gate (LPCG) modules contain a local programming
model to control the clock gates for the peripherals. An LPCG module
is used to locally gate the clocks for the associated peripheral.
Note:
This level of clock gating is provided after the clocks are generated
by the SCU resources and clock controls. Thus even if the clock is
enabled by these control bits, it might still not be running based
on the base resource.
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: devicetree@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
.../devicetree/bindings/clock/imx8qxp-lpcg.txt | 51 +++++++
include/dt-bindings/clock/imx8qxp-clock.h | 153 +++++++++++++++++++++
2 files changed, 204 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
new file mode 100644
index 0000000..965cfa4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
@@ -0,0 +1,51 @@
+* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
+
+The Low-Power Clock Gate (LPCG) modules contain a local programming
+model to control the clock gates for the peripherals. An LPCG module
+is used to locally gate the clocks for the associated peripheral.
+
+Note:
+This level of clock gating is provided after the clocks are generated
+by the SCU resources and clock controls. Thus even if the clock is
+enabled by these control bits, it might still not be running based
+on the base resource.
+
+Required properties:
+- compatible: Should be one of:
+ "fsl,imx8qxp-lpcg-adma",
+ "fsl,imx8qxp-lpcg-conn",
+ "fsl,imx8qxp-lpcg-dc",
+ "fsl,imx8qxp-lpcg-dsp",
+ "fsl,imx8qxp-lpcg-gpu",
+ "fsl,imx8qxp-lpcg-hsio",
+ "fsl,imx8qxp-lpcg-img",
+ "fsl,imx8qxp-lpcg-lsio",
+ "fsl,imx8qxp-lpcg-vpu"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.
+See the full list of clock IDs from:
+include/dt-bindings/clock/imx8qxp-clock.h
+
+Examples:
+
+#include <dt-bindings/clock/imx8qxp-clock.h>
+
+conn_lpcg: clock-controller@5b200000 {
+ compatible = "fsl,imx8qxp-lpcg-conn";
+ reg = <0x5b200000 0xb0000>;
+ #clock-cells = <1>;
+};
+
+usdhc1: mmc@5b010000 {
+ compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x5b010000 0x10000>;
+ clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>,
+ <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>,
+ <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>;
+ clock-names = "ipg", "per", "ahb";
+};
diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h
index d72a39c..6fec368 100644
--- a/include/dt-bindings/clock/imx8qxp-clock.h
+++ b/include/dt-bindings/clock/imx8qxp-clock.h
@@ -133,4 +133,157 @@
#define IMX8QXP_SCU_CLK_END 190
+/* LPCG clocks */
+
+/* LSIO SS LPCG */
+#define IMX8QXP_LSIO_LPCG_PWM0_IPG_CLK 0
+#define IMX8QXP_LSIO_LPCG_PWM0_IPG_S_CLK 1
+#define IMX8QXP_LSIO_LPCG_PWM0_IPG_HF_CLK 2
+#define IMX8QXP_LSIO_LPCG_PWM0_IPG_SLV_CLK 3
+#define IMX8QXP_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4
+#define IMX8QXP_LSIO_LPCG_PWM1_IPG_CLK 5
+#define IMX8QXP_LSIO_LPCG_PWM1_IPG_S_CLK 6
+#define IMX8QXP_LSIO_LPCG_PWM1_IPG_HF_CLK 7
+#define IMX8QXP_LSIO_LPCG_PWM1_IPG_SLV_CLK 8
+#define IMX8QXP_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9
+#define IMX8QXP_LSIO_LPCG_PWM2_IPG_CLK 10
+#define IMX8QXP_LSIO_LPCG_PWM2_IPG_S_CLK 11
+#define IMX8QXP_LSIO_LPCG_PWM2_IPG_HF_CLK 12
+#define IMX8QXP_LSIO_LPCG_PWM2_IPG_SLV_CLK 13
+#define IMX8QXP_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14
+#define IMX8QXP_LSIO_LPCG_PWM3_IPG_CLK 15
+#define IMX8QXP_LSIO_LPCG_PWM3_IPG_S_CLK 16
+#define IMX8QXP_LSIO_LPCG_PWM3_IPG_HF_CLK 17
+#define IMX8QXP_LSIO_LPCG_PWM3_IPG_SLV_CLK 18
+#define IMX8QXP_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19
+#define IMX8QXP_LSIO_LPCG_PWM4_IPG_CLK 20
+#define IMX8QXP_LSIO_LPCG_PWM4_IPG_S_CLK 21
+#define IMX8QXP_LSIO_LPCG_PWM4_IPG_HF_CLK 22
+#define IMX8QXP_LSIO_LPCG_PWM4_IPG_SLV_CLK 23
+#define IMX8QXP_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24
+#define IMX8QXP_LSIO_LPCG_PWM5_IPG_CLK 25
+#define IMX8QXP_LSIO_LPCG_PWM5_IPG_S_CLK 26
+#define IMX8QXP_LSIO_LPCG_PWM5_IPG_HF_CLK 27
+#define IMX8QXP_LSIO_LPCG_PWM5_IPG_SLV_CLK 28
+#define IMX8QXP_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29
+#define IMX8QXP_LSIO_LPCG_PWM6_IPG_CLK 30
+#define IMX8QXP_LSIO_LPCG_PWM6_IPG_S_CLK 31
+#define IMX8QXP_LSIO_LPCG_PWM6_IPG_HF_CLK 32
+#define IMX8QXP_LSIO_LPCG_PWM6_IPG_SLV_CLK 33
+#define IMX8QXP_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34
+#define IMX8QXP_LSIO_LPCG_PWM7_IPG_CLK 35
+#define IMX8QXP_LSIO_LPCG_PWM7_IPG_S_CLK 36
+#define IMX8QXP_LSIO_LPCG_PWM7_IPG_HF_CLK 37
+#define IMX8QXP_LSIO_LPCG_PWM7_IPG_SLV_CLK 38
+#define IMX8QXP_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39
+#define IMX8QXP_LSIO_LPCG_GPT0_IPG_CLK 40
+#define IMX8QXP_LSIO_LPCG_GPT0_IPG_S_CLK 41
+#define IMX8QXP_LSIO_LPCG_GPT0_IPG_HF_CLK 42
+#define IMX8QXP_LSIO_LPCG_GPT0_IPG_SLV_CLK 43
+#define IMX8QXP_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44
+#define IMX8QXP_LSIO_LPCG_GPT1_IPG_CLK 45
+#define IMX8QXP_LSIO_LPCG_GPT1_IPG_S_CLK 46
+#define IMX8QXP_LSIO_LPCG_GPT1_IPG_HF_CLK 47
+#define IMX8QXP_LSIO_LPCG_GPT1_IPG_SLV_CLK 48
+#define IMX8QXP_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49
+#define IMX8QXP_LSIO_LPCG_GPT2_IPG_CLK 50
+#define IMX8QXP_LSIO_LPCG_GPT2_IPG_S_CLK 51
+#define IMX8QXP_LSIO_LPCG_GPT2_IPG_HF_CLK 52
+#define IMX8QXP_LSIO_LPCG_GPT2_IPG_SLV_CLK 53
+#define IMX8QXP_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54
+#define IMX8QXP_LSIO_LPCG_GPT3_IPG_CLK 55
+#define IMX8QXP_LSIO_LPCG_GPT3_IPG_S_CLK 56
+#define IMX8QXP_LSIO_LPCG_GPT3_IPG_HF_CLK 57
+#define IMX8QXP_LSIO_LPCG_GPT3_IPG_SLV_CLK 58
+#define IMX8QXP_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59
+#define IMX8QXP_LSIO_LPCG_GPT4_IPG_CLK 60
+#define IMX8QXP_LSIO_LPCG_GPT4_IPG_S_CLK 61
+#define IMX8QXP_LSIO_LPCG_GPT4_IPG_HF_CLK 62
+#define IMX8QXP_LSIO_LPCG_GPT4_IPG_SLV_CLK 63
+#define IMX8QXP_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64
+#define IMX8QXP_LSIO_LPCG_FSPI0_HCLK 65
+#define IMX8QXP_LSIO_LPCG_FSPI0_IPG_CLK 66
+#define IMX8QXP_LSIO_LPCG_FSPI0_IPG_S_CLK 67
+#define IMX8QXP_LSIO_LPCG_FSPI0_IPG_SFCK 68
+#define IMX8QXP_LSIO_LPCG_FSPI1_HCLK 69
+#define IMX8QXP_LSIO_LPCG_FSPI1_IPG_CLK 70
+#define IMX8QXP_LSIO_LPCG_FSPI1_IPG_S_CLK 71
+#define IMX8QXP_LSIO_LPCG_FSPI1_IPG_SFCK 72
+
+#define IMX8QXP_LSIO_LPCG_CLK_END 73
+
+/* Connectivity SS LPCG */
+#define IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK 0
+#define IMX8QXP_CONN_LPCG_SDHC0_PER_CLK 1
+#define IMX8QXP_CONN_LPCG_SDHC0_HCLK 2
+#define IMX8QXP_CONN_LPCG_SDHC1_IPG_CLK 3
+#define IMX8QXP_CONN_LPCG_SDHC1_PER_CLK 4
+#define IMX8QXP_CONN_LPCG_SDHC1_HCLK 5
+#define IMX8QXP_CONN_LPCG_SDHC2_IPG_CLK 6
+#define IMX8QXP_CONN_LPCG_SDHC2_PER_CLK 7
+#define IMX8QXP_CONN_LPCG_SDHC2_HCLK 8
+#define IMX8QXP_CONN_LPCG_GPMI_APB_CLK 9
+#define IMX8QXP_CONN_LPCG_GPMI_BCH_APB_CLK 10
+#define IMX8QXP_CONN_LPCG_GPMI_BCH_IO_CLK 11
+#define IMX8QXP_CONN_LPCG_GPMI_BCH_CLK 12
+#define IMX8QXP_CONN_LPCG_APBHDMA_CLK 13
+#define IMX8QXP_CONN_LPCG_ENET0_ROOT_CLK 14
+#define IMX8QXP_CONN_LPCG_ENET0_TX_CLK 15
+#define IMX8QXP_CONN_LPCG_ENET0_AHB_CLK 16
+#define IMX8QXP_CONN_LPCG_ENET0_IPG_S_CLK 17
+#define IMX8QXP_CONN_LPCG_ENET0_IPG_CLK 18
+
+#define IMX8QXP_CONN_LPCG_ENET1_ROOT_CLK 19
+#define IMX8QXP_CONN_LPCG_ENET1_TX_CLK 20
+#define IMX8QXP_CONN_LPCG_ENET1_AHB_CLK 21
+#define IMX8QXP_CONN_LPCG_ENET1_IPG_S_CLK 22
+#define IMX8QXP_CONN_LPCG_ENET1_IPG_CLK 23
+
+#define IMX8QXP_CONN_LPCG_CLK_END 24
+
+/* ADMA SS LPCG */
+#define IMX8QXP_ADMA_LPCG_UART0_IPG_CLK 0
+#define IMX8QXP_ADMA_LPCG_UART0_BAUD_CLK 1
+#define IMX8QXP_ADMA_LPCG_UART1_IPG_CLK 2
+#define IMX8QXP_ADMA_LPCG_UART1_BAUD_CLK 3
+#define IMX8QXP_ADMA_LPCG_UART2_IPG_CLK 4
+#define IMX8QXP_ADMA_LPCG_UART2_BAUD_CLK 5
+#define IMX8QXP_ADMA_LPCG_UART3_IPG_CLK 6
+#define IMX8QXP_ADMA_LPCG_UART3_BAUD_CLK 7
+#define IMX8QXP_ADMA_LPCG_SPI0_IPG_CLK 8
+#define IMX8QXP_ADMA_LPCG_SPI1_IPG_CLK 9
+#define IMX8QXP_ADMA_LPCG_SPI2_IPG_CLK 10
+#define IMX8QXP_ADMA_LPCG_SPI3_IPG_CLK 11
+#define IMX8QXP_ADMA_LPCG_SPI0_CLK 12
+#define IMX8QXP_ADMA_LPCG_SPI1_CLK 13
+#define IMX8QXP_ADMA_LPCG_SPI2_CLK 14
+#define IMX8QXP_ADMA_LPCG_SPI3_CLK 15
+#define IMX8QXP_ADMA_LPCG_CAN0_IPG_CLK 16
+#define IMX8QXP_ADMA_LPCG_CAN0_IPG_PE_CLK 17
+#define IMX8QXP_ADMA_LPCG_CAN0_IPG_CHI_CLK 18
+#define IMX8QXP_ADMA_LPCG_CAN1_IPG_CLK 19
+#define IMX8QXP_ADMA_LPCG_CAN1_IPG_PE_CLK 20
+#define IMX8QXP_ADMA_LPCG_CAN1_IPG_CHI_CLK 21
+#define IMX8QXP_ADMA_LPCG_CAN2_IPG_CLK 22
+#define IMX8QXP_ADMA_LPCG_CAN2_IPG_PE_CLK 23
+#define IMX8QXP_ADMA_LPCG_CAN2_IPG_CHI_CLK 24
+#define IMX8QXP_ADMA_LPCG_I2C0_CLK 25
+#define IMX8QXP_ADMA_LPCG_I2C1_CLK 26
+#define IMX8QXP_ADMA_LPCG_I2C2_CLK 27
+#define IMX8QXP_ADMA_LPCG_I2C3_CLK 28
+#define IMX8QXP_ADMA_LPCG_I2C0_IPG_CLK 29
+#define IMX8QXP_ADMA_LPCG_I2C1_IPG_CLK 30
+#define IMX8QXP_ADMA_LPCG_I2C2_IPG_CLK 31
+#define IMX8QXP_ADMA_LPCG_I2C3_IPG_CLK 32
+#define IMX8QXP_ADMA_LPCG_FTM0_CLK 33
+#define IMX8QXP_ADMA_LPCG_FTM1_CLK 34
+#define IMX8QXP_ADMA_LPCG_FTM0_IPG_CLK 35
+#define IMX8QXP_ADMA_LPCG_FTM1_IPG_CLK 36
+#define IMX8QXP_ADMA_LPCG_PWM_HI_CLK 37
+#define IMX8QXP_ADMA_LPCG_PWM_IPG_CLK 38
+#define IMX8QXP_ADMA_LPCG_LCD_PIX_CLK 39
+#define IMX8QXP_ADMA_LPCG_LCD_APB_CLK 40
+
+#define IMX8QXP_ADMA_LPCG_CLK_END 41
+
#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V9 6/7] clk: imx: add lpcg clock support
2018-12-04 14:39 [PATCH V9 0/7] clk: imx: add imx8qxp clock support Aisheng DONG
` (4 preceding siblings ...)
2018-12-04 14:39 ` [PATCH V9 5/7] dt-bindings: clock: add imx8qxp lpcg clock binding Aisheng DONG
@ 2018-12-04 14:39 ` Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 7/7] clk: imx: add imx8qxp lpcg driver Aisheng DONG
2018-12-10 20:46 ` [PATCH V9 0/7] clk: imx: add imx8qxp clock support Stephen Boyd
7 siblings, 0 replies; 22+ messages in thread
From: Aisheng DONG @ 2018-12-04 14:39 UTC (permalink / raw)
To: linux-clk
Cc: linux-arm-kernel, sboyd, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel, Aisheng DONG
The Low-Power Clock Gate (LPCG) modules contain a local programming
model to control the clock gates for the peripherals. An LPCG module
is used to locally gate the clocks for the associated peripheral.
And they're bedind the SCU clock.
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/clk/imx/Makefile | 3 +-
drivers/clk/imx/clk-lpcg-scu.c | 114 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk-scu.h | 3 ++
3 files changed, 119 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/imx/clk-lpcg-scu.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 75312fb..4f72163 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -21,7 +21,8 @@ obj-$(CONFIG_MXC_CLK) += \
clk-sccg-pll.o
obj-$(CONFIG_MXC_CLK_SCU) += \
- clk-scu.o
+ clk-scu.o \
+ clk-lpcg-scu.o
obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c
new file mode 100644
index 0000000..fbf3416
--- /dev/null
+++ b/drivers/clk/imx/clk-lpcg-scu.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+static DEFINE_SPINLOCK(imx_lpcg_scu_lock);
+
+#define CLK_GATE_SCU_LPCG_MASK 0x3
+#define CLK_GATE_SCU_LPCG_HW_SEL BIT(0)
+#define CLK_GATE_SCU_LPCG_SW_SEL BIT(1)
+
+/*
+ * struct clk_lpcg_scu - Description of LPCG clock
+ *
+ * @hw: clk_hw of this LPCG
+ * @reg: register of this LPCG clock
+ * @bit_idx: bit index of this LPCG clock
+ * @hw_gate: HW auto gate enable
+ *
+ * This structure describes one LPCG clock
+ */
+struct clk_lpcg_scu {
+ struct clk_hw hw;
+ void __iomem *reg;
+ u8 bit_idx;
+ bool hw_gate;
+};
+
+#define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw)
+
+static int clk_lpcg_scu_enable(struct clk_hw *hw)
+{
+ struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw);
+ unsigned long flags;
+ u32 reg, val;
+
+ spin_lock_irqsave(&imx_lpcg_scu_lock, flags);
+
+ reg = readl_relaxed(clk->reg);
+ reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx);
+
+ val = CLK_GATE_SCU_LPCG_SW_SEL;
+ if (clk->hw_gate)
+ val |= CLK_GATE_SCU_LPCG_HW_SEL;
+
+ reg |= val << clk->bit_idx;
+ writel(reg, clk->reg);
+
+ spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);
+
+ return 0;
+}
+
+static void clk_lpcg_scu_disable(struct clk_hw *hw)
+{
+ struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&imx_lpcg_scu_lock, flags);
+
+ reg = readl_relaxed(clk->reg);
+ reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx);
+ writel(reg, clk->reg);
+
+ spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);
+}
+
+static const struct clk_ops clk_lpcg_scu_ops = {
+ .enable = clk_lpcg_scu_enable,
+ .disable = clk_lpcg_scu_disable,
+};
+
+struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name,
+ unsigned long flags, void __iomem *reg,
+ u8 bit_idx, bool hw_gate)
+{
+ struct clk_lpcg_scu *clk;
+ struct clk_init_data init;
+ struct clk_hw *hw;
+ int ret;
+
+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+ if (!clk)
+ return ERR_PTR(-ENOMEM);
+
+ clk->reg = reg;
+ clk->bit_idx = bit_idx;
+ clk->hw_gate = hw_gate;
+
+ init.name = name;
+ init.ops = &clk_lpcg_scu_ops;
+ init.flags = CLK_SET_RATE_PARENT | flags;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+
+ clk->hw.init = &init;
+
+ hw = &clk->hw;
+ ret = clk_hw_register(NULL, hw);
+ if (ret) {
+ kfree(clk);
+ hw = ERR_PTR(ret);
+ }
+
+ return hw;
+}
diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
index 09f381b..b8e91b1 100644
--- a/drivers/clk/imx/clk-scu.h
+++ b/drivers/clk/imx/clk-scu.h
@@ -18,4 +18,7 @@ static inline int imx_clk_scu_init(void)
struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id, u8 clk_type);
+struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name,
+ unsigned long flags, void __iomem *reg,
+ u8 bit_idx, bool hw_gate);
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V9 7/7] clk: imx: add imx8qxp lpcg driver
2018-12-04 14:39 [PATCH V9 0/7] clk: imx: add imx8qxp clock support Aisheng DONG
` (5 preceding siblings ...)
2018-12-04 14:39 ` [PATCH V9 6/7] clk: imx: add lpcg clock support Aisheng DONG
@ 2018-12-04 14:39 ` Aisheng DONG
2018-12-10 20:46 ` [PATCH V9 0/7] clk: imx: add imx8qxp clock support Stephen Boyd
7 siblings, 0 replies; 22+ messages in thread
From: Aisheng DONG @ 2018-12-04 14:39 UTC (permalink / raw)
To: linux-clk
Cc: linux-arm-kernel, sboyd, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel, Aisheng DONG
Add imx8qxp lpcg driver support
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/clk/imx/Makefile | 2 +-
drivers/clk/imx/clk-imx8qxp-lpcg.c | 216 +++++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk-imx8qxp-lpcg.h | 102 ++++++++++++++++++
3 files changed, 319 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/imx/clk-imx8qxp-lpcg.c
create mode 100644 drivers/clk/imx/clk-imx8qxp-lpcg.h
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 4f72163..ba6521c 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -41,4 +41,4 @@ obj-$(CONFIG_SOC_IMX7ULP) += clk-imx7ulp.o
obj-$(CONFIG_SOC_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o
-obj-$(CONFIG_SOC_IMX8QXP) += clk-imx8qxp.o
+obj-$(CONFIG_SOC_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o
diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
new file mode 100644
index 0000000..dcae1dd
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk-scu.h"
+#include "clk-imx8qxp-lpcg.h"
+
+#include <dt-bindings/clock/imx8qxp-clock.h>
+
+/*
+ * struct imx8qxp_lpcg_data - Description of one LPCG clock
+ * @id: clock ID
+ * @name: clock name
+ * @parent: parent clock name
+ * @flags: common clock flags
+ * @offset: offset of this LPCG clock
+ * @bit_idx: bit index of this LPCG clock
+ * @hw_gate: whether supports HW autogate
+ *
+ * This structure describes one LPCG clock
+ */
+struct imx8qxp_lpcg_data {
+ int id;
+ char *name;
+ char *parent;
+ unsigned long flags;
+ u32 offset;
+ u8 bit_idx;
+ bool hw_gate;
+};
+
+/*
+ * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks
+ * @lpcg: LPCG clocks array of one subsystem
+ * @num_lpcg: the number of LPCG clocks
+ * @num_max: the maximum number of LPCG clocks
+ *
+ * This structure describes each subsystem LPCG clocks information
+ * which then will be used to create respective LPCGs clocks
+ */
+struct imx8qxp_ss_lpcg {
+ const struct imx8qxp_lpcg_data *lpcg;
+ u8 num_lpcg;
+ u8 num_max;
+};
+
+static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = {
+ { IMX8QXP_ADMA_LPCG_UART0_IPG_CLK, "uart0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_0_LPCG, 16, 0, },
+ { IMX8QXP_ADMA_LPCG_UART0_BAUD_CLK, "uart0_lpcg_baud_clk", "uart0_clk", 0, ADMA_LPUART_0_LPCG, 0, 0, },
+ { IMX8QXP_ADMA_LPCG_UART1_IPG_CLK, "uart1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_1_LPCG, 16, 0, },
+ { IMX8QXP_ADMA_LPCG_UART1_BAUD_CLK, "uart1_lpcg_baud_clk", "uart1_clk", 0, ADMA_LPUART_1_LPCG, 0, 0, },
+ { IMX8QXP_ADMA_LPCG_UART2_IPG_CLK, "uart2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_2_LPCG, 16, 0, },
+ { IMX8QXP_ADMA_LPCG_UART2_BAUD_CLK, "uart2_lpcg_baud_clk", "uart2_clk", 0, ADMA_LPUART_2_LPCG, 0, 0, },
+ { IMX8QXP_ADMA_LPCG_UART3_IPG_CLK, "uart3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_3_LPCG, 16, 0, },
+ { IMX8QXP_ADMA_LPCG_UART3_BAUD_CLK, "uart3_lpcg_baud_clk", "uart3_clk", 0, ADMA_LPUART_3_LPCG, 0, 0, },
+ { IMX8QXP_ADMA_LPCG_I2C0_IPG_CLK, "i2c0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_0_LPCG, 16, 0, },
+ { IMX8QXP_ADMA_LPCG_I2C0_CLK, "i2c0_lpcg_clk", "i2c0_clk", 0, ADMA_LPI2C_0_LPCG, 0, 0, },
+ { IMX8QXP_ADMA_LPCG_I2C1_IPG_CLK, "i2c1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_1_LPCG, 16, 0, },
+ { IMX8QXP_ADMA_LPCG_I2C1_CLK, "i2c1_lpcg_clk", "i2c1_clk", 0, ADMA_LPI2C_1_LPCG, 0, 0, },
+ { IMX8QXP_ADMA_LPCG_I2C2_IPG_CLK, "i2c2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_2_LPCG, 16, 0, },
+ { IMX8QXP_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, },
+ { IMX8QXP_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, },
+ { IMX8QXP_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, },
+};
+
+static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = {
+ .lpcg = imx8qxp_lpcg_adma,
+ .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_adma),
+ .num_max = IMX8QXP_ADMA_LPCG_CLK_END,
+};
+
+static const struct imx8qxp_lpcg_data imx8qxp_lpcg_conn[] = {
+ { IMX8QXP_CONN_LPCG_SDHC0_PER_CLK, "sdhc0_lpcg_per_clk", "sdhc0_clk", 0, CONN_USDHC_0_LPCG, 0, 0, },
+ { IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK, "sdhc0_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_0_LPCG, 16, 0, },
+ { IMX8QXP_CONN_LPCG_SDHC0_HCLK, "sdhc0_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_0_LPCG, 20, 0, },
+ { IMX8QXP_CONN_LPCG_SDHC1_PER_CLK, "sdhc1_lpcg_per_clk", "sdhc1_clk", 0, CONN_USDHC_1_LPCG, 0, 0, },
+ { IMX8QXP_CONN_LPCG_SDHC1_IPG_CLK, "sdhc1_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_1_LPCG, 16, 0, },
+ { IMX8QXP_CONN_LPCG_SDHC1_HCLK, "sdhc1_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_1_LPCG, 20, 0, },
+ { IMX8QXP_CONN_LPCG_SDHC2_PER_CLK, "sdhc2_lpcg_per_clk", "sdhc2_clk", 0, CONN_USDHC_2_LPCG, 0, 0, },
+ { IMX8QXP_CONN_LPCG_SDHC2_IPG_CLK, "sdhc2_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_2_LPCG, 16, 0, },
+ { IMX8QXP_CONN_LPCG_SDHC2_HCLK, "sdhc2_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_2_LPCG, 20, 0, },
+ { IMX8QXP_CONN_LPCG_ENET0_ROOT_CLK, "enet0_ipg_root_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 0, 0, },
+ { IMX8QXP_CONN_LPCG_ENET0_TX_CLK, "enet0_tx_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 4, 0, },
+ { IMX8QXP_CONN_LPCG_ENET0_AHB_CLK, "enet0_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_0_LPCG, 8, 0, },
+ { IMX8QXP_CONN_LPCG_ENET0_IPG_S_CLK, "enet0_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_0_LPCG, 20, 0, },
+ { IMX8QXP_CONN_LPCG_ENET0_IPG_CLK, "enet0_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_0_LPCG, 16, 0, },
+ { IMX8QXP_CONN_LPCG_ENET1_ROOT_CLK, "enet1_ipg_root_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 0, 0, },
+ { IMX8QXP_CONN_LPCG_ENET1_TX_CLK, "enet1_tx_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 4, 0, },
+ { IMX8QXP_CONN_LPCG_ENET1_AHB_CLK, "enet1_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_1_LPCG, 8, 0, },
+ { IMX8QXP_CONN_LPCG_ENET1_IPG_S_CLK, "enet1_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_1_LPCG, 20, 0, },
+ { IMX8QXP_CONN_LPCG_ENET1_IPG_CLK, "enet1_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_1_LPCG, 16, 0, },
+};
+
+static const struct imx8qxp_ss_lpcg imx8qxp_ss_conn = {
+ .lpcg = imx8qxp_lpcg_conn,
+ .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_conn),
+ .num_max = IMX8QXP_CONN_LPCG_CLK_END,
+};
+
+static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = {
+ { IMX8QXP_LSIO_LPCG_PWM0_IPG_CLK, "pwm0_lpcg_ipg_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 0, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM0_IPG_HF_CLK, "pwm0_lpcg_ipg_hf_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 4, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM0_IPG_S_CLK, "pwm0_lpcg_ipg_s_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 16, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM0_IPG_SLV_CLK, "pwm0_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_0_LPCG, 20, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM0_IPG_MSTR_CLK, "pwm0_lpcg_ipg_mstr_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 24, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM1_IPG_CLK, "pwm1_lpcg_ipg_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 0, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM1_IPG_HF_CLK, "pwm1_lpcg_ipg_hf_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 4, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM1_IPG_S_CLK, "pwm1_lpcg_ipg_s_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 16, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM1_IPG_SLV_CLK, "pwm1_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_1_LPCG, 20, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM1_IPG_MSTR_CLK, "pwm1_lpcg_ipg_mstr_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 24, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM2_IPG_CLK, "pwm2_lpcg_ipg_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 0, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM2_IPG_HF_CLK, "pwm2_lpcg_ipg_hf_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 4, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM2_IPG_S_CLK, "pwm2_lpcg_ipg_s_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 16, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM2_IPG_SLV_CLK, "pwm2_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_2_LPCG, 20, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM2_IPG_MSTR_CLK, "pwm2_lpcg_ipg_mstr_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 24, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM3_IPG_CLK, "pwm3_lpcg_ipg_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 0, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM3_IPG_HF_CLK, "pwm3_lpcg_ipg_hf_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 4, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM3_IPG_S_CLK, "pwm3_lpcg_ipg_s_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 16, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM3_IPG_SLV_CLK, "pwm3_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_3_LPCG, 20, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM3_IPG_MSTR_CLK, "pwm3_lpcg_ipg_mstr_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 24, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM4_IPG_CLK, "pwm4_lpcg_ipg_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 0, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM4_IPG_HF_CLK, "pwm4_lpcg_ipg_hf_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 4, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM4_IPG_S_CLK, "pwm4_lpcg_ipg_s_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 16, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM4_IPG_SLV_CLK, "pwm4_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_4_LPCG, 20, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM4_IPG_MSTR_CLK, "pwm4_lpcg_ipg_mstr_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 24, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM5_IPG_CLK, "pwm5_lpcg_ipg_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 0, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM5_IPG_HF_CLK, "pwm5_lpcg_ipg_hf_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 4, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM5_IPG_S_CLK, "pwm5_lpcg_ipg_s_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 16, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM5_IPG_SLV_CLK, "pwm5_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_5_LPCG, 20, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM5_IPG_MSTR_CLK, "pwm5_lpcg_ipg_mstr_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 24, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM6_IPG_CLK, "pwm6_lpcg_ipg_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 0, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM6_IPG_HF_CLK, "pwm6_lpcg_ipg_hf_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 4, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM6_IPG_S_CLK, "pwm6_lpcg_ipg_s_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 16, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM6_IPG_SLV_CLK, "pwm6_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_6_LPCG, 20, 0, },
+ { IMX8QXP_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, },
+};
+
+static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
+ .lpcg = imx8qxp_lpcg_lsio,
+ .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio),
+ .num_max = IMX8QXP_LSIO_LPCG_CLK_END,
+};
+
+static int imx8qxp_lpcg_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct clk_hw_onecell_data *clk_data;
+ const struct imx8qxp_ss_lpcg *ss_lpcg;
+ const struct imx8qxp_lpcg_data *lpcg;
+ struct resource *res;
+ struct clk_hw **clks;
+ void __iomem *base;
+ int i;
+
+ ss_lpcg = of_device_get_match_data(dev);
+ if (!ss_lpcg)
+ return -ENODEV;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap(dev, res->start, resource_size(res));
+ if (!base)
+ return -ENOMEM;
+
+ clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
+ ss_lpcg->num_max), GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
+ clk_data->num = ss_lpcg->num_max;
+ clks = clk_data->hws;
+
+ for (i = 0; i < ss_lpcg->num_lpcg; i++) {
+ lpcg = ss_lpcg->lpcg + i;
+ clks[lpcg->id] = imx_clk_lpcg_scu(lpcg->name, lpcg->parent,
+ lpcg->flags, base + lpcg->offset,
+ lpcg->bit_idx, lpcg->hw_gate);
+ }
+
+ for (i = 0; i < clk_data->num; i++) {
+ if (IS_ERR(clks[i]))
+ pr_warn("i.MX clk %u: register failed with %ld\n",
+ i, PTR_ERR(clks[i]));
+ }
+
+ return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
+}
+
+static const struct of_device_id imx8qxp_lpcg_match[] = {
+ { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
+ { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
+ { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver imx8qxp_lpcg_clk_driver = {
+ .driver = {
+ .name = "imx8qxp-lpcg-clk",
+ .of_match_table = imx8qxp_lpcg_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = imx8qxp_lpcg_clk_probe,
+};
+
+builtin_platform_driver(imx8qxp_lpcg_clk_driver);
diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h b/drivers/clk/imx/clk-imx8qxp-lpcg.h
new file mode 100644
index 0000000..2a37ce5
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#ifndef _IMX8QXP_LPCG_H
+#define _IMX8QXP_LPCG_H
+
+/*LSIO SS */
+#define LSIO_PWM_0_LPCG 0x00000
+#define LSIO_PWM_1_LPCG 0x10000
+#define LSIO_PWM_2_LPCG 0x20000
+#define LSIO_PWM_3_LPCG 0x30000
+#define LSIO_PWM_4_LPCG 0x40000
+#define LSIO_PWM_5_LPCG 0x50000
+#define LSIO_PWM_6_LPCG 0x60000
+#define LSIO_PWM_7_LPCG 0x70000
+#define LSIO_GPIO_0_LPCG 0x80000
+#define LSIO_GPIO_1_LPCG 0x90000
+#define LSIO_GPIO_2_LPCG 0xa0000
+#define LSIO_GPIO_3_LPCG 0xb0000
+#define LSIO_GPIO_4_LPCG 0xc0000
+#define LSIO_GPIO_5_LPCG 0xd0000
+#define LSIO_GPIO_6_LPCG 0xe0000
+#define LSIO_GPIO_7_LPCG 0xf0000
+#define LSIO_FSPI_0_LPCG 0x120000
+#define LSIO_FSPI_1_LPCG 0x130000
+#define LSIO_GPT_0_LPCG 0x140000
+#define LSIO_GPT_1_LPCG 0x150000
+#define LSIO_GPT_2_LPCG 0x160000
+#define LSIO_GPT_3_LPCG 0x170000
+#define LSIO_GPT_4_LPCG 0x180000
+#define LSIO_OCRAM_LPCG 0x190000
+#define LSIO_KPP_LPCG 0x1a0000
+#define LSIO_ROMCP_LPCG 0x100000
+
+/* Connectivity SS */
+#define CONN_USDHC_0_LPCG 0x00000
+#define CONN_USDHC_1_LPCG 0x10000
+#define CONN_USDHC_2_LPCG 0x20000
+#define CONN_ENET_0_LPCG 0x30000
+#define CONN_ENET_1_LPCG 0x40000
+#define CONN_DTCP_LPCG 0x50000
+#define CONN_MLB_LPCG 0x60000
+#define CONN_USB_2_LPCG 0x70000
+#define CONN_USB_3_LPCG 0x80000
+#define CONN_NAND_LPCG 0x90000
+#define CONN_EDMA_LPCG 0xa0000
+
+/* ADMA SS */
+#define ADMA_ASRC_0_LPCG 0x400000
+#define ADMA_ESAI_0_LPCG 0x410000
+#define ADMA_SPDIF_0_LPCG 0x420000
+#define ADMA_SAI_0_LPCG 0x440000
+#define ADMA_SAI_1_LPCG 0x450000
+#define ADMA_SAI_2_LPCG 0x460000
+#define ADMA_SAI_3_LPCG 0x470000
+#define ADMA_GPT_5_LPCG 0x4b0000
+#define ADMA_GPT_6_LPCG 0x4c0000
+#define ADMA_GPT_7_LPCG 0x4d0000
+#define ADMA_GPT_8_LPCG 0x4e0000
+#define ADMA_GPT_9_LPCG 0x4f0000
+#define ADMA_GPT_10_LPCG 0x500000
+#define ADMA_HIFI_LPCG 0x580000
+#define ADMA_OCRAM_LPCG 0x590000
+#define ADMA_EDMA_0_LPCG 0x5f0000
+#define ADMA_ASRC_1_LPCG 0xc00000
+#define ADMA_SAI_4_LPCG 0xc20000
+#define ADMA_SAI_5_LPCG 0xc30000
+#define ADMA_AMIX_LPCG 0xc40000
+#define ADMA_MQS_LPCG 0xc50000
+#define ADMA_ACM_LPCG 0xc60000
+#define ADMA_REC_CLK0_LPCG 0xd00000
+#define ADMA_REC_CLK1_LPCG 0xd10000
+#define ADMA_PLL_CLK0_LPCG 0xd20000
+#define ADMA_PLL_CLK1_LPCG 0xd30000
+#define ADMA_MCLKOUT0_LPCG 0xd50000
+#define ADMA_MCLKOUT1_LPCG 0xd60000
+#define ADMA_EDMA_1_LPCG 0xdf0000
+#define ADMA_LPSPI_0_LPCG 0x1400000
+#define ADMA_LPSPI_1_LPCG 0x1410000
+#define ADMA_LPSPI_2_LPCG 0x1420000
+#define ADMA_LPSPI_3_LPCG 0x1430000
+#define ADMA_LPUART_0_LPCG 0x1460000
+#define ADMA_LPUART_1_LPCG 0x1470000
+#define ADMA_LPUART_2_LPCG 0x1480000
+#define ADMA_LPUART_3_LPCG 0x1490000
+#define ADMA_LCD_LPCG 0x1580000
+#define ADMA_PWM_LPCG 0x1590000
+#define ADMA_LPI2C_0_LPCG 0x1c00000
+#define ADMA_LPI2C_1_LPCG 0x1c10000
+#define ADMA_LPI2C_2_LPCG 0x1c20000
+#define ADMA_LPI2C_3_LPCG 0x1c30000
+#define ADMA_ADC_0_LPCG 0x1c80000
+#define ADMA_FTM_0_LPCG 0x1ca0000
+#define ADMA_FTM_1_LPCG 0x1cb0000
+#define ADMA_FLEXCAN_0_LPCG 0x1cd0000
+#define ADMA_FLEXCAN_1_LPCG 0x1ce0000
+#define ADMA_FLEXCAN_2_LPCG 0x1cf0000
+
+#endif /* _IMX8QXP_LPCG_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH V9 0/7] clk: imx: add imx8qxp clock support
2018-12-04 14:39 [PATCH V9 0/7] clk: imx: add imx8qxp clock support Aisheng DONG
` (6 preceding siblings ...)
2018-12-04 14:39 ` [PATCH V9 7/7] clk: imx: add imx8qxp lpcg driver Aisheng DONG
@ 2018-12-10 20:46 ` Stephen Boyd
2018-12-11 2:04 ` Aisheng Dong
2018-12-11 4:05 ` Aisheng Dong
7 siblings, 2 replies; 22+ messages in thread
From: Stephen Boyd @ 2018-12-10 20:46 UTC (permalink / raw)
To: linux-clk, Aisheng DONG
Cc: linux-arm-kernel, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel, Aisheng DONG
Quoting Aisheng DONG (2018-12-04 06:39:18)
> This patch series adds i.MX8QXP clock support which is based
> on the clock service provided by SCU firmware.
>
> Note: It depends on SCU driver which has already been merged by Shawn.
> So this patch series could go through Shawn's tree as well.
Which patch series?
I'm having trouble applying the first patch, so I suspect something is
wrong.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V9 1/7] clk: imx: add configuration option for mmio clks
2018-12-04 14:39 ` [PATCH V9 1/7] clk: imx: add configuration option for mmio clks Aisheng DONG
@ 2018-12-10 20:55 ` Stephen Boyd
2018-12-11 2:36 ` Aisheng Dong
0 siblings, 1 reply; 22+ messages in thread
From: Stephen Boyd @ 2018-12-10 20:55 UTC (permalink / raw)
To: linux-clk, Aisheng DONG
Cc: linux-arm-kernel, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel, Aisheng DONG
Quoting Aisheng DONG (2018-12-04 06:39:22)
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index c12a05c..303082c 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -570,6 +580,7 @@ config SOC_IMX7ULP
> config SOC_VF610
> bool "Vybrid Family VF610 support"
> select ARM_GIC if ARCH_MULTI_V7
> + select MXC_CLK
> select PINCTRL_VF610
>
Instead of select can we break this dependency on the arch Kconfig and
have:
config MXC_CLK
def_bool ARCH_MXC && !ARM64
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 5c0b11e..f850424 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -1,6 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -obj-y += \
> +obj-$(CONFIG_MXC_CLK) += \
Because this changes to obj-$(CONFIG) we should change the
drivers/clk/Makefile to have obj-y for this Makefile instead of
depending on ARCH_MXC.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V9 2/7] clk: imx: add scu clock common part
2018-12-04 14:39 ` [PATCH V9 2/7] clk: imx: add scu clock common part Aisheng DONG
@ 2018-12-10 21:56 ` Stephen Boyd
2018-12-11 3:35 ` Aisheng Dong
0 siblings, 1 reply; 22+ messages in thread
From: Stephen Boyd @ 2018-12-10 21:56 UTC (permalink / raw)
To: linux-clk, Aisheng DONG
Cc: linux-arm-kernel, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel, Aisheng DONG
Quoting Aisheng DONG (2018-12-04 06:39:25)
> diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
> index 43a3ecc..63e7b01 100644
> --- a/drivers/clk/imx/Kconfig
> +++ b/drivers/clk/imx/Kconfig
> @@ -3,3 +3,7 @@
> config MXC_CLK
> bool
> depends on ARCH_MXC
> +
> +config MXC_CLK_SCU
Is there any reason to make this a hidden option instead of making it a
selectable option? It can still depend on ARCH_MXC and ARM64, but
otherwise it should be compilable as long as CONFIG_IMX_SCU is defined
(this should also be a config we depend on here).
> + bool
> + depends on ARCH_MXC && ARM64
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index f850424..4abed37 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -20,6 +20,9 @@ obj-$(CONFIG_MXC_CLK) += \
> clk-pllv4.o \
> clk-sccg-pll.o
>
> +obj-$(CONFIG_MXC_CLK_SCU) += \
> + clk-scu.o
> +
> obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
> obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
> obj-$(CONFIG_SOC_IMX25) += clk-imx25.o
> diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
> new file mode 100644
> index 0000000..ec8a471
> --- /dev/null
> +++ b/drivers/clk/imx/clk-scu.c
> @@ -0,0 +1,265 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + * Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/slab.h>
> +
> +#include "clk-scu.h"
> +
> +struct imx_sc_ipc *ccm_ipc_handle;
Why does this need to be a global? Can it be in each clk_scu instance
instead?
> +
> diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h
> new file mode 100644
> index 0000000..09f381b
> --- /dev/null
> +++ b/drivers/clk/imx/clk-scu.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + * Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +#ifndef __IMX_CLK_SCU_H
> +#define __IMX_CLK_SCU_H
> +
> +#include <linux/firmware/imx/sci.h>
> +
> +extern struct imx_sc_ipc *ccm_ipc_handle;
> +
> +static inline int imx_clk_scu_init(void)
> +{
> + return imx_scu_get_handle(&ccm_ipc_handle);
And then this can be implemented in the C driver so that ccm_ipc_handle
doesn't need to be exported into the header file?
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V9 0/7] clk: imx: add imx8qxp clock support
2018-12-10 20:46 ` [PATCH V9 0/7] clk: imx: add imx8qxp clock support Stephen Boyd
@ 2018-12-11 2:04 ` Aisheng Dong
2018-12-11 4:05 ` Aisheng Dong
1 sibling, 0 replies; 22+ messages in thread
From: Aisheng Dong @ 2018-12-11 2:04 UTC (permalink / raw)
To: Stephen Boyd, linux-clk
Cc: linux-arm-kernel, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel
> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd@kernel.org]
> Sent: Tuesday, December 11, 2018 4:47 AM
> To: linux-clk@vger.kernel.org; Aisheng Dong <aisheng.dong@nxp.com>
> Cc: linux-arm-kernel@lists.infradead.org; mturquette@baylibre.com;
> shawnguo@kernel.org; Fabio Estevam <fabio.estevam@nxp.com>; dl-linux-imx
> <linux-imx@nxp.com>; kernel@pengutronix.de; Aisheng Dong
> <aisheng.dong@nxp.com>
> Subject: Re: [PATCH V9 0/7] clk: imx: add imx8qxp clock support
>
> Quoting Aisheng DONG (2018-12-04 06:39:18)
> > This patch series adds i.MX8QXP clock support which is based on the
> > clock service provided by SCU firmware.
> >
> > Note: It depends on SCU driver which has already been merged by Shawn.
> > So this patch series could go through Shawn's tree as well.
>
> Which patch series?
>
> I'm having trouble applying the first patch, so I suspect something is wrong.
Which branch would you like me to make the patch against?
I made the patch against clk-next branch and just re-tested it was ok.
BTW, it depends on the following SCU firmware patch which already in 4.20-RC
In your tree. So it's safe to apply.
commit edbee095fafb4b727b51032bdc41e345f95bbc20
Author: Dong Aisheng <aisheng.dong@nxp.com>
Date: Sun Oct 7 21:04:42 2018 +0800
firmware: imx: add SCU firmware driver support
The System Controller Firmware (SCFW) is a low-level system function
which runs on a dedicated Cortex-M core to provide power, clock, and
resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
(QM, QP), and i.MX8QX (QXP, DX).
This patch implements the SCU firmware IPC function and the common
message sending API sc_call_rpc.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jassi Brar <jassisinghbrar@gmail.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V9 1/7] clk: imx: add configuration option for mmio clks
2018-12-10 20:55 ` Stephen Boyd
@ 2018-12-11 2:36 ` Aisheng Dong
2018-12-11 19:29 ` Stephen Boyd
0 siblings, 1 reply; 22+ messages in thread
From: Aisheng Dong @ 2018-12-11 2:36 UTC (permalink / raw)
To: Stephen Boyd, linux-clk
Cc: linux-arm-kernel, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel
> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd@kernel.org]
> Sent: Tuesday, December 11, 2018 4:55 AM
[...]
> Subject: Re: [PATCH V9 1/7] clk: imx: add configuration option for mmio clks
>
> Quoting Aisheng DONG (2018-12-04 06:39:22)
> > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> > index c12a05c..303082c 100644
> > --- a/arch/arm/mach-imx/Kconfig
> > +++ b/arch/arm/mach-imx/Kconfig
> > @@ -570,6 +580,7 @@ config SOC_IMX7ULP config SOC_VF610
> > bool "Vybrid Family VF610 support"
> > select ARM_GIC if ARCH_MULTI_V7
> > + select MXC_CLK
> > select PINCTRL_VF610
> >
>
> Instead of select can we break this dependency on the arch Kconfig and
> have:
>
> config MXC_CLK
> def_bool ARCH_MXC && !ARM64
>
Thanks for the suggestion.
One little problem is that we also have LS1021 supported under ARCH_MXC which
does not use MXC_CLK.
> > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index
> > 5c0b11e..f850424 100644
> > --- a/drivers/clk/imx/Makefile
> > +++ b/drivers/clk/imx/Makefile
> > @@ -1,6 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> >
> > -obj-y += \
> > +obj-$(CONFIG_MXC_CLK) += \
>
> Because this changes to obj-$(CONFIG) we should change the
> drivers/clk/Makefile to have obj-y for this Makefile instead of depending on
> ARCH_MXC.
We also use ARCH_MXC for ARMv8 SoC clocks.
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V9 2/7] clk: imx: add scu clock common part
2018-12-10 21:56 ` Stephen Boyd
@ 2018-12-11 3:35 ` Aisheng Dong
2018-12-17 10:27 ` Lothar Waßmann
0 siblings, 1 reply; 22+ messages in thread
From: Aisheng Dong @ 2018-12-11 3:35 UTC (permalink / raw)
To: Stephen Boyd, linux-clk
Cc: linux-arm-kernel, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel
> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd@kernel.org]
> Quoting Aisheng DONG (2018-12-04 06:39:25)
> > diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index
> > 43a3ecc..63e7b01 100644
> > --- a/drivers/clk/imx/Kconfig
> > +++ b/drivers/clk/imx/Kconfig
> > @@ -3,3 +3,7 @@
> > config MXC_CLK
> > bool
> > depends on ARCH_MXC
> > +
> > +config MXC_CLK_SCU
>
> Is there any reason to make this a hidden option instead of making it a
> selectable option? It can still depend on ARCH_MXC and ARM64, but otherwise
> it should be compilable as long as CONFIG_IMX_SCU is defined (this should
> also be a config we depend on here).
>
This is mostly following the exist using that CLK is selected by SoC config option.
https://patchwork.kernel.org/patch/10677309/
As CLK usually is required for platform to run well, so we did not make it selectable.
> > + bool
> > + depends on ARCH_MXC && ARM64
> > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index
> > f850424..4abed37 100644
> > --- a/drivers/clk/imx/Makefile
> > +++ b/drivers/clk/imx/Makefile
> > @@ -20,6 +20,9 @@ obj-$(CONFIG_MXC_CLK) += \
> > clk-pllv4.o \
> > clk-sccg-pll.o
> >
> > +obj-$(CONFIG_MXC_CLK_SCU) += \
> > + clk-scu.o
> > +
> > obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
> > obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
> > obj-$(CONFIG_SOC_IMX25) += clk-imx25.o diff --git
> > a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c new file mode
> > 100644 index 0000000..ec8a471
> > --- /dev/null
> > +++ b/drivers/clk/imx/clk-scu.c
> > @@ -0,0 +1,265 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2018 NXP
> > + * Dong Aisheng <aisheng.dong@nxp.com>
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/err.h>
> > +#include <linux/slab.h>
> > +
> > +#include "clk-scu.h"
> > +
> > +struct imx_sc_ipc *ccm_ipc_handle;
>
> Why does this need to be a global? Can it be in each clk_scu instance instead?
>
No, no need to be in each clk_scu instance.
There's only one handler.
> > +
> > diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h new
> > file mode 100644 index 0000000..09f381b
> > --- /dev/null
> > +++ b/drivers/clk/imx/clk-scu.h
> > @@ -0,0 +1,21 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2018 NXP
> > + * Dong Aisheng <aisheng.dong@nxp.com>
> > + */
> > +
> > +#ifndef __IMX_CLK_SCU_H
> > +#define __IMX_CLK_SCU_H
> > +
> > +#include <linux/firmware/imx/sci.h>
> > +
> > +extern struct imx_sc_ipc *ccm_ipc_handle;
> > +
> > +static inline int imx_clk_scu_init(void) {
> > + return imx_scu_get_handle(&ccm_ipc_handle);
>
> And then this can be implemented in the C driver so that ccm_ipc_handle
> doesn't need to be exported into the header file?
Looks like a good suggestion.
I will take this as there's no other users of ccm_ipc_handle now, so no need in headfile.
Thanks
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V9 0/7] clk: imx: add imx8qxp clock support
2018-12-10 20:46 ` [PATCH V9 0/7] clk: imx: add imx8qxp clock support Stephen Boyd
2018-12-11 2:04 ` Aisheng Dong
@ 2018-12-11 4:05 ` Aisheng Dong
1 sibling, 0 replies; 22+ messages in thread
From: Aisheng Dong @ 2018-12-11 4:05 UTC (permalink / raw)
To: Stephen Boyd, linux-clk
Cc: linux-arm-kernel, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel
> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd@kernel.org]
> Quoting Aisheng DONG (2018-12-04 06:39:18)
> > This patch series adds i.MX8QXP clock support which is based on the
> > clock service provided by SCU firmware.
> >
> > Note: It depends on SCU driver which has already been merged by Shawn.
> > So this patch series could go through Shawn's tree as well.
>
> Which patch series?
>
> I'm having trouble applying the first patch, so I suspect something is wrong.
As I replied in last mail, patches were made against clk-next branch.
I also tried apply against clk-master branch and met the same failure.
$ git am *.patch
Patch is empty. Was it split wrong?
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
$ git am --skip
Applying: clk: imx: add configuration option for mmio clks
error: patch failed: drivers/clk/imx/Makefile:1
error: drivers/clk/imx/Makefile: patch does not apply
Patch failed at 0002 clk: imx: add configuration option for mmio clks
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
If manually apply, it can work.
$ patch -p1 < 0001-clk-imx-add-configuration-option-for-mmio-clks.patch
patching file arch/arm/mach-imx/Kconfig
Hunk #7 succeeded at 571 (offset -9 lines).
patching file drivers/clk/Kconfig
patching file drivers/clk/imx/Kconfig
patching file drivers/clk/imx/Makefile
Hunk #1 succeeded at 1 with fuzz 1.
I guess it might because clk-next merged clk-imx7ulp.c and clk-imx8mq.c which
Changed the drivers/clk/imx/Makefile a bit.
If you want me to generate the patch set against clk-master, please let me know.
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V9 1/7] clk: imx: add configuration option for mmio clks
2018-12-11 2:36 ` Aisheng Dong
@ 2018-12-11 19:29 ` Stephen Boyd
2018-12-12 1:09 ` Aisheng Dong
0 siblings, 1 reply; 22+ messages in thread
From: Stephen Boyd @ 2018-12-11 19:29 UTC (permalink / raw)
To: linux-clk, Aisheng Dong
Cc: linux-arm-kernel, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel
Quoting Aisheng Dong (2018-12-10 18:36:29)
> > -----Original Message-----
> > From: Stephen Boyd [mailto:sboyd@kernel.org]
> > Sent: Tuesday, December 11, 2018 4:55 AM
> [...]
> > Subject: Re: [PATCH V9 1/7] clk: imx: add configuration option for mmio clks
> >
> > Quoting Aisheng DONG (2018-12-04 06:39:22)
> > > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> > > index c12a05c..303082c 100644
> > > --- a/arch/arm/mach-imx/Kconfig
> > > +++ b/arch/arm/mach-imx/Kconfig
> > > @@ -570,6 +580,7 @@ config SOC_IMX7ULP config SOC_VF610
> > > bool "Vybrid Family VF610 support"
> > > select ARM_GIC if ARCH_MULTI_V7
> > > + select MXC_CLK
> > > select PINCTRL_VF610
> > >
> >
> > Instead of select can we break this dependency on the arch Kconfig and
> > have:
> >
> > config MXC_CLK
> > def_bool ARCH_MXC && !ARM64
> >
>
> Thanks for the suggestion.
> One little problem is that we also have LS1021 supported under ARCH_MXC which
> does not use MXC_CLK.
Ok. So then your change is also limiting the compilation of
drivers/clk/imx/ to only the platforms that select it now, instead of
all ARCH_MXC like it was done before.
We can also have def_bool <big list of SoC platforms> if that helps for
the optimization that this patch is making.
arm-soc has generally pushed against having so many different arch level
Kconfig options because they make for unwieldy Kconfig fragments that
may become conflicting. Instead, the options for the different SoCs are
removed and we just have one for the platform and rely on defconfigs to
pick the right drivers.
Why can't we do that here?
>
> > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index
> > > 5c0b11e..f850424 100644
> > > --- a/drivers/clk/imx/Makefile
> > > +++ b/drivers/clk/imx/Makefile
> > > @@ -1,6 +1,6 @@
> > > # SPDX-License-Identifier: GPL-2.0
> > >
> > > -obj-y += \
> > > +obj-$(CONFIG_MXC_CLK) += \
> >
> > Because this changes to obj-$(CONFIG) we should change the
> > drivers/clk/Makefile to have obj-y for this Makefile instead of depending on
> > ARCH_MXC.
>
> We also use ARCH_MXC for ARMv8 SoC clocks.
Yes, and? I'm suggesting drivers/clk/Makefile have an obj-y +=
drivers/clk/imx/ and then decide to compile or not compile the MXC_CLK
"core" bits based on CONFIG_MXC_CLK config option.
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V9 1/7] clk: imx: add configuration option for mmio clks
2018-12-11 19:29 ` Stephen Boyd
@ 2018-12-12 1:09 ` Aisheng Dong
2018-12-12 10:27 ` Aisheng Dong
0 siblings, 1 reply; 22+ messages in thread
From: Aisheng Dong @ 2018-12-12 1:09 UTC (permalink / raw)
To: Stephen Boyd, linux-clk
Cc: linux-arm-kernel, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel
> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd@kernel.org]
> Quoting Aisheng Dong (2018-12-10 18:36:29)
> > > -----Original Message-----
> > > From: Stephen Boyd [mailto:sboyd@kernel.org]
> > > Sent: Tuesday, December 11, 2018 4:55 AM
> > [...]
> > > Subject: Re: [PATCH V9 1/7] clk: imx: add configuration option for
> > > mmio clks
> > >
> > > Quoting Aisheng DONG (2018-12-04 06:39:22)
> > > > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> > > > index c12a05c..303082c 100644
> > > > --- a/arch/arm/mach-imx/Kconfig
> > > > +++ b/arch/arm/mach-imx/Kconfig
> > > > @@ -570,6 +580,7 @@ config SOC_IMX7ULP config SOC_VF610
> > > > bool "Vybrid Family VF610 support"
> > > > select ARM_GIC if ARCH_MULTI_V7
> > > > + select MXC_CLK
> > > > select PINCTRL_VF610
> > > >
> > >
> > > Instead of select can we break this dependency on the arch Kconfig
> > > and
> > > have:
> > >
> > > config MXC_CLK
> > > def_bool ARCH_MXC && !ARM64
> > >
> >
> > Thanks for the suggestion.
> > One little problem is that we also have LS1021 supported under
> > ARCH_MXC which does not use MXC_CLK.
>
> Ok. So then your change is also limiting the compilation of drivers/clk/imx/ to
> only the platforms that select it now, instead of all ARCH_MXC like it was done
> before.
>
> We can also have def_bool <big list of SoC platforms> if that helps for the
> optimization that this patch is making.
>
> arm-soc has generally pushed against having so many different arch level
> Kconfig options because they make for unwieldy Kconfig fragments that may
> become conflicting. Instead, the options for the different SoCs are removed
> and we just have one for the platform and rely on defconfigs to pick the right
> drivers.
>
Thanks for telling the detailed background. Very clear now.
> Why can't we do that here?
>
> >
> > > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> > > > index
> > > > 5c0b11e..f850424 100644
> > > > --- a/drivers/clk/imx/Makefile
> > > > +++ b/drivers/clk/imx/Makefile
> > > > @@ -1,6 +1,6 @@
> > > > # SPDX-License-Identifier: GPL-2.0
> > > >
> > > > -obj-y += \
> > > > +obj-$(CONFIG_MXC_CLK) += \
> > >
> > > Because this changes to obj-$(CONFIG) we should change the
> > > drivers/clk/Makefile to have obj-y for this Makefile instead of
> > > depending on ARCH_MXC.
> >
> > We also use ARCH_MXC for ARMv8 SoC clocks.
>
> Yes, and? I'm suggesting drivers/clk/Makefile have an obj-y += drivers/clk/imx/
> and then decide to compile or not compile the MXC_CLK "core" bits based on
> CONFIG_MXC_CLK config option.
Sorry for the missunderstanding before.
I guess you point is have an ojb-y += drivrs/clk/imx/
Then in drivers/clk/imx/Kconfig
config MXC_CLK
def_bool ARCH_MXC && !ARM64
select MXC_clk bits
config MXC_CLK_SCU
def_bool ARCH_MXC && ARM64
select SCU clock bits
If wrong please let me know.
Will update the patch series and re-send.
Thanks for the suggestion.
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V9 1/7] clk: imx: add configuration option for mmio clks
2018-12-12 1:09 ` Aisheng Dong
@ 2018-12-12 10:27 ` Aisheng Dong
2018-12-12 22:23 ` Stephen Boyd
0 siblings, 1 reply; 22+ messages in thread
From: Aisheng Dong @ 2018-12-12 10:27 UTC (permalink / raw)
To: Stephen Boyd, linux-clk
Cc: linux-arm-kernel, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel
Hi Stephen,
> > > > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> > > > > index
> > > > > 5c0b11e..f850424 100644
> > > > > --- a/drivers/clk/imx/Makefile
> > > > > +++ b/drivers/clk/imx/Makefile
> > > > > @@ -1,6 +1,6 @@
> > > > > # SPDX-License-Identifier: GPL-2.0
> > > > >
> > > > > -obj-y += \
> > > > > +obj-$(CONFIG_MXC_CLK) += \
> > > >
> > > > Because this changes to obj-$(CONFIG) we should change the
> > > > drivers/clk/Makefile to have obj-y for this Makefile instead of
> > > > depending on ARCH_MXC.
> > >
> > > We also use ARCH_MXC for ARMv8 SoC clocks.
> >
> > Yes, and? I'm suggesting drivers/clk/Makefile have an obj-y +=
> > drivers/clk/imx/ and then decide to compile or not compile the MXC_CLK
> > "core" bits based on CONFIG_MXC_CLK config option.
>
> Sorry for the missunderstanding before.
> I guess you point is have an ojb-y += drivrs/clk/imx/ Then in
> drivers/clk/imx/Kconfig config MXC_CLK
> def_bool ARCH_MXC && !ARM64
> select MXC_clk bits
> config MXC_CLK_SCU
> def_bool ARCH_MXC && ARM64
> select SCU clock bits
>
> If wrong please let me know.
>
> Will update the patch series and re-send.
> Thanks for the suggestion.
>
I tried and met another problem that MX8MQ (ARM64) is also
using legacy MXC_CLK. (And 3 more MX8M series based chips.)
That means I have to write something like:
config MXC_CLK
bool
def_bool (ARCH_MXC && !ARM64) || (ARCH_MXC && ARM64 && SOC_IMX8MQ)
config MXC_CLK_SCU
bool
def_bool (ARCH_MXC && ARM64 && !SOC_IMX8MQ)
But it can't work as ARM64 supports multiplatforms.
e.g. we have also SOC_IMX8QXP, SOC_IMX8QM, SOC_IMX8DM ...
Do you have a suggestion about this?
Regards
Dong Aisheng
> Regards
> Dong Aisheng
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V9 1/7] clk: imx: add configuration option for mmio clks
2018-12-12 10:27 ` Aisheng Dong
@ 2018-12-12 22:23 ` Stephen Boyd
2018-12-13 0:32 ` Aisheng Dong
0 siblings, 1 reply; 22+ messages in thread
From: Stephen Boyd @ 2018-12-12 22:23 UTC (permalink / raw)
To: linux-clk, Aisheng Dong
Cc: linux-arm-kernel, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel
Quoting Aisheng Dong (2018-12-12 02:27:24)
> Hi Stephen,
>
> > > > > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> > > > > > index
> > > > > > 5c0b11e..f850424 100644
> > > > > > --- a/drivers/clk/imx/Makefile
> > > > > > +++ b/drivers/clk/imx/Makefile
> > > > > > @@ -1,6 +1,6 @@
> > > > > > # SPDX-License-Identifier: GPL-2.0
> > > > > >
> > > > > > -obj-y += \
> > > > > > +obj-$(CONFIG_MXC_CLK) += \
> > > > >
> > > > > Because this changes to obj-$(CONFIG) we should change the
> > > > > drivers/clk/Makefile to have obj-y for this Makefile instead of
> > > > > depending on ARCH_MXC.
> > > >
> > > > We also use ARCH_MXC for ARMv8 SoC clocks.
> > >
> > > Yes, and? I'm suggesting drivers/clk/Makefile have an obj-y +=
> > > drivers/clk/imx/ and then decide to compile or not compile the MXC_CLK
> > > "core" bits based on CONFIG_MXC_CLK config option.
> >
> > Sorry for the missunderstanding before.
> > I guess you point is have an ojb-y += drivrs/clk/imx/ Then in
> > drivers/clk/imx/Kconfig config MXC_CLK
> > def_bool ARCH_MXC && !ARM64
> > select MXC_clk bits
> > config MXC_CLK_SCU
> > def_bool ARCH_MXC && ARM64
> > select SCU clock bits
> >
> > If wrong please let me know.
> >
> > Will update the patch series and re-send.
> > Thanks for the suggestion.
Yes that looks like what I'm asking for.
> >
>
> I tried and met another problem that MX8MQ (ARM64) is also
> using legacy MXC_CLK. (And 3 more MX8M series based chips.)
>
> That means I have to write something like:
> config MXC_CLK
> bool
> def_bool (ARCH_MXC && !ARM64) || (ARCH_MXC && ARM64 && SOC_IMX8MQ)
>
> config MXC_CLK_SCU
> bool
> def_bool (ARCH_MXC && ARM64 && !SOC_IMX8MQ)
>
> But it can't work as ARM64 supports multiplatforms.
> e.g. we have also SOC_IMX8QXP, SOC_IMX8QM, SOC_IMX8DM ...
>
> Do you have a suggestion about this?
>
Can you put the enabling of MXC_CLK_SCU in the defconfig and exposed it
as a user selectable option? And keep hiding the MXC_CLK option behind
the def_bool? I hope that MXC_CLK could be user selectable eventually,
but the def_bool is there to make it easier to bridge the transition and
update everyone's defconfigs while it is moved into the defconfig.
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V9 1/7] clk: imx: add configuration option for mmio clks
2018-12-12 22:23 ` Stephen Boyd
@ 2018-12-13 0:32 ` Aisheng Dong
0 siblings, 0 replies; 22+ messages in thread
From: Aisheng Dong @ 2018-12-13 0:32 UTC (permalink / raw)
To: Stephen Boyd, linux-clk
Cc: linux-arm-kernel, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel
> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd@kernel.org]
> Sent: Thursday, December 13, 2018 6:24 AM
> To: linux-clk@vger.kernel.org; Aisheng Dong <aisheng.dong@nxp.com>
> Cc: linux-arm-kernel@lists.infradead.org; mturquette@baylibre.com;
> shawnguo@kernel.org; Fabio Estevam <fabio.estevam@nxp.com>; dl-linux-imx
> <linux-imx@nxp.com>; kernel@pengutronix.de
> Subject: RE: [PATCH V9 1/7] clk: imx: add configuration option for mmio clks
>
> Quoting Aisheng Dong (2018-12-12 02:27:24)
> > Hi Stephen,
> >
> > > > > > > diff --git a/drivers/clk/imx/Makefile
> > > > > > > b/drivers/clk/imx/Makefile index
> > > > > > > 5c0b11e..f850424 100644
> > > > > > > --- a/drivers/clk/imx/Makefile
> > > > > > > +++ b/drivers/clk/imx/Makefile
> > > > > > > @@ -1,6 +1,6 @@
> > > > > > > # SPDX-License-Identifier: GPL-2.0
> > > > > > >
> > > > > > > -obj-y += \
> > > > > > > +obj-$(CONFIG_MXC_CLK) += \
> > > > > >
> > > > > > Because this changes to obj-$(CONFIG) we should change the
> > > > > > drivers/clk/Makefile to have obj-y for this Makefile instead
> > > > > > of depending on ARCH_MXC.
> > > > >
> > > > > We also use ARCH_MXC for ARMv8 SoC clocks.
> > > >
> > > > Yes, and? I'm suggesting drivers/clk/Makefile have an obj-y +=
> > > > drivers/clk/imx/ and then decide to compile or not compile the
> > > > MXC_CLK "core" bits based on CONFIG_MXC_CLK config option.
> > >
> > > Sorry for the missunderstanding before.
> > > I guess you point is have an ojb-y += drivrs/clk/imx/ Then in
> > > drivers/clk/imx/Kconfig config MXC_CLK
> > > def_bool ARCH_MXC && !ARM64
> > > select MXC_clk bits
> > > config MXC_CLK_SCU
> > > def_bool ARCH_MXC && ARM64
> > > select SCU clock bits
> > >
> > > If wrong please let me know.
> > >
> > > Will update the patch series and re-send.
> > > Thanks for the suggestion.
>
> Yes that looks like what I'm asking for.
>
> > >
> >
> > I tried and met another problem that MX8MQ (ARM64) is also using
> > legacy MXC_CLK. (And 3 more MX8M series based chips.)
> >
> > That means I have to write something like:
> > config MXC_CLK
> > bool
> > def_bool (ARCH_MXC && !ARM64) || (ARCH_MXC && ARM64 &&
> > SOC_IMX8MQ)
> >
> > config MXC_CLK_SCU
> > bool
> > def_bool (ARCH_MXC && ARM64 && !SOC_IMX8MQ)
> >
> > But it can't work as ARM64 supports multiplatforms.
> > e.g. we have also SOC_IMX8QXP, SOC_IMX8QM, SOC_IMX8DM ...
> >
> > Do you have a suggestion about this?
> >
>
> Can you put the enabling of MXC_CLK_SCU in the defconfig and exposed it as a
> user selectable option? And keep hiding the MXC_CLK option behind the
> def_bool? I hope that MXC_CLK could be user selectable eventually, but the
> def_bool is there to make it easier to bridge the transition and update
> everyone's defconfigs while it is moved into the defconfig.
Sounds like a good suggestion.
I will do it now.
In order to avoid breaking MX8MQ, I will keep MXC_CLK as
config MXC_CLK
bool
def_bool (ARCH_MXC && !ARM64) || (ARCH_MXC && ARM64 && SOC_IMX8MQ)
and make MXC_CLK_SCU a user selectable option.
And finally we will make MXC_CLK selectable as well after the transition.
If any issue please let me know.
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V9 2/7] clk: imx: add scu clock common part
2018-12-11 3:35 ` Aisheng Dong
@ 2018-12-17 10:27 ` Lothar Waßmann
2018-12-17 10:30 ` Aisheng Dong
0 siblings, 1 reply; 22+ messages in thread
From: Lothar Waßmann @ 2018-12-17 10:27 UTC (permalink / raw)
To: Aisheng Dong
Cc: Stephen Boyd, linux-clk, mturquette, dl-linux-imx, kernel,
Fabio Estevam, shawnguo, linux-arm-kernel
Hi,
On Tue, 11 Dec 2018 03:35:48 +0000 Aisheng Dong wrote:
> > -----Original Message-----
> > From: Stephen Boyd [mailto:sboyd@kernel.org]
> > Quoting Aisheng DONG (2018-12-04 06:39:25)
> > > diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index
> > > 43a3ecc..63e7b01 100644
> > > --- a/drivers/clk/imx/Kconfig
> > > +++ b/drivers/clk/imx/Kconfig
> > > @@ -3,3 +3,7 @@
> > > config MXC_CLK
> > > bool
> > > depends on ARCH_MXC
> > > +
> > > +config MXC_CLK_SCU
> >
> > Is there any reason to make this a hidden option instead of making it a
> > selectable option? It can still depend on ARCH_MXC and ARM64, but otherwise
> > it should be compilable as long as CONFIG_IMX_SCU is defined (this should
> > also be a config we depend on here).
> >
>
> This is mostly following the exist using that CLK is selected by SoC config option.
> https://patchwork.kernel.org/patch/10677309/
>
> As CLK usually is required for platform to run well, so we did not make it selectable.
>
> > > + bool
> > > + depends on ARCH_MXC && ARM64
> > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index
> > > f850424..4abed37 100644
> > > --- a/drivers/clk/imx/Makefile
> > > +++ b/drivers/clk/imx/Makefile
> > > @@ -20,6 +20,9 @@ obj-$(CONFIG_MXC_CLK) += \
> > > clk-pllv4.o \
> > > clk-sccg-pll.o
> > >
> > > +obj-$(CONFIG_MXC_CLK_SCU) += \
> > > + clk-scu.o
> > > +
> > > obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
> > > obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
> > > obj-$(CONFIG_SOC_IMX25) += clk-imx25.o diff --git
> > > a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c new file mode
> > > 100644 index 0000000..ec8a471
> > > --- /dev/null
> > > +++ b/drivers/clk/imx/clk-scu.c
> > > @@ -0,0 +1,265 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright 2018 NXP
> > > + * Dong Aisheng <aisheng.dong@nxp.com>
> > > + */
> > > +
> > > +#include <linux/clk-provider.h>
> > > +#include <linux/err.h>
> > > +#include <linux/slab.h>
> > > +
> > > +#include "clk-scu.h"
> > > +
> > > +struct imx_sc_ipc *ccm_ipc_handle;
> >
> > Why does this need to be a global? Can it be in each clk_scu instance instead?
> >
>
> No, no need to be in each clk_scu instance.
> There's only one handler.
>
Shouldn't it be 'static'?
Lothar Waßmann
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH V9 2/7] clk: imx: add scu clock common part
2018-12-17 10:27 ` Lothar Waßmann
@ 2018-12-17 10:30 ` Aisheng Dong
0 siblings, 0 replies; 22+ messages in thread
From: Aisheng Dong @ 2018-12-17 10:30 UTC (permalink / raw)
To: Lothar Waßmann
Cc: Stephen Boyd, linux-clk, mturquette, dl-linux-imx, kernel,
Fabio Estevam, shawnguo, linux-arm-kernel
[...]
> > > > +#include "clk-scu.h"
> > > > +
> > > > +struct imx_sc_ipc *ccm_ipc_handle;
> > >
> > > Why does this need to be a global? Can it be in each clk_scu instance
> instead?
> > >
> >
> > No, no need to be in each clk_scu instance.
> > There's only one handler.
> >
> Shouldn't it be 'static'?
>
This has been fixed in CLK tree.
Regards
Dong Aisheng
>
> Lothar Waßmann
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2018-12-17 10:38 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-12-04 14:39 [PATCH V9 0/7] clk: imx: add imx8qxp clock support Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 1/7] clk: imx: add configuration option for mmio clks Aisheng DONG
2018-12-10 20:55 ` Stephen Boyd
2018-12-11 2:36 ` Aisheng Dong
2018-12-11 19:29 ` Stephen Boyd
2018-12-12 1:09 ` Aisheng Dong
2018-12-12 10:27 ` Aisheng Dong
2018-12-12 22:23 ` Stephen Boyd
2018-12-13 0:32 ` Aisheng Dong
2018-12-04 14:39 ` [PATCH V9 2/7] clk: imx: add scu clock common part Aisheng DONG
2018-12-10 21:56 ` Stephen Boyd
2018-12-11 3:35 ` Aisheng Dong
2018-12-17 10:27 ` Lothar Waßmann
2018-12-17 10:30 ` Aisheng Dong
2018-12-04 14:39 ` [PATCH V9 3/7] dt-bindings: clock: imx8qxp: add SCU clock IDs Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 4/7] clk: imx: add imx8qxp clk driver Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 5/7] dt-bindings: clock: add imx8qxp lpcg clock binding Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 6/7] clk: imx: add lpcg clock support Aisheng DONG
2018-12-04 14:39 ` [PATCH V9 7/7] clk: imx: add imx8qxp lpcg driver Aisheng DONG
2018-12-10 20:46 ` [PATCH V9 0/7] clk: imx: add imx8qxp clock support Stephen Boyd
2018-12-11 2:04 ` Aisheng Dong
2018-12-11 4:05 ` Aisheng Dong
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