* [PATCH] clk: imx6q: add DCICx clocks gate
@ 2018-11-30 6:31 Anson Huang
2018-12-10 19:34 ` Stephen Boyd
0 siblings, 1 reply; 2+ messages in thread
From: Anson Huang @ 2018-11-30 6:31 UTC (permalink / raw)
To: shawnguo, s.hauer, kernel, Fabio Estevam, mturquette, sboyd,
robh+dt, mark.rutland, clement.peron, colin.didier,
linux-arm-kernel, linux-clk, linux-kernel, devicetree
Cc: dl-linux-imx
On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks
gate in CCM_CCGR0 register, add them into clock tree for
clock management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
drivers/clk/imx/clk-imx6q.c | 2 ++
include/dt-bindings/clock/imx6qdl-clock.h | 4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index bbe0c60..31a9d94 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -737,6 +737,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
+ clk[IMX6QDL_CLK_DCIC1] = imx_clk_gate2("dcic1", "ipu1_podf", base + 0x68, 24);
+ clk[IMX6QDL_CLK_DCIC2] = imx_clk_gate2("dcic2", "ipu2_podf", base + 0x68, 26);
clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 87b068f..b3cef29 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -274,6 +274,8 @@
#define IMX6QDL_CLK_EPIT1 261
#define IMX6QDL_CLK_EPIT2 262
#define IMX6QDL_CLK_MMDC_P0_IPG 263
-#define IMX6QDL_CLK_END 264
+#define IMX6QDL_CLK_DCIC1 264
+#define IMX6QDL_CLK_DCIC2 265
+#define IMX6QDL_CLK_END 266
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: imx6q: add DCICx clocks gate
2018-11-30 6:31 [PATCH] clk: imx6q: add DCICx clocks gate Anson Huang
@ 2018-12-10 19:34 ` Stephen Boyd
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Boyd @ 2018-12-10 19:34 UTC (permalink / raw)
To: clement.peron, colin.didier, devicetree, kernel,
linux-arm-kernel, linux-clk, linux-kernel, mark.rutland,
mturquette, robh+dt, s.hauer, shawnguo, Anson Huang,
Fabio Estevam
Cc: dl-linux-imx
Quoting Anson Huang (2018-11-29 22:31:40)
> On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks
> gate in CCM_CCGR0 register, add them into clock tree for
> clock management.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 2+ messages in thread
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