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From: Stephen Boyd <sboyd@kernel.org>
To: Dinh Nguyen <dinguyen@kernel.org>, linux-clk@vger.kernel.org
Cc: dinguyen@kernel.org, mturquette@baylibre.com,
	linux-stable@vger.kernel.org
Subject: Re: [PATCH] clk: socfpga: stratix10: fix rate calculation for pll clocks
Date: Fri, 11 Jan 2019 15:41:08 -0800	[thread overview]
Message-ID: <154725006827.169631.11387684968829410246@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20181218000614.30520-1-dinguyen@kernel.org>

Quoting Dinh Nguyen (2018-12-17 16:06:14)
> The main PLL calculation has a mistake. We should be using the
> multiplying the VCO frequency, not the parent clock frequency.
> 
> Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for
> Stratix10 platform")
> Cc: linux-stable@vger.kernel.org
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---

Applied to clk-fixes


      reply	other threads:[~2019-01-11 23:41 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-18  0:06 [PATCH] clk: socfpga: stratix10: fix rate calculation for pll clocks Dinh Nguyen
2019-01-11 23:41 ` Stephen Boyd [this message]

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