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* [PATCH] clk: socfpga: stratix10: fix rate calculation for pll clocks
@ 2018-12-18  0:06 Dinh Nguyen
  2019-01-11 23:41 ` Stephen Boyd
  0 siblings, 1 reply; 2+ messages in thread
From: Dinh Nguyen @ 2018-12-18  0:06 UTC (permalink / raw)
  To: linux-clk; +Cc: dinguyen, mturquette, sboyd, linux-stable

The main PLL calculation has a mistake. We should be using the
multiplying the VCO frequency, not the parent clock frequency.

Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 drivers/clk/socfpga/clk-pll-s10.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index 2d5d8b43727e..c4d0b6f6abf2 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -43,7 +43,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
 	/* Read mdiv and fdiv from the fdbck register */
 	reg = readl(socfpgaclk->hw.reg + 0x4);
 	mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
-	vco_freq = (unsigned long long)parent_rate * (mdiv + 6);
+	vco_freq = (unsigned long long)vco_freq * (mdiv + 6);
 
 	return (unsigned long)vco_freq;
 }
-- 
2.20.0


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] clk: socfpga: stratix10: fix rate calculation for pll clocks
  2018-12-18  0:06 [PATCH] clk: socfpga: stratix10: fix rate calculation for pll clocks Dinh Nguyen
@ 2019-01-11 23:41 ` Stephen Boyd
  0 siblings, 0 replies; 2+ messages in thread
From: Stephen Boyd @ 2019-01-11 23:41 UTC (permalink / raw)
  To: Dinh Nguyen, linux-clk; +Cc: dinguyen, mturquette, linux-stable

Quoting Dinh Nguyen (2018-12-17 16:06:14)
> The main PLL calculation has a mistake. We should be using the
> multiplying the VCO frequency, not the parent clock frequency.
> 
> Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for
> Stratix10 platform")
> Cc: linux-stable@vger.kernel.org
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---

Applied to clk-fixes


^ permalink raw reply	[flat|nested] 2+ messages in thread

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2018-12-18  0:06 [PATCH] clk: socfpga: stratix10: fix rate calculation for pll clocks Dinh Nguyen
2019-01-11 23:41 ` Stephen Boyd

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