From: Stephen Boyd <sboyd@kernel.org>
To: mtk14994 <wangyan.wang@mediatek.com>
Cc: CK Hu <ck.hu@mediatek.com>,
Michael Turquette <mturquette@baylibre.com>,
Ryder Lee <ryder.lee@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
srv_heupstream@mediatek.com,
chunhui dai <chunhui.dai@mediatek.com>,
David Airlie <airlied@linux.ie>,
Sean Wang <sean.wang@mediatek.com>,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
dri-devel@lists.freedesktop.org, Daniel Vetter <daniel@ffwll.ch>,
Matthias Brugger <matthias.bgg@gmail.com>,
Colin Ian King <colin.king@canonical.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V5 5/8] clk: mediatek: add MUX_GATE_FLAGS_2
Date: Thu, 21 Feb 2019 23:55:00 -0800 [thread overview]
Message-ID: <155082210099.77512.4042430864962937771@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1550716451.23876.5.camel@mszsdaap41>
Quoting mtk14994 (2019-02-20 18:34:11)
> Dear Stephen,
> > + unsigned char mux_flags;
> >
> > Why isn't it an unsigned long? Isn't this supposed to match the
> > frameworks version of the clk flags?
>
> ----> it is unsigned char mux_flags ,becasuse struct clk_mux {
>
> ....
> ....
> u8 flags;
> ....
> }
>
> it is matched when use " mux->flags = mc->mux_flags;"
>
Please try to not top-post.
Ok I thought it was the generic clk flags, not the mux specific flag
bits. Sounds fine then, but I would sort of expect it to match the type
in clk_mux then, i.e. be a u8 instead of an unsigned char (yes it's the
same in the end but it looks different at a glance).
next prev parent reply other threads:[~2019-02-22 7:55 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-20 2:53 [PATCH V5 0/8] make mt7623 clock of hdmi stable wangyan wang
2019-02-20 2:53 ` [PATCH v5 1/8] drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware wangyan wang
2019-02-20 2:53 ` [PATCH V5 2/8] drm/mediatek: move the setting of fixed divider wangyan wang
2019-02-20 2:53 ` [PATCH V5 3/8] drm/mediatek: using different flags of clk for HDMI phy wangyan wang
2019-02-20 2:53 ` [PATCH V5 4/8] drm/mediatek: fix the rate and divder of hdmi phy for MT2701 wangyan wang
2019-02-20 2:53 ` [PATCH V5 5/8] clk: mediatek: add MUX_GATE_FLAGS_2 wangyan wang
2019-02-20 19:37 ` Stephen Boyd
2019-02-21 2:34 ` mtk14994
2019-02-22 7:55 ` Stephen Boyd [this message]
2019-02-20 2:53 ` [PATCH V5 6/8] clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel wangyan wang
2019-02-20 2:53 ` [PATCH V5 7/8] drm/mediatek: using new factor for tvdpll in MT2701 wangyan wang
2019-02-20 2:53 ` [PATCH V5 8/8] drm/mediatek: fix the rate of parent for hdmi phy " wangyan wang
2019-02-20 3:07 ` [PATCH V5 0/8] make mt7623 clock of hdmi stable Ryder Lee
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