From: Stephen Boyd <sboyd@kernel.org>
To: Weiyi Lu <weiyi.lu@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh@kernel.org>,
Stephen Boyd <sboyd@codeaurora.org>,
James Liao <jamesjj.liao@mediatek.com>,
Fan Chen <fan.chen@mediatek.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-clk@vger.kernel.org, srv_heupstream@mediatek.com,
stable@vger.kernel.org
Subject: Re: [PATCH v4 00/12] Mediatek MT8183 clock and scpsys support
Date: Tue, 26 Feb 2019 09:45:54 -0800 [thread overview]
Message-ID: <155120315465.260864.9490825097795511702@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1551153650.1047.4.camel@mtksdaap41>
Quoting Weiyi Lu (2019-02-25 20:00:50)
> On Thu, 2019-02-21 at 23:48 -0800, Stephen Boyd wrote:
> > Quoting Matthias Brugger (2019-02-21 00:36:24)
> > >
> > >
> > > On 20/02/2019 20:18, Stephen Boyd wrote:
> > > >
> > > > What's the merge plan here? Do you want me to apply these patches to clk
> > > > tree? Will someone be sending me a pull request for mediatek clk changes
> > > > this cycle? It's getting pretty late for much of anything making this
> > > > upcoming merge window.
> > > >
> > >
> > > As far as I can see, the clock patches are independent, so I think it is OK to
> > > take them. SCPSYS patches will go through my tree once they are in shape.
> >
> > Ok great. When patches for clks are interspersed throughout the patch
> > series it makes me think that something later in the series depends on
> > something that isn't a clk patch so then I can't apply it.
> >
>
> Hi Stephen,
>
> Sorry for making such complex dependencies between the clk patches and
> others in this series. And just like Matthias mentioned, the clock
> patches are independent from others. I could resend a clock-only series
> right away if each clock patch in v4 is qualified to merge into
> clk-next.
> If there still some provide need to be fixed, please let me know. I'll
> fix them and send v5 only for clock.
It looks like Matthias has some comments on the first patch that need to
be addressed. I looked over the rest of the clk patches and they look ok
at a quick glance. If you resend just the clk patches without the rest
then I can probably apply them for the upcoming merge window.
next prev parent reply other threads:[~2019-02-26 17:46 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-01 8:30 [PATCH v4 00/12] Mediatek MT8183 clock and scpsys support Weiyi Lu
2019-02-01 8:30 ` Weiyi Lu
2019-02-20 19:18 ` Stephen Boyd
2019-02-21 8:36 ` Matthias Brugger
2019-02-22 7:48 ` Stephen Boyd
2019-02-26 4:00 ` Weiyi Lu
2019-02-26 17:45 ` Stephen Boyd [this message]
2019-02-01 8:30 ` [PATCH v4 01/12] clk: mediatek: Disable tuner_en before change PLL rate Weiyi Lu
2019-02-26 15:59 ` Matthias Brugger
2019-02-27 3:51 ` Weiyi Lu
2019-02-27 4:39 ` Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 02/12] clk: mediatek: add new clkmux register API Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 03/12] clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 04/12] soc: mediatek: add new flow for mtcmos power Weiyi Lu
2019-02-08 18:30 ` Matthias Brugger
2019-02-01 8:30 ` [PATCH v4 05/12] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 06/12] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 07/12] clk: mediatek: Add flags support for mtk_gate data Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 08/12] clk: mediatek: Add MT8183 clock support Weiyi Lu
2019-02-26 17:50 ` Stephen Boyd
2019-02-27 2:51 ` Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 09/12] dt-bindings: soc: fix typo of MT8173 power dt-bindings Weiyi Lu
2019-02-07 15:35 ` Matthias Brugger
2019-02-01 8:30 ` [PATCH v4 10/12] dt-bindings: soc: Add MT8183 " Weiyi Lu
2019-02-08 18:33 ` Matthias Brugger
2019-02-01 8:30 ` [PATCH v4 11/12] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2019-02-01 8:30 ` [PATCH v4 12/12] clk: mediatek: Allow changing PLL rate when it is off Weiyi Lu
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