* [PATCH V2] clk: imx: imx8mq: fix sys3_pll_out_sels
@ 2019-10-28 3:08 Peng Fan
2019-11-04 1:11 ` Shawn Guo
0 siblings, 1 reply; 2+ messages in thread
From: Peng Fan @ 2019-10-28 3:08 UTC (permalink / raw)
To: mturquette, sboyd, shawnguo, s.hauer, festevam, Abel Vesa
Cc: kernel, dl-linux-imx, Anson Huang, Jacky Bai, linux-clk,
linux-arm-kernel, linux-kernel, Leonard Crestez, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent.
According to the current imx_clk_sccg_pll design, it uses both
bypass1/2, however set bypass2 as 1 is not correct, because it will
make sys[x]_pll_out use wrong parent and might access wrong registers.
So correct bypass2 to 0 and fix sys3_pll_out_sels.
Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
V2:
Rebased on Shawn's clk/imx tree to avoid conflicts
drivers/clk/imx/clk-imx8mq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 4a5dbc4366a5..5f10a606d836 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -34,7 +34,7 @@ static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_
static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
-static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", "sys2_pll1_ref_sel", };
+static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", };
static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", };
static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", };
@@ -342,7 +342,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_fixed("sys1_pll_out", 800000000);
clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_fixed("sys2_pll_out", 1000000000);
- clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITICAL);
+ clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, base + 0x48, CLK_IS_CRITICAL);
clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL);
clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_sccg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);
--
2.16.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH V2] clk: imx: imx8mq: fix sys3_pll_out_sels
2019-10-28 3:08 [PATCH V2] clk: imx: imx8mq: fix sys3_pll_out_sels Peng Fan
@ 2019-11-04 1:11 ` Shawn Guo
0 siblings, 0 replies; 2+ messages in thread
From: Shawn Guo @ 2019-11-04 1:11 UTC (permalink / raw)
To: Peng Fan
Cc: mturquette, sboyd, s.hauer, festevam, Abel Vesa, kernel,
dl-linux-imx, Anson Huang, Jacky Bai, linux-clk,
linux-arm-kernel, linux-kernel, Leonard Crestez
On Mon, Oct 28, 2019 at 03:08:34AM +0000, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent.
>
> According to the current imx_clk_sccg_pll design, it uses both
> bypass1/2, however set bypass2 as 1 is not correct, because it will
> make sys[x]_pll_out use wrong parent and might access wrong registers.
>
> So correct bypass2 to 0 and fix sys3_pll_out_sels.
>
> Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk")
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied, thanks.
^ permalink raw reply [flat|nested] 2+ messages in thread
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