* [PATCH RESEND v3 01/15] arm64: dts: imx8qxp: add fallback compatible string for scu pd
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 02/15] arm64: dts: imx8qxp: move scu pd node before scu clock node Dong Aisheng
` (14 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng, Rob Herring, Mark Rutland, devicetree
According to binding doc, add the fallback compatible string for
scu pd.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2: new patch
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 9646a41e0532..dc3d408d091a 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -171,7 +171,7 @@
};
pd: imx8qx-pd {
- compatible = "fsl,imx8qxp-scu-pd";
+ compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
};
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 02/15] arm64: dts: imx8qxp: move scu pd node before scu clock node
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 01/15] arm64: dts: imx8qxp: add fallback compatible string for scu pd Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 03/15] arm64: dts: imx8qxp: orginize dts in subsystems Dong Aisheng
` (13 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng, Rob Herring, Mark Rutland, devicetree
SCU clock depends on SCU Power domain. So let's move scu pd node
before scu clock to make it probe earlier.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2: new patch
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index dc3d408d091a..c716b7b81b36 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -153,6 +153,11 @@
&lsio_mu1 1 3
&lsio_mu1 3 3>;
+ pd: imx8qx-pd {
+ compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
+ #power-domain-cells = <1>;
+ };
+
clk: clock-controller {
compatible = "fsl,imx8qxp-clk";
#clock-cells = <1>;
@@ -170,11 +175,6 @@
#size-cells = <1>;
};
- pd: imx8qx-pd {
- compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
- #power-domain-cells = <1>;
- };
-
scu_key: scu-key {
compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
linux,keycodes = <KEY_POWER>;
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 03/15] arm64: dts: imx8qxp: orginize dts in subsystems
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 01/15] arm64: dts: imx8qxp: add fallback compatible string for scu pd Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 02/15] arm64: dts: imx8qxp: move scu pd node before scu clock node Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 04/15] arm64: dts: imx8: add lsio lpcg clocks Dong Aisheng
` (12 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng, Rob Herring, Mark Rutland, devicetree
MX8 SoC is comprised of a few HW subsystems while some of them can be
reused in the different SoCs. So let's re-orginize them into subsystems
in device tree as well for the possible reuse of the common part.
Note, as there's still no devices of hsio subsys, so removed it
first instead of creating a subsys headfile with no devices.
They will be added back when new devices added.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v3:
* no changes except rebase
---
.../boot/dts/freescale/imx8-ss-adma.dtsi | 130 ++++++
.../boot/dts/freescale/imx8-ss-conn.dtsi | 89 ++++
.../arm64/boot/dts/freescale/imx8-ss-ddr.dtsi | 19 +
.../boot/dts/freescale/imx8-ss-lsio.dtsi | 138 ++++++
.../boot/dts/freescale/imx8qxp-ss-adma.dtsi | 41 ++
.../boot/dts/freescale/imx8qxp-ss-conn.dtsi | 25 ++
.../boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 65 +++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 396 +-----------------
8 files changed, 517 insertions(+), 386 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
new file mode 100644
index 000000000000..28b8fc9a81d4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+adma_subsys: bus@59000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x59000000 0x0 0x59000000 0x2000000>;
+
+ adma_lpcg: clock-controller@59000000 {
+ reg = <0x59000000 0x2000000>;
+ #clock-cells = <1>;
+ };
+
+ adma_dsp: dsp@596e8000 {
+ compatible = "fsl,imx8qxp-dsp";
+ reg = <0x596e8000 0x88000>;
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
+ clock-names = "ipg", "ocram", "core";
+ power-domains = <&pd IMX_SC_R_MU_13A>,
+ <&pd IMX_SC_R_MU_13B>,
+ <&pd IMX_SC_R_DSP>,
+ <&pd IMX_SC_R_DSP_RAM>;
+ mbox-names = "txdb0", "txdb1",
+ "rxdb0", "rxdb1";
+ mboxes = <&lsio_mu13 2 0>,
+ <&lsio_mu13 2 1>,
+ <&lsio_mu13 3 0>,
+ <&lsio_mu13 3 1>;
+ memory-region = <&dsp_reserved>;
+ status = "disabled";
+ };
+
+ adma_lpuart0: serial@5a060000 {
+ reg = <0x5a060000 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
+ clock-names = "ipg", "baud";
+ power-domains = <&pd IMX_SC_R_UART_0>;
+ status = "disabled";
+ };
+
+ adma_lpuart1: serial@5a070000 {
+ reg = <0x5a070000 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
+ clock-names = "ipg", "baud";
+ power-domains = <&pd IMX_SC_R_UART_1>;
+ status = "disabled";
+ };
+
+ adma_lpuart2: serial@5a080000 {
+ reg = <0x5a080000 0x1000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
+ clock-names = "ipg", "baud";
+ power-domains = <&pd IMX_SC_R_UART_2>;
+ status = "disabled";
+ };
+
+ adma_lpuart3: serial@5a090000 {
+ reg = <0x5a090000 0x1000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
+ clock-names = "ipg", "baud";
+ power-domains = <&pd IMX_SC_R_UART_3>;
+ status = "disabled";
+ };
+
+ adma_i2c0: i2c@5a800000 {
+ reg = <0x5a800000 0x4000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
+ clock-names = "per";
+ assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_0>;
+ status = "disabled";
+ };
+
+ adma_i2c1: i2c@5a810000 {
+ reg = <0x5a810000 0x4000>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
+ clock-names = "per";
+ assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_1>;
+ status = "disabled";
+ };
+
+ adma_i2c2: i2c@5a820000 {
+ reg = <0x5a820000 0x4000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
+ clock-names = "per";
+ assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_2>;
+ status = "disabled";
+ };
+
+ adma_i2c3: i2c@5a830000 {
+ reg = <0x5a830000 0x4000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
+ clock-names = "per";
+ assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_3>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
new file mode 100644
index 000000000000..5cf357fb85ae
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+conn_subsys: bus@5b000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
+
+ conn_lpcg: clock-controller@5b200000 {
+ reg = <0x5b200000 0xb0000>;
+ #clock-cells = <1>;
+ };
+
+ usdhc1: mmc@5b010000 {
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x5b010000 0x10000>;
+ clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
+ <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
+ <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
+ clock-names = "ipg", "per", "ahb";
+ power-domains = <&pd IMX_SC_R_SDHC_0>;
+ status = "disabled";
+ };
+
+ usdhc2: mmc@5b020000 {
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x5b020000 0x10000>;
+ clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
+ <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
+ <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
+ clock-names = "ipg", "per", "ahb";
+ power-domains = <&pd IMX_SC_R_SDHC_1>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc3: mmc@5b030000 {
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x5b030000 0x10000>;
+ clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
+ <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
+ <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
+ clock-names = "ipg", "per", "ahb";
+ power-domains = <&pd IMX_SC_R_SDHC_2>;
+ status = "disabled";
+ };
+
+ fec1: ethernet@5b040000 {
+ reg = <0x5b040000 0x10000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
+ <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
+ <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
+ <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
+ clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ power-domains = <&pd IMX_SC_R_ENET_0>;
+ status = "disabled";
+ };
+
+ fec2: ethernet@5b050000 {
+ reg = <0x5b050000 0x10000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
+ <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
+ <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
+ <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
+ clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ power-domains = <&pd IMX_SC_R_ENET_1>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi
new file mode 100644
index 000000000000..5ad2a31f0d90
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+ddr_subsys: bus@5c000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
+
+ ddr-pmu@5c020000 {
+ compatible = "fsl,imx8-ddr-pmu";
+ reg = <0x5c020000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
new file mode 100644
index 000000000000..00eaadbdcc0a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+lsio_subsys: bus@5d000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
+
+ lsio_gpio0: gpio@5d080000 {
+ reg = <0x5d080000 0x10000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_0>;
+ };
+
+ lsio_gpio1: gpio@5d090000 {
+ reg = <0x5d090000 0x10000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_1>;
+ };
+
+ lsio_gpio2: gpio@5d0a0000 {
+ reg = <0x5d0a0000 0x10000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_2>;
+ };
+
+ lsio_gpio3: gpio@5d0b0000 {
+ reg = <0x5d0b0000 0x10000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_3>;
+ };
+
+ lsio_gpio4: gpio@5d0c0000 {
+ reg = <0x5d0c0000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_4>;
+ };
+
+ lsio_gpio5: gpio@5d0d0000 {
+ reg = <0x5d0d0000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_5>;
+ };
+
+ lsio_gpio6: gpio@5d0e0000 {
+ reg = <0x5d0e0000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_6>;
+ };
+
+ lsio_gpio7: gpio@5d0f0000 {
+ reg = <0x5d0f0000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd IMX_SC_R_GPIO_7>;
+ };
+
+ lsio_mu0: mailbox@5d1b0000 {
+ reg = <0x5d1b0000 0x10000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ lsio_mu1: mailbox@5d1c0000 {
+ reg = <0x5d1c0000 0x10000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ lsio_mu2: mailbox@5d1d0000 {
+ reg = <0x5d1d0000 0x10000>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ lsio_mu3: mailbox@5d1e0000 {
+ reg = <0x5d1e0000 0x10000>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ lsio_mu4: mailbox@5d1f0000 {
+ reg = <0x5d1f0000 0x10000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ lsio_mu13: mailbox@5d280000 {
+ reg = <0x5d280000 0x10000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_MU_13A>;
+ };
+
+ lsio_lpcg: clock-controller@5d400000 {
+ reg = <0x5d400000 0x400000>;
+ #clock-cells = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
new file mode 100644
index 000000000000..5809324de8df
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&adma_lpcg {
+ compatible = "fsl,imx8qxp-lpcg-adma";
+};
+
+&adma_lpuart0 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+};
+
+&adma_lpuart1 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+};
+
+&adma_lpuart2 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+};
+
+&adma_lpuart3 {
+ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+};
+
+&adma_i2c0 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&adma_i2c1 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&adma_i2c2 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&adma_i2c3 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
new file mode 100644
index 000000000000..ea0cd518680b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&conn_lpcg {
+ compatible = "fsl,imx8qxp-lpcg-conn";
+};
+
+&usdhc1 {
+ compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
+};
+
+&usdhc2 {
+ compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
+};
+
+&fec1 {
+ compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
+};
+
+&fec2 {
+ compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
new file mode 100644
index 000000000000..b02ae5df597f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&lsio_gpio0 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio1 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio2 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio3 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio4 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio5 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio6 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio7 {
+ compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_mu0 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu1 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu2 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu3 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu4 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu13 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_lpcg {
+ compatible = "fsl,imx8qxp-lpcg-lsio";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index c716b7b81b36..e408d214943f 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
@@ -213,389 +213,13 @@
clock-output-names = "xtal_24MHz";
};
- adma_subsys: bus@59000000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x59000000 0x0 0x59000000 0x2000000>;
-
- adma_lpcg: clock-controller@59000000 {
- compatible = "fsl,imx8qxp-lpcg-adma";
- reg = <0x59000000 0x2000000>;
- #clock-cells = <1>;
- };
-
- adma_dsp: dsp@596e8000 {
- compatible = "fsl,imx8qxp-dsp";
- reg = <0x596e8000 0x88000>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
- clock-names = "ipg", "ocram", "core";
- power-domains = <&pd IMX_SC_R_MU_13A>,
- <&pd IMX_SC_R_MU_13B>,
- <&pd IMX_SC_R_DSP>,
- <&pd IMX_SC_R_DSP_RAM>;
- mbox-names = "txdb0", "txdb1",
- "rxdb0", "rxdb1";
- mboxes = <&lsio_mu13 2 0>,
- <&lsio_mu13 2 1>,
- <&lsio_mu13 3 0>,
- <&lsio_mu13 3 1>;
- memory-region = <&dsp_reserved>;
- status = "disabled";
- };
-
- adma_lpuart0: serial@5a060000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x5a060000 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
- clock-names = "ipg", "baud";
- power-domains = <&pd IMX_SC_R_UART_0>;
- status = "disabled";
- };
-
- adma_lpuart1: serial@5a070000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x5a070000 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
- clock-names = "ipg", "baud";
- power-domains = <&pd IMX_SC_R_UART_1>;
- status = "disabled";
- };
-
- adma_lpuart2: serial@5a080000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x5a080000 0x1000>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
- clock-names = "ipg", "baud";
- power-domains = <&pd IMX_SC_R_UART_2>;
- status = "disabled";
- };
-
- adma_lpuart3: serial@5a090000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x5a090000 0x1000>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
- clock-names = "ipg", "baud";
- power-domains = <&pd IMX_SC_R_UART_3>;
- status = "disabled";
- };
-
- adma_i2c0: i2c@5a800000 {
- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x5a800000 0x4000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
- clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
- assigned-clock-rates = <24000000>;
- power-domains = <&pd IMX_SC_R_I2C_0>;
- status = "disabled";
- };
-
- adma_i2c1: i2c@5a810000 {
- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x5a810000 0x4000>;
- interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
- clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
- assigned-clock-rates = <24000000>;
- power-domains = <&pd IMX_SC_R_I2C_1>;
- status = "disabled";
- };
-
- adma_i2c2: i2c@5a820000 {
- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x5a820000 0x4000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
- clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
- assigned-clock-rates = <24000000>;
- power-domains = <&pd IMX_SC_R_I2C_2>;
- status = "disabled";
- };
-
- adma_i2c3: i2c@5a830000 {
- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x5a830000 0x4000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
- clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
- assigned-clock-rates = <24000000>;
- power-domains = <&pd IMX_SC_R_I2C_3>;
- status = "disabled";
- };
- };
-
- conn_subsys: bus@5b000000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
-
- conn_lpcg: clock-controller@5b200000 {
- compatible = "fsl,imx8qxp-lpcg-conn";
- reg = <0x5b200000 0xb0000>;
- #clock-cells = <1>;
- };
-
- usdhc1: mmc@5b010000 {
- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x5b010000 0x10000>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
- clock-names = "ipg", "per", "ahb";
- power-domains = <&pd IMX_SC_R_SDHC_0>;
- status = "disabled";
- };
-
- usdhc2: mmc@5b020000 {
- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x5b020000 0x10000>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
- clock-names = "ipg", "per", "ahb";
- power-domains = <&pd IMX_SC_R_SDHC_1>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
- status = "disabled";
- };
-
- usdhc3: mmc@5b030000 {
- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x5b030000 0x10000>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
- clock-names = "ipg", "per", "ahb";
- power-domains = <&pd IMX_SC_R_SDHC_2>;
- status = "disabled";
- };
-
- fec1: ethernet@5b040000 {
- compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
- reg = <0x5b040000 0x10000>;
- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
- clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
- fsl,num-tx-queues=<3>;
- fsl,num-rx-queues=<3>;
- power-domains = <&pd IMX_SC_R_ENET_0>;
- status = "disabled";
- };
-
- fec2: ethernet@5b050000 {
- compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
- reg = <0x5b050000 0x10000>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
- clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
- fsl,num-tx-queues=<3>;
- fsl,num-rx-queues=<3>;
- power-domains = <&pd IMX_SC_R_ENET_1>;
- status = "disabled";
- };
- };
-
- ddr_subsyss: bus@5c000000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
-
- ddr-pmu@5c020000 {
- compatible = "fsl,imx8-ddr-pmu";
- reg = <0x5c020000 0x10000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- lsio_subsys: bus@5d000000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
-
- lsio_gpio0: gpio@5d080000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d080000 0x10000>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_0>;
- };
-
- lsio_gpio1: gpio@5d090000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d090000 0x10000>;
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_1>;
- };
-
- lsio_gpio2: gpio@5d0a0000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d0a0000 0x10000>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_2>;
- };
-
- lsio_gpio3: gpio@5d0b0000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d0b0000 0x10000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_3>;
- };
-
- lsio_gpio4: gpio@5d0c0000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d0c0000 0x10000>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_4>;
- };
-
- lsio_gpio5: gpio@5d0d0000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d0d0000 0x10000>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_5>;
- };
-
- lsio_gpio6: gpio@5d0e0000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d0e0000 0x10000>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_6>;
- };
-
- lsio_gpio7: gpio@5d0f0000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d0f0000 0x10000>;
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_7>;
- };
-
- lsio_mu0: mailbox@5d1b0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
- reg = <0x5d1b0000 0x10000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- status = "disabled";
- };
-
- lsio_mu1: mailbox@5d1c0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
- reg = <0x5d1c0000 0x10000>;
- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- };
-
- lsio_mu2: mailbox@5d1d0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
- reg = <0x5d1d0000 0x10000>;
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- status = "disabled";
- };
-
- lsio_mu3: mailbox@5d1e0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
- reg = <0x5d1e0000 0x10000>;
- interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- status = "disabled";
- };
-
- lsio_mu4: mailbox@5d1f0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
- reg = <0x5d1f0000 0x10000>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- status = "disabled";
- };
-
- lsio_mu13: mailbox@5d280000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
- reg = <0x5d280000 0x10000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- power-domains = <&pd IMX_SC_R_MU_13A>;
- };
-
- lsio_lpcg: clock-controller@5d400000 {
- compatible = "fsl,imx8qxp-lpcg-lsio";
- reg = <0x5d400000 0x400000>;
- #clock-cells = <1>;
- };
- };
+ /* sorted in register address */
+ #include "imx8-ss-adma.dtsi"
+ #include "imx8-ss-conn.dtsi"
+ #include "imx8-ss-ddr.dtsi"
+ #include "imx8-ss-lsio.dtsi"
};
+
+#include "imx8qxp-ss-adma.dtsi"
+#include "imx8qxp-ss-conn.dtsi"
+#include "imx8qxp-ss-lsio.dtsi"
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 04/15] arm64: dts: imx8: add lsio lpcg clocks
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (2 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 03/15] arm64: dts: imx8qxp: orginize dts in subsystems Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 05/15] arm64: dts: imx8: add conn " Dong Aisheng
` (11 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng, Rob Herring, Mark Rutland, devicetree
Add lsio lpcg clocks
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* update to use clock-indices property instead of bit-offset property
v1->v2:
* Use old SCU clock binding temporarily to avoid build warning due to SCU
clock cell will be changed to 2.
* add power domain property
---
.../boot/dts/freescale/imx8-ss-lsio.dtsi | 156 +++++++++++++++++-
1 file changed, 155 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index 00eaadbdcc0a..e839aa8ab586 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -4,12 +4,29 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
+#include <dt-bindings/clock/imx8-lpcg.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+
lsio_subsys: bus@5d000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
+ lsio_mem_clk: clock-lsio-mem {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lsio_mem_clk";
+ };
+
+ lsio_bus_clk: clock-lsio-bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "lsio_bus_clk";
+ };
+
lsio_gpio0: gpio@5d080000 {
reg = <0x5d080000 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
@@ -131,8 +148,145 @@ lsio_subsys: bus@5d000000 {
power-domains = <&pd IMX_SC_R_MU_13A>;
};
- lsio_lpcg: clock-controller@5d400000 {
+ /* LPCG clocks */
+ lsio_lpcg: clock-controller-legacy@5d400000 {
reg = <0x5d400000 0x400000>;
#clock-cells = <1>;
};
+
+ pwm0_lpcg: clock-controller@5d400000 {
+ reg = <0x5d400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_LSIO_PWM0_CLK>, <&clk IMX_LSIO_PWM0_CLK>,
+ <&clk IMX_LSIO_PWM0_CLK>, <&lsio_bus_clk>,
+ <&clk IMX_LSIO_PWM0_CLK>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_6>;
+ clock-output-names = "pwm0_lpcg_ipg_clk",
+ "pwm0_lpcg_ipg_hf_clk",
+ "pwm0_lpcg_ipg_s_clk",
+ "pwm0_lpcg_ipg_slv_clk",
+ "pwm0_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_0>;
+ };
+
+ pwm1_lpcg: clock-controller@5d410000 {
+ reg = <0x5d410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_LSIO_PWM1_CLK>, <&clk IMX_LSIO_PWM1_CLK>,
+ <&clk IMX_LSIO_PWM1_CLK>, <&lsio_bus_clk>,
+ <&clk IMX_LSIO_PWM1_CLK>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_6>;
+ clock-output-names = "pwm1_lpcg_ipg_clk",
+ "pwm1_lpcg_ipg_hf_clk",
+ "pwm1_lpcg_ipg_s_clk",
+ "pwm1_lpcg_ipg_slv_clk",
+ "pwm1_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_1>;
+ };
+
+ pwm2_lpcg: clock-controller@5d420000 {
+ reg = <0x5d420000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_LSIO_PWM2_CLK>, <&clk IMX_LSIO_PWM2_CLK>,
+ <&clk IMX_LSIO_PWM2_CLK>, <&lsio_bus_clk>,
+ <&clk IMX_LSIO_PWM2_CLK>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_6>;
+ clock-output-names = "pwm2_lpcg_ipg_clk",
+ "pwm2_lpcg_ipg_hf_clk",
+ "pwm2_lpcg_ipg_s_clk",
+ "pwm2_lpcg_ipg_slv_clk",
+ "pwm2_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_2>;
+ };
+
+ pwm3_lpcg: clock-controller@5d430000 {
+ reg = <0x5d430000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_LSIO_PWM3_CLK>, <&clk IMX_LSIO_PWM3_CLK>,
+ <&clk IMX_LSIO_PWM3_CLK>, <&lsio_bus_clk>,
+ <&clk IMX_LSIO_PWM3_CLK>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_6>;
+ clock-output-names = "pwm3_lpcg_ipg_clk",
+ "pwm3_lpcg_ipg_hf_clk",
+ "pwm3_lpcg_ipg_s_clk",
+ "pwm3_lpcg_ipg_slv_clk",
+ "pwm3_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_3>;
+ };
+
+ pwm4_lpcg: clock-controller@5d440000 {
+ reg = <0x5d440000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_LSIO_PWM4_CLK>, <&clk IMX_LSIO_PWM4_CLK>,
+ <&clk IMX_LSIO_PWM4_CLK>, <&lsio_bus_clk>,
+ <&clk IMX_LSIO_PWM4_CLK>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_6>;
+ clock-output-names = "pwm4_lpcg_ipg_clk",
+ "pwm4_lpcg_ipg_hf_clk",
+ "pwm4_lpcg_ipg_s_clk",
+ "pwm4_lpcg_ipg_slv_clk",
+ "pwm4_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_4>;
+ };
+
+ pwm5_lpcg: clock-controller@5d450000 {
+ reg = <0x5d450000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_LSIO_PWM5_CLK>, <&clk IMX_LSIO_PWM5_CLK>,
+ <&clk IMX_LSIO_PWM5_CLK>, <&lsio_bus_clk>,
+ <&clk IMX_LSIO_PWM5_CLK>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_6>;
+ clock-output-names = "pwm5_lpcg_ipg_clk",
+ "pwm5_lpcg_ipg_hf_clk",
+ "pwm5_lpcg_ipg_s_clk",
+ "pwm5_lpcg_ipg_slv_clk",
+ "pwm5_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_5>;
+ };
+
+ pwm6_lpcg: clock-controller@5d460000 {
+ reg = <0x5d460000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_LSIO_PWM6_CLK>, <&clk IMX_LSIO_PWM6_CLK>,
+ <&clk IMX_LSIO_PWM6_CLK>, <&lsio_bus_clk>,
+ <&clk IMX_LSIO_PWM6_CLK>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_6>;
+ clock-output-names = "pwm6_lpcg_ipg_clk",
+ "pwm6_lpcg_ipg_hf_clk",
+ "pwm6_lpcg_ipg_s_clk",
+ "pwm6_lpcg_ipg_slv_clk",
+ "pwm6_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_6>;
+ };
+
+ pwm7_lpcg: clock-controller@5d470000 {
+ reg = <0x5d470000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_LSIO_PWM7_CLK>, <&clk IMX_LSIO_PWM7_CLK>,
+ <&clk IMX_LSIO_PWM7_CLK>, <&lsio_bus_clk>,
+ <&clk IMX_LSIO_PWM7_CLK>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_6>;
+ clock-output-names = "pwm7_lpcg_ipg_clk",
+ "pwm7_lpcg_ipg_hf_clk",
+ "pwm7_lpcg_ipg_s_clk",
+ "pwm7_lpcg_ipg_slv_clk",
+ "pwm7_lpcg_ipg_mstr_clk";
+ power-domains = <&pd IMX_SC_R_PWM_7>;
+ };
};
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 05/15] arm64: dts: imx8: add conn lpcg clocks
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (3 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 04/15] arm64: dts: imx8: add lsio lpcg clocks Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 06/15] arm64: dts: imx8: add adma " Dong Aisheng
` (10 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng, Rob Herring, Mark Rutland, devicetree
Add conn lpcg clocks
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* update to use clock-indices property instead of bit-offset property
v1->v2:
* Use old SCU clock binding temporarily to avoid build warning due to SCU
clock cell will be changed to 2.
* add power domain propertyv1->v2:
---
.../boot/dts/freescale/imx8-ss-conn.dtsi | 104 +++++++++++++++++-
1 file changed, 101 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 5cf357fb85ae..66899c5feaac 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -4,15 +4,34 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
+#include <dt-bindings/clock/imx8-lpcg.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+
conn_subsys: bus@5b000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
- conn_lpcg: clock-controller@5b200000 {
- reg = <0x5b200000 0xb0000>;
- #clock-cells = <1>;
+ conn_axi_clk: clock-conn-axi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <333333333>;
+ clock-output-names = "conn_axi_clk";
+ };
+
+ conn_ahb_clk: clock-conn-ahb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <166666666>;
+ clock-output-names = "conn_ahb_clk";
+ };
+
+ conn_ipg_clk: clock-conn-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <83333333>;
+ clock-output-names = "conn_ipg_clk";
};
usdhc1: mmc@5b010000 {
@@ -86,4 +105,83 @@ conn_subsys: bus@5b000000 {
power-domains = <&pd IMX_SC_R_ENET_1>;
status = "disabled";
};
+
+ /* LPCG clocks */
+ conn_lpcg: clock-controller-legacy@5b200000 {
+ reg = <0x5b200000 0xb0000>;
+ #clock-cells = <1>;
+ };
+
+ sdhc0_lpcg: clock-controller@5b200000 {
+ reg = <0x5b200000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_CONN_SDHC0_CLK>,
+ <&conn_ipg_clk>, <&conn_axi_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
+ clock-output-names = "sdhc0_lpcg_per_clk",
+ "sdhc0_lpcg_ipg_clk",
+ "sdhc0_lpcg_ahb_clk";
+ power-domains = <&pd IMX_SC_R_SDHC_0>;
+ };
+
+ sdhc1_lpcg: clock-controller@5b210000 {
+ reg = <0x5b210000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_CONN_SDHC1_CLK>,
+ <&conn_ipg_clk>, <&conn_axi_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
+ clock-output-names = "sdhc1_lpcg_per_clk",
+ "sdhc1_lpcg_ipg_clk",
+ "sdhc1_lpcg_ahb_clk";
+ power-domains = <&pd IMX_SC_R_SDHC_1>;
+ };
+
+ sdhc2_lpcg: clock-controller@5b220000 {
+ reg = <0x5b220000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_CONN_SDHC2_CLK>,
+ <&conn_ipg_clk>, <&conn_axi_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
+ clock-output-names = "sdhc2_lpcg_per_clk",
+ "sdhc2_lpcg_ipg_clk",
+ "sdhc2_lpcg_ahb_clk";
+ power-domains = <&pd IMX_SC_R_SDHC_2>;
+ };
+
+ enet0_lpcg: clock-controller@5b230000 {
+ reg = <0x5b230000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>,
+ <&clk IMX_CONN_ENET0_ROOT_CLK>,
+ <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
+ clock-output-names = "enet0_ipg_root_clk",
+ "enet0_tx_clk",
+ "enet0_ahb_clk",
+ "enet0_ipg_clk",
+ "enet0_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_ENET_0>;
+ };
+
+ enet1_lpcg: clock-controller@5b240000 {
+ reg = <0x5b240000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>,
+ <&clk IMX_CONN_ENET1_ROOT_CLK>,
+ <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
+ clock-output-names = "enet1_ipg_root_clk",
+ "enet1_tx_clk",
+ "enet1_ahb_clk",
+ "enet1_ipg_clk",
+ "enet1_ipg_s_clk";
+ power-domains = <&pd IMX_SC_R_ENET_1>;
+ };
};
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 06/15] arm64: dts: imx8: add adma lpcg clocks
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (4 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 05/15] arm64: dts: imx8: add conn " Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 07/15] arm64: dts: imx8: switch to two cell scu clock binding Dong Aisheng
` (9 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng, Rob Herring, Mark Rutland, devicetree
Add adma lpcg clocks
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v3->v4:
* add missing lpcg headfile
v2->v3:
* update to use clock-indices property instead of bit-offset property
v1->v2:
* Use old SCU clock binding temporarily to avoid build warning due to SCU
clock cell will be changed to 2.
* add power domain property
---
.../boot/dts/freescale/imx8-ss-adma.dtsi | 122 ++++++++++++++++++
1 file changed, 122 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 28b8fc9a81d4..6bd194a98c36 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -4,17 +4,51 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
+#include <dt-bindings/clock/imx8-lpcg.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+
adma_subsys: bus@59000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x59000000 0x0 0x59000000 0x2000000>;
+ dma_ipg_clk: clock-dma-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "dma_ipg_clk";
+ };
+
+ /* LPCG clocks */
adma_lpcg: clock-controller@59000000 {
reg = <0x59000000 0x2000000>;
#clock-cells = <1>;
};
+ dsp_lpcg: clock-controller@59580000 {
+ reg = <0x59580000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&dma_ipg_clk>,
+ <&dma_ipg_clk>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_7>;
+ clock-output-names = "dsp_lpcg_adb_clk",
+ "dsp_lpcg_ipg_clk",
+ "dsp_lpcg_core_clk";
+ power-domains = <&pd IMX_SC_R_DSP>;
+ };
+
+ dsp_ram_lpcg: clock-controller@59590000 {
+ reg = <0x59590000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "dsp_ram_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_DSP_RAM>;
+ };
+
adma_dsp: dsp@596e8000 {
compatible = "fsl,imx8qxp-dsp";
reg = <0x596e8000 0x88000>;
@@ -80,6 +114,50 @@ adma_subsys: bus@59000000 {
status = "disabled";
};
+ uart0_lpcg: clock-controller@5a460000 {
+ reg = <0x5a460000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_UART0_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart0_lpcg_baud_clk",
+ "uart0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_0>;
+ };
+
+ uart1_lpcg: clock-controller@5a470000 {
+ reg = <0x5a470000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_UART1_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart1_lpcg_baud_clk",
+ "uart1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_1>;
+ };
+
+ uart2_lpcg: clock-controller@5a480000 {
+ reg = <0x5a480000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_UART2_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart2_lpcg_baud_clk",
+ "uart2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_2>;
+ };
+
+ uart3_lpcg: clock-controller@5a490000 {
+ reg = <0x5a490000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_UART3_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart3_lpcg_baud_clk",
+ "uart3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_3>;
+ };
+
adma_i2c0: i2c@5a800000 {
reg = <0x5a800000 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
@@ -127,4 +205,48 @@ adma_subsys: bus@59000000 {
power-domains = <&pd IMX_SC_R_I2C_3>;
status = "disabled";
};
+
+ i2c0_lpcg: clock-controller@5ac00000 {
+ reg = <0x5ac00000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_I2C0_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c0_lpcg_clk",
+ "i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_0>;
+ };
+
+ i2c1_lpcg: clock-controller@5ac10000 {
+ reg = <0x5ac10000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_I2C1_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c1_lpcg_clk",
+ "i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_1>;
+ };
+
+ i2c2_lpcg: clock-controller@5ac20000 {
+ reg = <0x5ac20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_I2C2_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c2_lpcg_clk",
+ "i2c2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_2>;
+ };
+
+ i2c3_lpcg: clock-controller@5ac30000 {
+ reg = <0x5ac30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_ADMA_I2C3_CLK>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c3_lpcg_clk",
+ "i2c3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_3>;
+ };
};
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 07/15] arm64: dts: imx8: switch to two cell scu clock binding
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (5 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 06/15] arm64: dts: imx8: add adma " Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 08/15] arm64: dts: imx8: switch to new lpcg " Dong Aisheng
` (8 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng
switch to two cell scu clock binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes except rebase
v1->v2:
* split from lpcg binding changes
---
.../boot/dts/freescale/imx8-ss-adma.dtsi | 24 +++----
.../boot/dts/freescale/imx8-ss-conn.dtsi | 14 ++--
.../boot/dts/freescale/imx8-ss-lsio.dtsi | 64 ++++++++++++-------
.../boot/dts/freescale/imx8qxp-ai_ml.dts | 4 +-
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 +-
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 10 +--
6 files changed, 68 insertions(+), 52 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 6bd194a98c36..044db3d659c0 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -117,7 +117,7 @@ adma_subsys: bus@59000000 {
uart0_lpcg: clock-controller@5a460000 {
reg = <0x5a460000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_UART0_CLK>,
+ clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart0_lpcg_baud_clk",
@@ -128,7 +128,7 @@ adma_subsys: bus@59000000 {
uart1_lpcg: clock-controller@5a470000 {
reg = <0x5a470000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_UART1_CLK>,
+ clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart1_lpcg_baud_clk",
@@ -139,7 +139,7 @@ adma_subsys: bus@59000000 {
uart2_lpcg: clock-controller@5a480000 {
reg = <0x5a480000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_UART2_CLK>,
+ clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart2_lpcg_baud_clk",
@@ -150,7 +150,7 @@ adma_subsys: bus@59000000 {
uart3_lpcg: clock-controller@5a490000 {
reg = <0x5a490000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_UART3_CLK>,
+ clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart3_lpcg_baud_clk",
@@ -164,7 +164,7 @@ adma_subsys: bus@59000000 {
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_0>;
status = "disabled";
@@ -176,7 +176,7 @@ adma_subsys: bus@59000000 {
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_1>;
status = "disabled";
@@ -188,7 +188,7 @@ adma_subsys: bus@59000000 {
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_2>;
status = "disabled";
@@ -200,7 +200,7 @@ adma_subsys: bus@59000000 {
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_3>;
status = "disabled";
@@ -209,7 +209,7 @@ adma_subsys: bus@59000000 {
i2c0_lpcg: clock-controller@5ac00000 {
reg = <0x5ac00000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_I2C0_CLK>,
+ clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c0_lpcg_clk",
@@ -220,7 +220,7 @@ adma_subsys: bus@59000000 {
i2c1_lpcg: clock-controller@5ac10000 {
reg = <0x5ac10000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_I2C1_CLK>,
+ clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c1_lpcg_clk",
@@ -231,7 +231,7 @@ adma_subsys: bus@59000000 {
i2c2_lpcg: clock-controller@5ac20000 {
reg = <0x5ac20000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_I2C2_CLK>,
+ clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c2_lpcg_clk",
@@ -242,7 +242,7 @@ adma_subsys: bus@59000000 {
i2c3_lpcg: clock-controller@5ac30000 {
reg = <0x5ac30000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_ADMA_I2C3_CLK>,
+ clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c3_lpcg_clk",
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 66899c5feaac..c04c939be58c 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -115,7 +115,7 @@ conn_subsys: bus@5b000000 {
sdhc0_lpcg: clock-controller@5b200000 {
reg = <0x5b200000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_CONN_SDHC0_CLK>,
+ clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
@@ -128,7 +128,7 @@ conn_subsys: bus@5b000000 {
sdhc1_lpcg: clock-controller@5b210000 {
reg = <0x5b210000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_CONN_SDHC1_CLK>,
+ clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
@@ -141,7 +141,7 @@ conn_subsys: bus@5b000000 {
sdhc2_lpcg: clock-controller@5b220000 {
reg = <0x5b220000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_CONN_SDHC2_CLK>,
+ clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
@@ -154,8 +154,8 @@ conn_subsys: bus@5b000000 {
enet0_lpcg: clock-controller@5b230000 {
reg = <0x5b230000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>,
- <&clk IMX_CONN_ENET0_ROOT_CLK>,
+ clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
@@ -171,8 +171,8 @@ conn_subsys: bus@5b000000 {
enet1_lpcg: clock-controller@5b240000 {
reg = <0x5b240000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>,
- <&clk IMX_CONN_ENET1_ROOT_CLK>,
+ clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index e839aa8ab586..4aa84c4dbb36 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -157,9 +157,11 @@ lsio_subsys: bus@5d000000 {
pwm0_lpcg: clock-controller@5d400000 {
reg = <0x5d400000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM0_CLK>, <&clk IMX_LSIO_PWM0_CLK>,
- <&clk IMX_LSIO_PWM0_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM0_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -174,9 +176,11 @@ lsio_subsys: bus@5d000000 {
pwm1_lpcg: clock-controller@5d410000 {
reg = <0x5d410000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM1_CLK>, <&clk IMX_LSIO_PWM1_CLK>,
- <&clk IMX_LSIO_PWM1_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM1_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -191,9 +195,11 @@ lsio_subsys: bus@5d000000 {
pwm2_lpcg: clock-controller@5d420000 {
reg = <0x5d420000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM2_CLK>, <&clk IMX_LSIO_PWM2_CLK>,
- <&clk IMX_LSIO_PWM2_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM2_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -208,9 +214,11 @@ lsio_subsys: bus@5d000000 {
pwm3_lpcg: clock-controller@5d430000 {
reg = <0x5d430000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM3_CLK>, <&clk IMX_LSIO_PWM3_CLK>,
- <&clk IMX_LSIO_PWM3_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM3_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -225,9 +233,11 @@ lsio_subsys: bus@5d000000 {
pwm4_lpcg: clock-controller@5d440000 {
reg = <0x5d440000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM4_CLK>, <&clk IMX_LSIO_PWM4_CLK>,
- <&clk IMX_LSIO_PWM4_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM4_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -242,9 +252,11 @@ lsio_subsys: bus@5d000000 {
pwm5_lpcg: clock-controller@5d450000 {
reg = <0x5d450000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM5_CLK>, <&clk IMX_LSIO_PWM5_CLK>,
- <&clk IMX_LSIO_PWM5_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM5_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -259,9 +271,11 @@ lsio_subsys: bus@5d000000 {
pwm6_lpcg: clock-controller@5d460000 {
reg = <0x5d460000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM6_CLK>, <&clk IMX_LSIO_PWM6_CLK>,
- <&clk IMX_LSIO_PWM6_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM6_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
@@ -276,9 +290,11 @@ lsio_subsys: bus@5d000000 {
pwm7_lpcg: clock-controller@5d470000 {
reg = <0x5d470000 0x10000>;
#clock-cells = <1>;
- clocks = <&clk IMX_LSIO_PWM7_CLK>, <&clk IMX_LSIO_PWM7_CLK>,
- <&clk IMX_LSIO_PWM7_CLK>, <&lsio_bus_clk>,
- <&clk IMX_LSIO_PWM7_CLK>;
+ clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
+ <&lsio_bus_clk>,
+ <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
index a3f8cf195974..b5352706e3f0 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
@@ -133,7 +133,7 @@
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
- assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -151,7 +151,7 @@
/* SD */
&usdhc2 {
- assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index d3d26cca7d52..bb374ea4f3bf 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -137,7 +137,7 @@
};
&usdhc1 {
- assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -149,7 +149,7 @@
};
&usdhc2 {
- assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
+ assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index e408d214943f..eb2f3765334e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -47,7 +47,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&clk IMX_A35_CLK>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -58,7 +58,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&clk IMX_A35_CLK>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -69,7 +69,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&clk IMX_A35_CLK>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -80,7 +80,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&clk IMX_A35_CLK>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -160,7 +160,7 @@
clk: clock-controller {
compatible = "fsl,imx8qxp-clk";
- #clock-cells = <1>;
+ #clock-cells = <2>;
clocks = <&xtal32k &xtal24m>;
clock-names = "xtal_32KHz", "xtal_24Mhz";
};
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 08/15] arm64: dts: imx8: switch to new lpcg clock binding
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (6 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 07/15] arm64: dts: imx8: switch to two cell scu clock binding Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 09/15] arm64: dts: imx8qm: add lsio ss support Dong Aisheng
` (7 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng
switch to new lpcg clock binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* use new clock-indices IDs
v1->v2:
* split scu clock changes
---
.../boot/dts/freescale/imx8-ss-adma.dtsi | 46 ++++++++++---------
.../boot/dts/freescale/imx8-ss-conn.dtsi | 44 +++++++++---------
.../boot/dts/freescale/imx8-ss-lsio.dtsi | 13 ++++--
.../boot/dts/freescale/imx8qxp-ss-adma.dtsi | 4 --
.../boot/dts/freescale/imx8qxp-ss-conn.dtsi | 4 --
.../boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 4 --
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
7 files changed, 56 insertions(+), 60 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 044db3d659c0..1501424c7b76 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -20,13 +20,8 @@ adma_subsys: bus@59000000 {
clock-output-names = "dma_ipg_clk";
};
- /* LPCG clocks */
- adma_lpcg: clock-controller@59000000 {
- reg = <0x59000000 0x2000000>;
- #clock-cells = <1>;
- };
-
dsp_lpcg: clock-controller@59580000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x59580000 0x10000>;
#clock-cells = <1>;
clocks = <&dma_ipg_clk>,
@@ -41,6 +36,7 @@ adma_subsys: bus@59000000 {
};
dsp_ram_lpcg: clock-controller@59590000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x59590000 0x10000>;
#clock-cells = <1>;
clocks = <&dma_ipg_clk>;
@@ -52,9 +48,9 @@ adma_subsys: bus@59000000 {
adma_dsp: dsp@596e8000 {
compatible = "fsl,imx8qxp-dsp";
reg = <0x596e8000 0x88000>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
+ clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
+ <&dsp_ram_lpcg IMX_LPCG_CLK_4>,
+ <&dsp_lpcg IMX_LPCG_CLK_7>;
clock-names = "ipg", "ocram", "core";
power-domains = <&pd IMX_SC_R_MU_13A>,
<&pd IMX_SC_R_MU_13B>,
@@ -74,8 +70,8 @@ adma_subsys: bus@59000000 {
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
+ clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
+ <&uart0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_0>;
status = "disabled";
@@ -85,8 +81,8 @@ adma_subsys: bus@59000000 {
reg = <0x5a070000 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
+ clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
+ <&uart1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_1>;
status = "disabled";
@@ -96,8 +92,8 @@ adma_subsys: bus@59000000 {
reg = <0x5a080000 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
+ clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
+ <&uart2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_2>;
status = "disabled";
@@ -107,14 +103,15 @@ adma_subsys: bus@59000000 {
reg = <0x5a090000 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
+ clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
+ <&uart3_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_3>;
status = "disabled";
};
uart0_lpcg: clock-controller@5a460000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a460000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
@@ -126,6 +123,7 @@ adma_subsys: bus@59000000 {
};
uart1_lpcg: clock-controller@5a470000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a470000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
@@ -137,6 +135,7 @@ adma_subsys: bus@59000000 {
};
uart2_lpcg: clock-controller@5a480000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a480000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
@@ -148,6 +147,7 @@ adma_subsys: bus@59000000 {
};
uart3_lpcg: clock-controller@5a490000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a490000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
@@ -162,7 +162,7 @@ adma_subsys: bus@59000000 {
reg = <0x5a800000 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
+ clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>;
clock-names = "per";
assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
@@ -174,7 +174,7 @@ adma_subsys: bus@59000000 {
reg = <0x5a810000 0x4000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
+ clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>;
clock-names = "per";
assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
@@ -186,7 +186,7 @@ adma_subsys: bus@59000000 {
reg = <0x5a820000 0x4000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
+ clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>;
clock-names = "per";
assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
@@ -198,7 +198,7 @@ adma_subsys: bus@59000000 {
reg = <0x5a830000 0x4000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
+ clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>;
clock-names = "per";
assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
@@ -207,6 +207,7 @@ adma_subsys: bus@59000000 {
};
i2c0_lpcg: clock-controller@5ac00000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
@@ -218,6 +219,7 @@ adma_subsys: bus@59000000 {
};
i2c1_lpcg: clock-controller@5ac10000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac10000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
@@ -229,6 +231,7 @@ adma_subsys: bus@59000000 {
};
i2c2_lpcg: clock-controller@5ac20000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac20000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
@@ -240,6 +243,7 @@ adma_subsys: bus@59000000 {
};
i2c3_lpcg: clock-controller@5ac30000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac30000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index c04c939be58c..725349e297be 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -38,9 +38,9 @@ conn_subsys: bus@5b000000 {
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
+ clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
+ <&sdhc0_lpcg IMX_LPCG_CLK_0>,
+ <&sdhc0_lpcg IMX_LPCG_CLK_5>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_0>;
status = "disabled";
@@ -50,9 +50,9 @@ conn_subsys: bus@5b000000 {
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b020000 0x10000>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
+ clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
+ <&sdhc1_lpcg IMX_LPCG_CLK_0>,
+ <&sdhc1_lpcg IMX_LPCG_CLK_5>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
@@ -64,9 +64,9 @@ conn_subsys: bus@5b000000 {
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b030000 0x10000>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
+ clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
+ <&sdhc2_lpcg IMX_LPCG_CLK_0>,
+ <&sdhc2_lpcg IMX_LPCG_CLK_5>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_2>;
status = "disabled";
@@ -78,10 +78,10 @@ conn_subsys: bus@5b000000 {
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
+ clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
+ <&enet0_lpcg IMX_LPCG_CLK_2>,
+ <&enet0_lpcg IMX_LPCG_CLK_1>,
+ <&enet0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
@@ -95,10 +95,10 @@ conn_subsys: bus@5b000000 {
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
+ clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
+ <&enet1_lpcg IMX_LPCG_CLK_2>,
+ <&enet1_lpcg IMX_LPCG_CLK_1>,
+ <&enet1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
@@ -107,12 +107,8 @@ conn_subsys: bus@5b000000 {
};
/* LPCG clocks */
- conn_lpcg: clock-controller-legacy@5b200000 {
- reg = <0x5b200000 0xb0000>;
- #clock-cells = <1>;
- };
-
sdhc0_lpcg: clock-controller@5b200000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b200000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
@@ -126,6 +122,7 @@ conn_subsys: bus@5b000000 {
};
sdhc1_lpcg: clock-controller@5b210000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b210000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
@@ -139,6 +136,7 @@ conn_subsys: bus@5b000000 {
};
sdhc2_lpcg: clock-controller@5b220000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b220000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
@@ -152,6 +150,7 @@ conn_subsys: bus@5b000000 {
};
enet0_lpcg: clock-controller@5b230000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b230000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
@@ -169,6 +168,7 @@ conn_subsys: bus@5b000000 {
};
enet1_lpcg: clock-controller@5b240000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b240000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index 4aa84c4dbb36..c21e0818887b 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -149,12 +149,8 @@ lsio_subsys: bus@5d000000 {
};
/* LPCG clocks */
- lsio_lpcg: clock-controller-legacy@5d400000 {
- reg = <0x5d400000 0x400000>;
- #clock-cells = <1>;
- };
-
pwm0_lpcg: clock-controller@5d400000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d400000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
@@ -174,6 +170,7 @@ lsio_subsys: bus@5d000000 {
};
pwm1_lpcg: clock-controller@5d410000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d410000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
@@ -193,6 +190,7 @@ lsio_subsys: bus@5d000000 {
};
pwm2_lpcg: clock-controller@5d420000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d420000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
@@ -212,6 +210,7 @@ lsio_subsys: bus@5d000000 {
};
pwm3_lpcg: clock-controller@5d430000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d430000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
@@ -231,6 +230,7 @@ lsio_subsys: bus@5d000000 {
};
pwm4_lpcg: clock-controller@5d440000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d440000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
@@ -250,6 +250,7 @@ lsio_subsys: bus@5d000000 {
};
pwm5_lpcg: clock-controller@5d450000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d450000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
@@ -269,6 +270,7 @@ lsio_subsys: bus@5d000000 {
};
pwm6_lpcg: clock-controller@5d460000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d460000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
@@ -288,6 +290,7 @@ lsio_subsys: bus@5d000000 {
};
pwm7_lpcg: clock-controller@5d470000 {
+ compatible = "fsl,imx8qxp-lpcg";
reg = <0x5d470000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
index 5809324de8df..c80303d5cc78 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
@@ -4,10 +4,6 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
-&adma_lpcg {
- compatible = "fsl,imx8qxp-lpcg-adma";
-};
-
&adma_lpuart0 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
index ea0cd518680b..8dd22bdd72c0 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
@@ -4,10 +4,6 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
-&conn_lpcg {
- compatible = "fsl,imx8qxp-lpcg-conn";
-};
-
&usdhc1 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
index b02ae5df597f..1c3d1171c1c3 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
@@ -59,7 +59,3 @@
&lsio_mu13 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
-
-&lsio_lpcg {
- compatible = "fsl,imx8qxp-lpcg-lsio";
-};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index eb2f3765334e..4281dd68ded2 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/clock/imx8-clock.h>
+#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 09/15] arm64: dts: imx8qm: add lsio ss support
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (7 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 08/15] arm64: dts: imx8: switch to new lpcg " Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 10/15] arm64: dts: imx8qm: add conn " Dong Aisheng
` (6 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng, Rob Herring, Mark Rutland, devicetree
The LSIO SS of MX8QM is exactly the same as MX8QXP. So we can fully
reuse the exist LSIO SS dtsi. Add <soc>-ss-lsio.dtsi with compatible
string updated according to imx8-ss-lsio.dtsi.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* change to the new two cell scu clk binding
---
.../boot/dts/freescale/imx8qm-ss-lsio.dtsi | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
new file mode 100644
index 000000000000..6fe390641010
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&lsio_gpio0 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio1 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio2 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio3 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio4 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio5 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio6 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_gpio7 {
+ compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+};
+
+&lsio_mu0 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu1 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu2 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu3 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu4 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu13 {
+ compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 10/15] arm64: dts: imx8qm: add conn ss support
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (8 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 09/15] arm64: dts: imx8qm: add lsio ss support Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 11/15] arm64: dts: imx8: split adma ss into dma and audio ss Dong Aisheng
` (5 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng, Rob Herring, Mark Rutland, devicetree
The CONN SS of MX8QM is mostly the same as MX8QXP except it has one more
USB HSIC module support. So we can fully reuse the exist CONN SS dtsi.
Add <soc>-ss-conn.dtsi with compatible string updated according to
imx8-ss-conn.dtsi.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* change to the new two cell scu clk binding
---
.../boot/dts/freescale/imx8qm-ss-conn.dtsi | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
new file mode 100644
index 000000000000..00ae820d5175
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&fec1 {
+ compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
+};
+
+&fec2 {
+ compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
+};
+
+&usdhc1 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc";
+};
+
+&usdhc2 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc";
+};
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 11/15] arm64: dts: imx8: split adma ss into dma and audio ss
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (9 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 10/15] arm64: dts: imx8qm: add conn " Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 12/15] arm64: dts: imx8qm: add dma ss support Dong Aisheng
` (4 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng
amda ss is consisted of dma and audio ss in qxp which are
also used in qm.
Let's split them into two ss for better code reuse.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v3->4:
* remove amda_* prefix for new boards colibri
v2->v3:
* use new clock-indices IDs
* remove ss prefix for adma
v1->v2:
* change to the new two cell scu clk binding
---
.../boot/dts/freescale/imx8-ss-adma.dtsi | 252 +-----------------
.../boot/dts/freescale/imx8-ss-audio.dtsi | 68 +++++
.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 210 +++++++++++++++
.../boot/dts/freescale/imx8qxp-ai_ml.dts | 16 +-
.../freescale/imx8qxp-colibri-eval-v3.dtsi | 8 +-
.../boot/dts/freescale/imx8qxp-colibri.dtsi | 12 +-
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 8 +-
.../boot/dts/freescale/imx8qxp-ss-adma.dtsi | 16 +-
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 8 +-
9 files changed, 314 insertions(+), 284 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 1501424c7b76..22b6dfe63950 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -4,253 +4,5 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
-#include <dt-bindings/clock/imx8-lpcg.h>
-#include <dt-bindings/firmware/imx/rsrc.h>
-
-adma_subsys: bus@59000000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x59000000 0x0 0x59000000 0x2000000>;
-
- dma_ipg_clk: clock-dma-ipg {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <120000000>;
- clock-output-names = "dma_ipg_clk";
- };
-
- dsp_lpcg: clock-controller@59580000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x59580000 0x10000>;
- #clock-cells = <1>;
- clocks = <&dma_ipg_clk>,
- <&dma_ipg_clk>,
- <&dma_ipg_clk>;
- clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
- <IMX_LPCG_CLK_7>;
- clock-output-names = "dsp_lpcg_adb_clk",
- "dsp_lpcg_ipg_clk",
- "dsp_lpcg_core_clk";
- power-domains = <&pd IMX_SC_R_DSP>;
- };
-
- dsp_ram_lpcg: clock-controller@59590000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x59590000 0x10000>;
- #clock-cells = <1>;
- clocks = <&dma_ipg_clk>;
- clock-indices = <IMX_LPCG_CLK_4>;
- clock-output-names = "dsp_ram_lpcg_ipg_clk";
- power-domains = <&pd IMX_SC_R_DSP_RAM>;
- };
-
- adma_dsp: dsp@596e8000 {
- compatible = "fsl,imx8qxp-dsp";
- reg = <0x596e8000 0x88000>;
- clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
- <&dsp_ram_lpcg IMX_LPCG_CLK_4>,
- <&dsp_lpcg IMX_LPCG_CLK_7>;
- clock-names = "ipg", "ocram", "core";
- power-domains = <&pd IMX_SC_R_MU_13A>,
- <&pd IMX_SC_R_MU_13B>,
- <&pd IMX_SC_R_DSP>,
- <&pd IMX_SC_R_DSP_RAM>;
- mbox-names = "txdb0", "txdb1",
- "rxdb0", "rxdb1";
- mboxes = <&lsio_mu13 2 0>,
- <&lsio_mu13 2 1>,
- <&lsio_mu13 3 0>,
- <&lsio_mu13 3 1>;
- memory-region = <&dsp_reserved>;
- status = "disabled";
- };
-
- adma_lpuart0: serial@5a060000 {
- reg = <0x5a060000 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
- <&uart0_lpcg IMX_LPCG_CLK_0>;
- clock-names = "ipg", "baud";
- power-domains = <&pd IMX_SC_R_UART_0>;
- status = "disabled";
- };
-
- adma_lpuart1: serial@5a070000 {
- reg = <0x5a070000 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
- <&uart1_lpcg IMX_LPCG_CLK_0>;
- clock-names = "ipg", "baud";
- power-domains = <&pd IMX_SC_R_UART_1>;
- status = "disabled";
- };
-
- adma_lpuart2: serial@5a080000 {
- reg = <0x5a080000 0x1000>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
- <&uart2_lpcg IMX_LPCG_CLK_0>;
- clock-names = "ipg", "baud";
- power-domains = <&pd IMX_SC_R_UART_2>;
- status = "disabled";
- };
-
- adma_lpuart3: serial@5a090000 {
- reg = <0x5a090000 0x1000>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
- <&uart3_lpcg IMX_LPCG_CLK_0>;
- clock-names = "ipg", "baud";
- power-domains = <&pd IMX_SC_R_UART_3>;
- status = "disabled";
- };
-
- uart0_lpcg: clock-controller@5a460000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x5a460000 0x10000>;
- #clock-cells = <1>;
- clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
- <&dma_ipg_clk>;
- clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
- clock-output-names = "uart0_lpcg_baud_clk",
- "uart0_lpcg_ipg_clk";
- power-domains = <&pd IMX_SC_R_UART_0>;
- };
-
- uart1_lpcg: clock-controller@5a470000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x5a470000 0x10000>;
- #clock-cells = <1>;
- clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
- <&dma_ipg_clk>;
- clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
- clock-output-names = "uart1_lpcg_baud_clk",
- "uart1_lpcg_ipg_clk";
- power-domains = <&pd IMX_SC_R_UART_1>;
- };
-
- uart2_lpcg: clock-controller@5a480000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x5a480000 0x10000>;
- #clock-cells = <1>;
- clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
- <&dma_ipg_clk>;
- clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
- clock-output-names = "uart2_lpcg_baud_clk",
- "uart2_lpcg_ipg_clk";
- power-domains = <&pd IMX_SC_R_UART_2>;
- };
-
- uart3_lpcg: clock-controller@5a490000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x5a490000 0x10000>;
- #clock-cells = <1>;
- clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
- <&dma_ipg_clk>;
- clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
- clock-output-names = "uart3_lpcg_baud_clk",
- "uart3_lpcg_ipg_clk";
- power-domains = <&pd IMX_SC_R_UART_3>;
- };
-
- adma_i2c0: i2c@5a800000 {
- reg = <0x5a800000 0x4000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>;
- clock-names = "per";
- assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
- assigned-clock-rates = <24000000>;
- power-domains = <&pd IMX_SC_R_I2C_0>;
- status = "disabled";
- };
-
- adma_i2c1: i2c@5a810000 {
- reg = <0x5a810000 0x4000>;
- interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>;
- clock-names = "per";
- assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
- assigned-clock-rates = <24000000>;
- power-domains = <&pd IMX_SC_R_I2C_1>;
- status = "disabled";
- };
-
- adma_i2c2: i2c@5a820000 {
- reg = <0x5a820000 0x4000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>;
- clock-names = "per";
- assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
- assigned-clock-rates = <24000000>;
- power-domains = <&pd IMX_SC_R_I2C_2>;
- status = "disabled";
- };
-
- adma_i2c3: i2c@5a830000 {
- reg = <0x5a830000 0x4000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>;
- clock-names = "per";
- assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
- assigned-clock-rates = <24000000>;
- power-domains = <&pd IMX_SC_R_I2C_3>;
- status = "disabled";
- };
-
- i2c0_lpcg: clock-controller@5ac00000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x5ac00000 0x10000>;
- #clock-cells = <1>;
- clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
- <&dma_ipg_clk>;
- clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
- clock-output-names = "i2c0_lpcg_clk",
- "i2c0_lpcg_ipg_clk";
- power-domains = <&pd IMX_SC_R_I2C_0>;
- };
-
- i2c1_lpcg: clock-controller@5ac10000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x5ac10000 0x10000>;
- #clock-cells = <1>;
- clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
- <&dma_ipg_clk>;
- clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
- clock-output-names = "i2c1_lpcg_clk",
- "i2c1_lpcg_ipg_clk";
- power-domains = <&pd IMX_SC_R_I2C_1>;
- };
-
- i2c2_lpcg: clock-controller@5ac20000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x5ac20000 0x10000>;
- #clock-cells = <1>;
- clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
- <&dma_ipg_clk>;
- clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
- clock-output-names = "i2c2_lpcg_clk",
- "i2c2_lpcg_ipg_clk";
- power-domains = <&pd IMX_SC_R_I2C_2>;
- };
-
- i2c3_lpcg: clock-controller@5ac30000 {
- compatible = "fsl,imx8qxp-lpcg";
- reg = <0x5ac30000 0x10000>;
- #clock-cells = <1>;
- clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
- <&dma_ipg_clk>;
- clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
- clock-output-names = "i2c3_lpcg_clk",
- "i2c3_lpcg_ipg_clk";
- power-domains = <&pd IMX_SC_R_I2C_3>;
- };
-};
+#include "imx8-ss-audio.dtsi"
+#include "imx8-ss-dma.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
new file mode 100644
index 000000000000..6c8d75ef9250
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/clock/imx8-lpcg.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+audio_subsys: bus@59000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x59000000 0x0 0x59000000 0x1000000>;
+
+ audio_ipg_clk: clock-audio-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "audio_ipg_clk";
+ };
+
+ dsp_lpcg: clock-controller@59580000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59580000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&audio_ipg_clk>,
+ <&audio_ipg_clk>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_7>;
+ clock-output-names = "dsp_lpcg_adb_clk",
+ "dsp_lpcg_ipg_clk",
+ "dsp_lpcg_core_clk";
+ power-domains = <&pd IMX_SC_R_DSP>;
+ };
+
+ dsp_ram_lpcg: clock-controller@59590000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59590000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "dsp_ram_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_DSP_RAM>;
+ };
+
+ dsp: dsp@596e8000 {
+ compatible = "fsl,imx8qxp-dsp";
+ reg = <0x596e8000 0x88000>;
+ clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
+ <&dsp_ram_lpcg IMX_LPCG_CLK_4>,
+ <&dsp_lpcg IMX_LPCG_CLK_7>;
+ clock-names = "ipg", "ocram", "core";
+ power-domains = <&pd IMX_SC_R_MU_13A>,
+ <&pd IMX_SC_R_MU_13B>,
+ <&pd IMX_SC_R_DSP>,
+ <&pd IMX_SC_R_DSP_RAM>;
+ mbox-names = "txdb0", "txdb1",
+ "rxdb0", "rxdb1";
+ mboxes = <&lsio_mu13 2 0>,
+ <&lsio_mu13 2 1>,
+ <&lsio_mu13 3 0>,
+ <&lsio_mu13 3 1>;
+ memory-region = <&dsp_reserved>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
new file mode 100644
index 000000000000..70c15e4a4da1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/clock/imx8-lpcg.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+dma_subsys: bus@5a000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
+
+ dma_ipg_clk: clock-dma-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <120000000>;
+ clock-output-names = "dma_ipg_clk";
+ };
+
+ lpuart0: serial@5a060000 {
+ reg = <0x5a060000 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
+ <&uart0_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "baud";
+ power-domains = <&pd IMX_SC_R_UART_0>;
+ status = "disabled";
+ };
+
+ lpuart1: serial@5a070000 {
+ reg = <0x5a070000 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
+ <&uart1_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "baud";
+ power-domains = <&pd IMX_SC_R_UART_1>;
+ status = "disabled";
+ };
+
+ lpuart2: serial@5a080000 {
+ reg = <0x5a080000 0x1000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
+ <&uart2_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "baud";
+ power-domains = <&pd IMX_SC_R_UART_2>;
+ status = "disabled";
+ };
+
+ lpuart3: serial@5a090000 {
+ reg = <0x5a090000 0x1000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
+ <&uart3_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "baud";
+ power-domains = <&pd IMX_SC_R_UART_3>;
+ status = "disabled";
+ };
+
+ uart0_lpcg: clock-controller@5a460000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a460000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart0_lpcg_baud_clk",
+ "uart0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_0>;
+ };
+
+ uart1_lpcg: clock-controller@5a470000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a470000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart1_lpcg_baud_clk",
+ "uart1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_1>;
+ };
+
+ uart2_lpcg: clock-controller@5a480000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a480000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart2_lpcg_baud_clk",
+ "uart2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_2>;
+ };
+
+ uart3_lpcg: clock-controller@5a490000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a490000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart3_lpcg_baud_clk",
+ "uart3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_3>;
+ };
+
+ i2c0: i2c@5a800000 {
+ reg = <0x5a800000 0x4000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "per";
+ assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@5a810000 {
+ reg = <0x5a810000 0x4000>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "per";
+ assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@5a820000 {
+ reg = <0x5a820000 0x4000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "per";
+ assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@5a830000 {
+ reg = <0x5a830000 0x4000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "per";
+ assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_I2C_3>;
+ status = "disabled";
+ };
+
+ i2c0_lpcg: clock-controller@5ac00000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac00000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c0_lpcg_clk",
+ "i2c0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_0>;
+ };
+
+ i2c1_lpcg: clock-controller@5ac10000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac10000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c1_lpcg_clk",
+ "i2c1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_1>;
+ };
+
+ i2c2_lpcg: clock-controller@5ac20000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c2_lpcg_clk",
+ "i2c2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_2>;
+ };
+
+ i2c3_lpcg: clock-controller@5ac30000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "i2c3_lpcg_clk",
+ "i2c3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_I2C_3>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
index b5352706e3f0..47bb68823b24 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
@@ -13,13 +13,13 @@
compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
aliases {
- serial1 = &adma_lpuart1;
- serial2 = &adma_lpuart2;
- serial3 = &adma_lpuart3;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
};
chosen {
- stdout-path = &adma_lpuart2;
+ stdout-path = &lpuart2;
};
memory@80000000 {
@@ -82,7 +82,7 @@
};
/* BT */
-&adma_lpuart0 {
+&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
uart-has-rtscts;
@@ -90,21 +90,21 @@
};
/* LS-UART0 */
-&adma_lpuart1 {
+&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
/* Debug */
-&adma_lpuart2 {
+&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";
};
/* PCI-E UART */
-&adma_lpuart3 {
+&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>;
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
index c7336f387605..144fc9e82da7 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
@@ -26,7 +26,7 @@
};
};
-&adma_i2c1 {
+&i2c1 {
status = "okay";
/* M41T0M6 real time clock on carrier board */
@@ -37,17 +37,17 @@
};
/* Colibri UART_B */
-&adma_lpuart0 {
+&lpuart0 {
status= "okay";
};
/* Colibri UART_C */
-&adma_lpuart2 {
+&lpuart2 {
status= "okay";
};
/* Colibri UART_A */
-&adma_lpuart3 {
+&lpuart3 {
status= "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
index 75f17a29f81e..f83d66e30806 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
@@ -10,7 +10,7 @@
compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
chosen {
- stdout-path = &adma_lpuart3;
+ stdout-path = &lpuart3;
};
reg_module_3v3: regulator-module-3v3 {
@@ -22,7 +22,7 @@
};
/* On-module I2C */
-&adma_i2c0 {
+&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
@@ -49,7 +49,7 @@
};
/* Colibri I2C */
-&adma_i2c1 {
+&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
@@ -58,19 +58,19 @@
};
/* Colibri UART_B */
-&adma_lpuart0 {
+&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
};
/* Colibri UART_C */
-&adma_lpuart2 {
+&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
};
/* Colibri UART_A */
-&adma_lpuart3 {
+&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index bb374ea4f3bf..76f470c7dd97 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -12,7 +12,7 @@
compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
chosen {
- stdout-path = &adma_lpuart0;
+ stdout-path = &lpuart0;
};
memory@80000000 {
@@ -30,7 +30,7 @@
};
};
-&adma_lpuart0 {
+&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
@@ -60,7 +60,7 @@
};
};
-&adma_i2c1 {
+&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
@@ -235,7 +235,7 @@
};
};
-&adma_dsp {
+&dsp {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
index c80303d5cc78..f0264f04f986 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
@@ -4,34 +4,34 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
-&adma_lpuart0 {
+&lpuart0 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};
-&adma_lpuart1 {
+&lpuart1 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};
-&adma_lpuart2 {
+&lpuart2 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};
-&adma_lpuart3 {
+&lpuart3 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};
-&adma_i2c0 {
+&i2c0 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};
-&adma_i2c1 {
+&i2c1 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};
-&adma_i2c2 {
+&i2c2 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};
-&adma_i2c3 {
+&i2c3 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 4281dd68ded2..ff87c677274b 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -31,10 +31,10 @@
mmc1 = &usdhc2;
mmc2 = &usdhc3;
mu1 = &lsio_mu1;
- serial0 = &adma_lpuart0;
- serial1 = &adma_lpuart1;
- serial2 = &adma_lpuart2;
- serial3 = &adma_lpuart3;
+ serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
};
cpus {
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 12/15] arm64: dts: imx8qm: add dma ss support
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (10 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 11/15] arm64: dts: imx8: split adma ss into dma and audio ss Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 13/15] arm64: dts: imx: add imx8qm common dts file Dong Aisheng
` (3 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng, Rob Herring, Mark Rutland, devicetree
The DMA SS of MX8QM is mostly the same as the DMA part in MX8QXP ADMA SS
while it has one more instance for each of LPUART, ADC and LPI2C. And unlike
MX8QXP that flexcan clocks are shared between multiple CAN instances,
MX8QM has separate flexcan clock slice.
So we reuse the most part of common imx8-ss-dma.dtsi and add new things
based on it.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* use new clock-indices IDs
* update lpuart fallback compatible string to fsl,imx8qxp-lpuart
v1->v2:
* change to the new two cell scu clk binding
---
.../boot/dts/freescale/imx8qm-ss-dma.dtsi | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
new file mode 100644
index 000000000000..bbe5f5ecfb92
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&dma_subsys {
+ uart4_lpcg: clock-controller@5a4a0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a4a0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "uart4_lpcg_baud_clk",
+ "uart4_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_UART_4>;
+ };
+};
+
+&lpuart0 {
+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+};
+
+&lpuart1 {
+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+};
+
+&lpuart2 {
+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+};
+
+&lpuart3 {
+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+};
+
+&i2c0 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&i2c1 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&i2c2 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+};
+
+&i2c3 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+};
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 13/15] arm64: dts: imx: add imx8qm common dts file
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (11 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 12/15] arm64: dts: imx8qm: add dma ss support Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2019-11-17 12:43 ` [PATCH RESEND v3 14/15] arm64: dts: imx: add imx8qm mek support Dong Aisheng
` (2 subsequent siblings)
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng, Rob Herring, Mark Rutland, devicetree
The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53
proccessor with powerful graphic and multimedia features. It uses
the same architecture as MX8QXP, so many SS can be reused.
This patch adds i.MX8QuadMax SoC dtsi file.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* remove a typo change on imx8qxp.dtsi which is unrelated to this patch
* include new imx8-lpcg.h
v1->v2:
* change to the new two cell scu clk binding
---
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 180 ++++++++++++++++++++++
1 file changed, 180 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qm.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
new file mode 100644
index 000000000000..87a4c3ec8861
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/clock/imx8-lpcg.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ serial0 = &lpuart0;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&A53_0>;
+ };
+ core1 {
+ cpu = <&A53_1>;
+ };
+ core2 {
+ cpu = <&A53_2>;
+ };
+ core3 {
+ cpu = <&A53_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&A72_0>;
+ };
+ core1 {
+ cpu = <&A72_1>;
+ };
+ };
+ };
+
+ A53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A53_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ };
+
+ A72_0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&A72_L2>;
+ };
+
+ A72_1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&A72_L2>;
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ A72_L2: l2-cache1 {
+ compatible = "cache";
+ };
+ };
+
+ gic: interrupt-controller@51a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+ <0x0 0x51b00000 0 0xC0000>, /* GICR */
+ <0x0 0x52000000 0 0x2000>, /* GICC */
+ <0x0 0x52010000 0 0x1000>, /* GICH */
+ <0x0 0x52020000 0 0x20000>; /* GICV */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
+ };
+
+ scu {
+ compatible = "fsl,imx-scu";
+ mbox-names = "tx0", "tx1", "tx2", "tx3",
+ "rx0", "rx1", "rx2", "rx3";
+ mboxes = <&lsio_mu1 0 0
+ &lsio_mu1 0 1
+ &lsio_mu1 0 2
+ &lsio_mu1 0 3
+ &lsio_mu1 1 0
+ &lsio_mu1 1 1
+ &lsio_mu1 1 2
+ &lsio_mu1 1 3>;
+
+ pd: imx8qx-pd {
+ compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
+ #power-domain-cells = <1>;
+ };
+
+ clk: clock-controller {
+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
+ #clock-cells = <2>;
+ };
+
+ iomuxc: pinctrl {
+ compatible = "fsl,imx8qm-iomuxc";
+ };
+
+ };
+
+ /* sorted in register address */
+ #include "imx8-ss-dma.dtsi"
+ #include "imx8-ss-conn.dtsi"
+ #include "imx8-ss-lsio.dtsi"
+};
+
+#include "imx8qm-ss-dma.dtsi"
+#include "imx8qm-ss-conn.dtsi"
+#include "imx8qm-ss-lsio.dtsi"
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v3 14/15] arm64: dts: imx: add imx8qm mek support
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (12 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 13/15] arm64: dts: imx: add imx8qm common dts file Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2020-02-25 9:07 ` Oliver Graute
2019-11-17 12:43 ` [PATCH RESEND v3 15/15] arm64: defconfig: " Dong Aisheng
2020-04-07 2:25 ` [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Aisheng Dong
15 siblings, 1 reply; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng, Rob Herring, Mark Rutland, devicetree
The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53
proccessor with powerful graphic and multimedia features.
This patch adds i.MX8QuadMax MEK board support.
Note that MX8QM needs a special workaround for TLB flush due to a SoC
errata, otherwise there may be random crash if enable both clusters of
A72 and A53. As the errata workaround is still not in mainline, so we
disable A72 cluster first for MX8QM MEK.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* copyright update to 2019, minor node name change
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 144 +++++++++++++++++++
2 files changed, 145 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-mek.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 38e344a2f0ff..54508e3059a7 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
new file mode 100644
index 000000000000..ce9d3f0b98fc
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+/dts-v1/;
+
+#include "imx8qm.dtsi"
+
+/ {
+ model = "Freescale i.MX8QM MEK";
+ compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+ chosen {
+ stdout-path = &lpuart0;
+ };
+
+ cpus {
+ /delete-node/ cpu-map;
+ /delete-node/ cpu@100;
+ /delete-node/ cpu@101;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ };
+
+ reg_usdhc2_vmmc: usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "SD1_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&lpuart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
+ IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
+ IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
+ IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
+ IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
+ IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
+ IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
+ IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
+ IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
+ IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
+ IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
+ IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
+ IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
+ IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
+ >;
+ };
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
+ IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+};
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH RESEND v3 14/15] arm64: dts: imx: add imx8qm mek support
2019-11-17 12:43 ` [PATCH RESEND v3 14/15] arm64: dts: imx: add imx8qm mek support Dong Aisheng
@ 2020-02-25 9:07 ` Oliver Graute
0 siblings, 0 replies; 18+ messages in thread
From: Oliver Graute @ 2020-02-25 9:07 UTC (permalink / raw)
To: Dong Aisheng
Cc: linux-arm-kernel, Mark Rutland, devicetree, sboyd, mturquette,
Rob Herring, linux-imx, kernel, fabio.estevam, shawnguo,
linux-clk, peng.fan
On 17/11/19, Dong Aisheng wrote:
> The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53
> proccessor with powerful graphic and multimedia features.
> This patch adds i.MX8QuadMax MEK board support.
>
> Note that MX8QM needs a special workaround for TLB flush due to a SoC
> errata, otherwise there may be random crash if enable both clusters of
> A72 and A53. As the errata workaround is still not in mainline, so we
> disable A72 cluster first for MX8QM MEK.
can you point me to the errata workaround patch for the MMU/TLB Coherency
issue? I observe the same issue here with another imx8qm board.
Best Regards,
Oliver
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND v3 15/15] arm64: defconfig: add imx8qm mek support
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (13 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 14/15] arm64: dts: imx: add imx8qm mek support Dong Aisheng
@ 2019-11-17 12:43 ` Dong Aisheng
2020-04-07 2:25 ` [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Aisheng Dong
15 siblings, 0 replies; 18+ messages in thread
From: Dong Aisheng @ 2019-11-17 12:43 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, fabio.estevam, linux-imx,
kernel, Dong Aisheng, Catalin Marinas, Will Deacon
Except MX8QM pinctrl driver is missing, all other necessary drivers
for a booting are reused from MX8QXP which are already enabled
in defconfig.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* add more commit messages
v1->v2:
* no changes
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ecd5952931c1..2e0d26fac8b0 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -404,6 +404,7 @@ CONFIG_PINCTRL_MAX77620=y
CONFIG_PINCTRL_IMX8MM=y
CONFIG_PINCTRL_IMX8MN=y
CONFIG_PINCTRL_IMX8MQ=y
+CONFIG_PINCTRL_IMX8QM=y
CONFIG_PINCTRL_IMX8QXP=y
CONFIG_PINCTRL_IPQ8074=y
CONFIG_PINCTRL_MSM8916=y
--
2.23.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* RE: [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support
2019-11-17 12:43 [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement and adding imx8qm support Dong Aisheng
` (14 preceding siblings ...)
2019-11-17 12:43 ` [PATCH RESEND v3 15/15] arm64: defconfig: " Dong Aisheng
@ 2020-04-07 2:25 ` Aisheng Dong
15 siblings, 0 replies; 18+ messages in thread
From: Aisheng Dong @ 2020-04-07 2:25 UTC (permalink / raw)
To: Aisheng Dong, linux-arm-kernel
Cc: linux-clk, sboyd, mturquette, shawnguo, Fabio Estevam,
dl-linux-imx, kernel
Hi Shawn,
Do you have any comments about this patchset?
BTW, it depends on the latest clock patchset which is pending for quite a long time.
Regards
Aisheng
> From: Dong Aisheng <aisheng.dong@nxp.com>
> Sent: Sunday, November 17, 2019 8:44 PM
> Subject: [PATCH RESEND v3 00/15] arm64: dts: imx8: architecture improvement
> and adding imx8qm support
>
> IMX SCU based platforms (e.g. MX8QM/MX8QXP) are comprised of a number
> of SS (Subsystems), those SS may be shared between different SoCs while most
> of them can be reused like Devices Resources, Clocks, Power domains and etc.
>
> This patch series aims to improve the MX8 architecture to comply with the HW
> design to save a lot of duplicated codes and benefits us a better maintainability
> and scalability in the future.
>
> This patch series depends on another clk new binding series:
>
> NOTE: for the missing undocumented compatible strings for the new SoC
> IMX8QM in this patch series. It will be sent in another patch series later.
>
> ChangeLog:
> v2->v3:
> * use clock-indices property instead of bit-offset property suggested by Shawn
> Guo
> * rebase to latest shawn/for-next
> v1->v2:
> * change to the new two cells scu clock binding, so original adding scu clocks
> patches were removed.
> * Move scu pd node above clk node
>
> Dong Aisheng (15):
> arm64: dts: imx8qxp: add fallback compatible string for scu pd
> arm64: dts: imx8qxp: move scu pd node before scu clock node
> arm64: dts: imx8qxp: orginize dts in subsystems
> arm64: dts: imx8: add lsio lpcg clocks
> arm64: dts: imx8: add conn lpcg clocks
> arm64: dts: imx8: add adma lpcg clocks
> arm64: dts: imx8: switch to two cell scu clock binding
> arm64: dts: imx8: switch to new lpcg clock binding
> arm64: dts: imx8qm: add lsio ss support
> arm64: dts: imx8qm: add conn ss support
> arm64: dts: imx8: split adma ss into dma and audio ss
> arm64: dts: imx8qm: add dma ss support
> arm64: dts: imx: add imx8qm common dts file
> arm64: dts: imx: add imx8qm mek support
> arm64: defconfig: add imx8qm mek support
>
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../boot/dts/freescale/imx8-ss-adma.dtsi | 8 +
> .../boot/dts/freescale/imx8-ss-audio.dtsi | 68 +++
> .../boot/dts/freescale/imx8-ss-conn.dtsi | 187 ++++++++
> .../arm64/boot/dts/freescale/imx8-ss-ddr.dtsi | 19
> + .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 210 +++++++++
> .../boot/dts/freescale/imx8-ss-lsio.dtsi | 311 +++++++++++++
> arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 144 ++++++
> .../boot/dts/freescale/imx8qm-ss-conn.dtsi | 21 +
> .../boot/dts/freescale/imx8qm-ss-dma.dtsi | 51 +++
> .../boot/dts/freescale/imx8qm-ss-lsio.dtsi | 61 +++
> arch/arm64/boot/dts/freescale/imx8qm.dtsi | 180 ++++++++
> .../boot/dts/freescale/imx8qxp-ai_ml.dts | 20 +-
> .../freescale/imx8qxp-colibri-eval-v3.dtsi | 8 +-
> .../boot/dts/freescale/imx8qxp-colibri.dtsi | 12 +-
> arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 12 +-
> .../boot/dts/freescale/imx8qxp-ss-adma.dtsi | 37 ++
> .../boot/dts/freescale/imx8qxp-ss-conn.dtsi | 21 +
> .../boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 61 +++
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 425 ++----------------
> arch/arm64/configs/defconfig | 1 +
> 21 files changed, 1432 insertions(+), 426 deletions(-) create mode 100644
> arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8qm.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
>
> --
> 2.23.0
^ permalink raw reply [flat|nested] 18+ messages in thread