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* [PATCH v1 1/2] clk: qcom: videocc: Update the clock flag for video_cc_vcodec0_core_clk
@ 2020-02-11 12:13 Taniya Das
  2020-02-11 12:13 ` [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk Taniya Das
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Taniya Das @ 2020-02-11 12:13 UTC (permalink / raw)
  To: Stephen Boyd, Michael Turquette, robh
  Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
	linux-kernel, Andy Gross, devicetree, robh+dt, Doug Anderson,
	Taniya Das

The clock disable signal for video_cc_vcodec0_core_clk is tied to
vcodec0_gdsc which is supported in the HW control mode. Thus turning off
the clock would be taken care automatically when the GDSC turns OFF by
hardware and clock driver does not require to poll on the CLK_OFF bit.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 drivers/clk/qcom/videocc-sc7180.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c
index c363c3c..276e5ec 100644
--- a/drivers/clk/qcom/videocc-sc7180.c
+++ b/drivers/clk/qcom/videocc-sc7180.c
@@ -97,7 +97,7 @@ static struct clk_branch video_cc_vcodec0_axi_clk = {

 static struct clk_branch video_cc_vcodec0_core_clk = {
 	.halt_reg = 0x890,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_VOTED,
 	.clkr = {
 		.enable_reg = 0x890,
 		.enable_mask = BIT(0),
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk
  2020-02-11 12:13 [PATCH v1 1/2] clk: qcom: videocc: Update the clock flag for video_cc_vcodec0_core_clk Taniya Das
@ 2020-02-11 12:13 ` Taniya Das
  2020-02-12 23:03   ` Stephen Boyd
  2020-02-12  0:33 ` [PATCH v1 1/2] clk: qcom: videocc: Update the clock flag for video_cc_vcodec0_core_clk Stephen Boyd
  2020-02-12 23:03 ` Stephen Boyd
  2 siblings, 1 reply; 5+ messages in thread
From: Taniya Das @ 2020-02-11 12:13 UTC (permalink / raw)
  To: Stephen Boyd, Michael Turquette, robh
  Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
	linux-kernel, Andy Gross, devicetree, robh+dt, Doug Anderson,
	Taniya Das

The disp_cc_mdss_rscc_ahb_clk is default enabled from hardware and thus
does not require to be marked CRITICAL. This which would allow the RCG to
be turned OFF when the display turns OFF and not blocking XO.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 drivers/clk/qcom/dispcc-sc7180.c | 19 -------------------
 1 file changed, 19 deletions(-)

diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c
index dd7af41..0a5d395 100644
--- a/drivers/clk/qcom/dispcc-sc7180.c
+++ b/drivers/clk/qcom/dispcc-sc7180.c
@@ -592,24 +592,6 @@ static struct clk_branch disp_cc_mdss_rot_clk = {
 	},
 };

-static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
-	.halt_reg = 0x400c,
-	.halt_check = BRANCH_HALT,
-	.clkr = {
-		.enable_reg = 0x400c,
-		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
-			.name = "disp_cc_mdss_rscc_ahb_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
-			},
-			.num_parents = 1,
-			.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
 	.halt_reg = 0x4008,
 	.halt_check = BRANCH_HALT,
@@ -687,7 +669,6 @@ static struct clk_regmap *disp_cc_sc7180_clocks[] = {
 	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
 	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
 	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
-	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
 	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
 	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
 	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH v1 1/2] clk: qcom: videocc: Update the clock flag for video_cc_vcodec0_core_clk
  2020-02-11 12:13 [PATCH v1 1/2] clk: qcom: videocc: Update the clock flag for video_cc_vcodec0_core_clk Taniya Das
  2020-02-11 12:13 ` [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk Taniya Das
@ 2020-02-12  0:33 ` Stephen Boyd
  2020-02-12 23:03 ` Stephen Boyd
  2 siblings, 0 replies; 5+ messages in thread
From: Stephen Boyd @ 2020-02-12  0:33 UTC (permalink / raw)
  To: Michael Turquette, Taniya Das, robh
  Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
	linux-kernel, Andy Gross, devicetree, robh+dt, Doug Anderson,
	Taniya Das

Quoting Taniya Das (2020-02-11 04:13:55)
> The clock disable signal for video_cc_vcodec0_core_clk is tied to
> vcodec0_gdsc which is supported in the HW control mode. Thus turning off
> the clock would be taken care automatically when the GDSC turns OFF by
> hardware and clock driver does not require to poll on the CLK_OFF bit.
> 
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
>  drivers/clk/qcom/videocc-sc7180.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c
> index c363c3c..276e5ec 100644
> --- a/drivers/clk/qcom/videocc-sc7180.c
> +++ b/drivers/clk/qcom/videocc-sc7180.c
> @@ -97,7 +97,7 @@ static struct clk_branch video_cc_vcodec0_axi_clk = {
> 
>  static struct clk_branch video_cc_vcodec0_core_clk = {
>         .halt_reg = 0x890,
> -       .halt_check = BRANCH_HALT,
> +       .halt_check = BRANCH_HALT_VOTED,

Ok. I looked closely and now I notice that some code is using
BRANCH_VOTED and other code is using BRANCH_HALT_VOTED. In the end, it's
the same value. I guess I should remove BRANCH_VOTED from the header
file and make it BIT(7) that's ored in there so that everyone
consistently uses BRANCH_HALT_VOTED.

>         .clkr = {
>                 .enable_reg = 0x890,

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH v1 1/2] clk: qcom: videocc: Update the clock flag for video_cc_vcodec0_core_clk
  2020-02-11 12:13 [PATCH v1 1/2] clk: qcom: videocc: Update the clock flag for video_cc_vcodec0_core_clk Taniya Das
  2020-02-11 12:13 ` [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk Taniya Das
  2020-02-12  0:33 ` [PATCH v1 1/2] clk: qcom: videocc: Update the clock flag for video_cc_vcodec0_core_clk Stephen Boyd
@ 2020-02-12 23:03 ` Stephen Boyd
  2 siblings, 0 replies; 5+ messages in thread
From: Stephen Boyd @ 2020-02-12 23:03 UTC (permalink / raw)
  To: Michael Turquette, Taniya Das, robh
  Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
	linux-kernel, Andy Gross, devicetree, robh+dt, Doug Anderson,
	Taniya Das

Quoting Taniya Das (2020-02-11 04:13:55)
> The clock disable signal for video_cc_vcodec0_core_clk is tied to
> vcodec0_gdsc which is supported in the HW control mode. Thus turning off
> the clock would be taken care automatically when the GDSC turns OFF by
> hardware and clock driver does not require to poll on the CLK_OFF bit.
> 
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---

Applied to clk-fixes

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk
  2020-02-11 12:13 ` [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk Taniya Das
@ 2020-02-12 23:03   ` Stephen Boyd
  0 siblings, 0 replies; 5+ messages in thread
From: Stephen Boyd @ 2020-02-12 23:03 UTC (permalink / raw)
  To: Michael Turquette, Taniya Das, robh
  Cc: David Brown, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
	linux-kernel, Andy Gross, devicetree, robh+dt, Doug Anderson,
	Taniya Das

Quoting Taniya Das (2020-02-11 04:13:56)
> The disp_cc_mdss_rscc_ahb_clk is default enabled from hardware and thus
> does not require to be marked CRITICAL. This which would allow the RCG to
> be turned OFF when the display turns OFF and not blocking XO.
> 
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---

Applied to clk-fixes

^ permalink raw reply	[flat|nested] 5+ messages in thread

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Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-11 12:13 [PATCH v1 1/2] clk: qcom: videocc: Update the clock flag for video_cc_vcodec0_core_clk Taniya Das
2020-02-11 12:13 ` [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk Taniya Das
2020-02-12 23:03   ` Stephen Boyd
2020-02-12  0:33 ` [PATCH v1 1/2] clk: qcom: videocc: Update the clock flag for video_cc_vcodec0_core_clk Stephen Boyd
2020-02-12 23:03 ` Stephen Boyd

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