From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<srv_heupstream@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH v6 20/22] clk: mediatek: Add MT8192 scp adsp clock support
Date: Tue, 22 Dec 2020 21:09:45 +0800 [thread overview]
Message-ID: <1608642587-15634-21-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1608642587-15634-1-git-send-email-weiyi.lu@mediatek.com>
Add MT8192 scp adsp clock provider
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 6 ++++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-scp_adsp.c | 50 ++++++++++++++++++++++++++++++
3 files changed, 57 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8192-scp_adsp.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index aba662f..1009e1f 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -551,6 +551,12 @@ config COMMON_CLK_MT8192_MSDC
help
This driver supports MediaTek MT8192 msdc and msdc_top clocks.
+config COMMON_CLK_MT8192_SCP_ADSP
+ bool "Clock driver for MediaTek MT8192 scp_adsp"
+ depends on COMMON_CLK_MT8192
+ help
+ This driver supports MediaTek MT8192 scp_adsp clocks.
+
config COMMON_CLK_MT8516
bool "Clock driver for MediaTek MT8516"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 8e4e343..a336fe7 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -77,5 +77,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MDPSYS) += clk-mt8192-mdp.o
obj-$(CONFIG_COMMON_CLK_MT8192_MFGCFG) += clk-mt8192-mfg.o
obj-$(CONFIG_COMMON_CLK_MT8192_MMSYS) += clk-mt8192-mm.o
obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o
+obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o
obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c
new file mode 100644
index 0000000..4bc2403
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2020 MediaTek Inc.
+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8192-clk.h>
+
+static const struct mtk_gate_regs scp_adsp_cg_regs = {
+ .set_ofs = 0x180,
+ .clr_ofs = 0x180,
+ .sta_ofs = 0x180,
+};
+
+#define GATE_SCP_ADSP(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &scp_adsp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+static const struct mtk_gate scp_adsp_clks[] = {
+ GATE_SCP_ADSP(CLK_SCP_ADSP_AUDIODSP, "scp_adsp_audiodsp", "adsp_sel", 0),
+};
+
+static const struct mtk_clk_desc scp_adsp_desc = {
+ .clks = scp_adsp_clks,
+ .num_clks = ARRAY_SIZE(scp_adsp_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8192_scp_adsp[] = {
+ {
+ .compatible = "mediatek,mt8192-scp_adsp",
+ .data = &scp_adsp_desc,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct platform_driver clk_mt8192_scp_adsp_drv = {
+ .probe = mtk_clk_simple_probe,
+ .driver = {
+ .name = "clk-mt8192-scp_adsp",
+ .of_match_table = of_match_clk_mt8192_scp_adsp,
+ },
+};
+
+builtin_platform_driver(clk_mt8192_scp_adsp_drv);
--
1.8.1.1.dirty
next prev parent reply other threads:[~2020-12-22 13:12 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-22 13:09 [PATCH v6 00/22] Mediatek MT8192 clock support Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller Weiyi Lu
2021-02-10 12:19 ` Matthias Brugger
2021-02-18 1:40 ` Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 02/22] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 03/22] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 04/22] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 05/22] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 06/22] clk: mediatek: Add dt-bindings of MT8192 clocks Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 07/22] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
2021-01-06 10:35 ` Ikjoon Jang
2020-12-22 13:09 ` [PATCH v6 08/22] clk: mediatek: Add configurable enable control to mtk_pll_data Weiyi Lu
2021-01-06 10:37 ` Ikjoon Jang
2020-12-22 13:09 ` [PATCH v6 09/22] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 10/22] clk: mediatek: Add MT8192 basic clocks support Weiyi Lu
2021-01-06 10:25 ` Ikjoon Jang
2021-01-06 10:42 ` Weiyi Lu
2021-01-06 10:52 ` Ikjoon Jang
2021-01-06 11:06 ` Weiyi Lu
2021-01-07 3:00 ` Ikjoon Jang
2021-02-10 12:46 ` Matthias Brugger
2021-02-18 1:59 ` Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 11/22] clk: mediatek: Add MT8192 audio clock support Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 12/22] clk: mediatek: Add MT8192 camsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 13/22] clk: mediatek: Add MT8192 imgsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 14/22] clk: mediatek: Add MT8192 imp i2c wrapper " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 15/22] clk: mediatek: Add MT8192 ipesys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 16/22] clk: mediatek: Add MT8192 mdpsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 17/22] clk: mediatek: Add MT8192 mfgcfg " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 18/22] clk: mediatek: Add MT8192 mmsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 19/22] clk: mediatek: Add MT8192 msdc " Weiyi Lu
2020-12-22 13:09 ` Weiyi Lu [this message]
2020-12-22 13:09 ` [PATCH v6 21/22] clk: mediatek: Add MT8192 vdecsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 22/22] clk: mediatek: Add MT8192 vencsys " Weiyi Lu
2021-01-13 7:18 ` [PATCH v6 00/22] Mediatek MT8192 " James Liao
2021-02-09 1:00 ` Stephen Boyd
2021-02-18 1:25 ` Weiyi Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1608642587-15634-21-git-send-email-weiyi.lu@mediatek.com \
--to=weiyi.lu@mediatek.com \
--cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
--cc=drinkcat@chromium.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=srv_heupstream@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).