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From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Ikjoon Jang <ikjn@chromium.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
	Nicolas Boichat <drinkcat@chromium.org>,
	srv_heupstream <srv_heupstream@mediatek.com>,
	"open list" <linux-kernel@vger.kernel.org>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	"moderated list:ARM/Mediatek SoC support" 
	<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
	"moderated list:ARM/Mediatek SoC support" 
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v6 10/22] clk: mediatek: Add MT8192 basic clocks support
Date: Wed, 6 Jan 2021 18:42:01 +0800	[thread overview]
Message-ID: <1609929721.7491.3.camel@mtksdaap41> (raw)
In-Reply-To: <CAATdQgC_BnZywDxaZgmF72VRoAZ-1vFGrPD9GL4uEBhsKQTxnQ@mail.gmail.com>

On Wed, 2021-01-06 at 18:25 +0800, Ikjoon Jang wrote:
> On Tue, Dec 22, 2020 at 9:14 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote:
> >
> > Add MT8192 basic clock providers, include topckgen, apmixedsys,
> > infracfg and pericfg.
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> >  drivers/clk/mediatek/Kconfig      |    8 +
> >  drivers/clk/mediatek/Makefile     |    1 +
> >  drivers/clk/mediatek/clk-mt8192.c | 1326 +++++++++++++++++++++++++++++++++++++
> >  drivers/clk/mediatek/clk-mux.h    |   15 +
> >  4 files changed, 1350 insertions(+)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8192.c
> >
> 
> <snip>
> 
> > diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
> > index f5625f4..afbc7df 100644
> > --- a/drivers/clk/mediatek/clk-mux.h
> > +++ b/drivers/clk/mediatek/clk-mux.h
> > @@ -77,6 +77,21 @@ struct mtk_mux {
> >                         _width, _gate, _upd_ofs, _upd,                  \
> >                         CLK_SET_RATE_PARENT)
> >
> > +#define MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,          \
> > +                       _mux_set_ofs, _mux_clr_ofs, _shift, _width,     \
> > +                       _upd_ofs, _upd, _flags)                         \
> > +               GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,  \
> > +                       _mux_set_ofs, _mux_clr_ofs, _shift, _width,     \
> > +                       0, _upd_ofs, _upd, _flags,                      \
> > +                       mtk_mux_clr_set_upd_ops)
> > +
> > +#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,                        \
> > +                       _mux_set_ofs, _mux_clr_ofs, _shift, _width,     \
> > +                       _upd_ofs, _upd)                                 \
> > +               MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents,             \
> > +                       _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift,   \
> > +                       _width, _upd_ofs, _upd, CLK_SET_RATE_PARENT)
> > +
> 
> conflicts, these macros are already existed in upstream.

really? These two macros don't show up in 5.11-rc1 yet.

> >  struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
> >                                  struct regmap *regmap,
> >                                  spinlock_t *lock);
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek


  reply	other threads:[~2021-01-06 10:48 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-22 13:09 [PATCH v6 00/22] Mediatek MT8192 clock support Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller Weiyi Lu
2021-02-10 12:19   ` Matthias Brugger
2021-02-18  1:40     ` Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 02/22] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 03/22] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 04/22] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 05/22] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 06/22] clk: mediatek: Add dt-bindings of MT8192 clocks Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 07/22] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
2021-01-06 10:35   ` Ikjoon Jang
2020-12-22 13:09 ` [PATCH v6 08/22] clk: mediatek: Add configurable enable control to mtk_pll_data Weiyi Lu
2021-01-06 10:37   ` Ikjoon Jang
2020-12-22 13:09 ` [PATCH v6 09/22] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 10/22] clk: mediatek: Add MT8192 basic clocks support Weiyi Lu
2021-01-06 10:25   ` Ikjoon Jang
2021-01-06 10:42     ` Weiyi Lu [this message]
2021-01-06 10:52       ` Ikjoon Jang
2021-01-06 11:06         ` Weiyi Lu
2021-01-07  3:00           ` Ikjoon Jang
2021-02-10 12:46   ` Matthias Brugger
2021-02-18  1:59     ` Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 11/22] clk: mediatek: Add MT8192 audio clock support Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 12/22] clk: mediatek: Add MT8192 camsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 13/22] clk: mediatek: Add MT8192 imgsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 14/22] clk: mediatek: Add MT8192 imp i2c wrapper " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 15/22] clk: mediatek: Add MT8192 ipesys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 16/22] clk: mediatek: Add MT8192 mdpsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 17/22] clk: mediatek: Add MT8192 mfgcfg " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 18/22] clk: mediatek: Add MT8192 mmsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 19/22] clk: mediatek: Add MT8192 msdc " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 20/22] clk: mediatek: Add MT8192 scp adsp " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 21/22] clk: mediatek: Add MT8192 vdecsys " Weiyi Lu
2020-12-22 13:09 ` [PATCH v6 22/22] clk: mediatek: Add MT8192 vencsys " Weiyi Lu
2021-01-13  7:18 ` [PATCH v6 00/22] Mediatek MT8192 " James Liao
2021-02-09  1:00 ` Stephen Boyd
2021-02-18  1:25   ` Weiyi Lu

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