* [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes
@ 2020-12-22 13:40 Weiyi Lu
2020-12-22 13:40 ` [PATCH 1/2] arm64: dts: mediatek: Add mt8192 clock controllers Weiyi Lu
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Weiyi Lu @ 2020-12-22 13:40 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
linux-clk, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Weiyi Lu
This series is based on v5.10-rc1, MT8192 dts v6[1] and
MT8192 clock v6 series[2].
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=373899
[2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=405295
Weiyi Lu (2):
arm64: dts: mediatek: Add mt8192 clock controllers
arm64: dts: mediatek: Correct UART0 bus clock of MT8192
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 165 ++++++++++++++++++++++-
1 file changed, 164 insertions(+), 1 deletion(-)
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] arm64: dts: mediatek: Add mt8192 clock controllers
2020-12-22 13:40 [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes Weiyi Lu
@ 2020-12-22 13:40 ` Weiyi Lu
2020-12-22 13:40 ` [PATCH 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192 Weiyi Lu
[not found] ` <4536e0a3-8e64-d2b0-df83-33705d10359a@gmail.com>
2 siblings, 0 replies; 6+ messages in thread
From: Weiyi Lu @ 2020-12-22 13:40 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
linux-clk, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Weiyi Lu
Add clock controller nodes for SoC mt8192
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 163 +++++++++++++++++++++++++++++++
1 file changed, 163 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e12e024..92dcfbd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -5,6 +5,7 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -213,6 +214,24 @@
};
};
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8192-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8192-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8192-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
pio: pinctrl@10005000 {
compatible = "mediatek,mt8192-pinctrl";
reg = <0 0x10005000 0 0x1000>,
@@ -238,6 +257,12 @@
#interrupt-cells = <2>;
};
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8192-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
systimer: timer@10017000 {
compatible = "mediatek,mt8192-timer",
"mediatek,mt6765-timer";
@@ -247,6 +272,12 @@
clock-names = "clk13m";
};
+ scp_adsp: syscon@10720000 {
+ compatible = "mediatek,mt8192-scp_adsp", "syscon";
+ reg = <0 0x10720000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt8192-uart",
"mediatek,mt6577-uart";
@@ -267,6 +298,12 @@
status = "disabled";
};
+ imp_iic_wrap_c: syscon@11007000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_c", "syscon";
+ reg = <0 0x11007000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
spi0: spi@1100a000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
@@ -379,6 +416,12 @@
status = "disabled";
};
+ audsys: syscon@11210000 {
+ compatible = "mediatek,mt8192-audsys", "syscon";
+ reg = <0 0x11210000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c3: i2c3@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
@@ -392,6 +435,12 @@
status = "disabled";
};
+ imp_iic_wrap_e: syscon@11cb1000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_e", "syscon";
+ reg = <0 0x11cb1000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c7: i2c7@11d00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d00000 0 0x1000>,
@@ -431,6 +480,12 @@
status = "disabled";
};
+ imp_iic_wrap_s: syscon@11d03000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_s", "syscon";
+ reg = <0 0x11d03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c1: i2c1@11d20000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d20000 0 0x1000>,
@@ -470,6 +525,12 @@
status = "disabled";
};
+ imp_iic_wrap_ws: syscon@11d23000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_ws", "syscon";
+ reg = <0 0x11d23000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c5: i2c5@11e00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11e00000 0 0x1000>,
@@ -483,6 +544,12 @@
status = "disabled";
};
+ imp_iic_wrap_w: syscon@11e01000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_w", "syscon";
+ reg = <0 0x11e01000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
i2c0: i2c0@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
@@ -508,5 +575,101 @@
#size-cells = <0>;
status = "disabled";
};
+
+ imp_iic_wrap_n: syscon@11f02000 {
+ compatible = "mediatek,mt8192-imp_iic_wrap_n", "syscon";
+ reg = <0 0x11f02000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ msdc_top: syscon@11f10000 {
+ compatible = "mediatek,mt8192-msdc_top", "syscon";
+ reg = <0 0x11f10000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ msdc: syscon@11f60000 {
+ compatible = "mediatek,mt8192-msdc", "syscon";
+ reg = <0 0x11f60000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mfgcfg: syscon@13fbf000 {
+ compatible = "mediatek,mt8192-mfgcfg", "syscon";
+ reg = <0 0x13fbf000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8192-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: syscon@15020000 {
+ compatible = "mediatek,mt8192-imgsys", "syscon";
+ reg = <0 0x15020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys2: syscon@15820000 {
+ compatible = "mediatek,mt8192-imgsys2", "syscon";
+ reg = <0 0x15820000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_soc: syscon@1600f000 {
+ compatible = "mediatek,mt8192-vdecsys_soc", "syscon";
+ reg = <0 0x1600f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon@1602f000 {
+ compatible = "mediatek,mt8192-vdecsys", "syscon";
+ reg = <0 0x1602f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: syscon@17000000 {
+ compatible = "mediatek,mt8192-vencsys", "syscon";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon@1a000000 {
+ compatible = "mediatek,mt8192-camsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawa: syscon@1a04f000 {
+ compatible = "mediatek,mt8192-camsys_rawa", "syscon";
+ reg = <0 0x1a04f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawb: syscon@1a06f000 {
+ compatible = "mediatek,mt8192-camsys_rawb", "syscon";
+ reg = <0 0x1a06f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawc: syscon@1a08f000 {
+ compatible = "mediatek,mt8192-camsys_rawc", "syscon";
+ reg = <0 0x1a08f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipesys: syscon@1b000000 {
+ compatible = "mediatek,mt8192-ipesys", "syscon";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mdpsys: syscon@1f000000 {
+ compatible = "mediatek,mt8192-mdpsys", "syscon";
+ reg = <0 0x1f000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
};
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
2020-12-22 13:40 [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes Weiyi Lu
2020-12-22 13:40 ` [PATCH 1/2] arm64: dts: mediatek: Add mt8192 clock controllers Weiyi Lu
@ 2020-12-22 13:40 ` Weiyi Lu
2021-01-31 13:29 ` Matthias Brugger
[not found] ` <4536e0a3-8e64-d2b0-df83-33705d10359a@gmail.com>
2 siblings, 1 reply; 6+ messages in thread
From: Weiyi Lu @ 2020-12-22 13:40 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
linux-clk, srv_heupstream, Project_Global_Chrome_Upstream_Group,
Weiyi Lu
infra_uart0 clock is the real one what uart0 uses as bus clock.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 92dcfbd..ac5dca6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -283,7 +283,7 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
--
1.8.1.1.dirty
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
2020-12-22 13:40 ` [PATCH 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192 Weiyi Lu
@ 2021-01-31 13:29 ` Matthias Brugger
0 siblings, 0 replies; 6+ messages in thread
From: Matthias Brugger @ 2021-01-31 13:29 UTC (permalink / raw)
To: Weiyi Lu, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
linux-clk, srv_heupstream, Project_Global_Chrome_Upstream_Group
On 22/12/2020 14:40, Weiyi Lu wrote:
> infra_uart0 clock is the real one what uart0 uses as bus clock.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 92dcfbd..ac5dca6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -283,7 +283,7 @@
> "mediatek,mt6577-uart";
> reg = <0 0x11002000 0 0x1000>;
> interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
Please update the clocks for all nodes to use the clock driver, not just uart or
uart0.
Thanks,
Matthias
> clock-names = "baud", "bus";
> status = "disabled";
> };
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes
[not found] ` <4536e0a3-8e64-d2b0-df83-33705d10359a@gmail.com>
@ 2021-02-01 9:31 ` Weiyi Lu
2021-02-01 10:15 ` Matthias Brugger
0 siblings, 1 reply; 6+ messages in thread
From: Weiyi Lu @ 2021-02-01 9:31 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Nicolas Boichat, devicetree, linux-arm-kernel,
linux-kernel, linux-mediatek, linux-clk, srv_heupstream,
Project_Global_Chrome_Upstream_Group
On Sun, 2021-01-31 at 14:27 +0100, Matthias Brugger wrote:
>
> On 22/12/2020 14:40, Weiyi Lu wrote:
> > This series is based on v5.10-rc1, MT8192 dts v6[1] and
> > MT8192 clock v6 series[2].
> >
> > [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=373899
> > [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=405295
> >
>
> [1] is already mainline. You could add this patch as a new one to [2]. But
> please try to improve the series, before sending just a new version with this
> patch added.
>
> Regards,
> Matthias
>
Hi Matthias,
Actually I'm a little confused now. Stephen suggested me to send clock
dts separately because dts may not go through his tree.
So I separated it from the MT8192 clock series since clock v6.
What do you suggest me to do next time?
> > Weiyi Lu (2):
> > arm64: dts: mediatek: Add mt8192 clock controllers
> > arm64: dts: mediatek: Correct UART0 bus clock of MT8192
> >
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 165 ++++++++++++++++++++++-
> > 1 file changed, 164 insertions(+), 1 deletion(-)
> >
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes
2021-02-01 9:31 ` [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes Weiyi Lu
@ 2021-02-01 10:15 ` Matthias Brugger
0 siblings, 0 replies; 6+ messages in thread
From: Matthias Brugger @ 2021-02-01 10:15 UTC (permalink / raw)
To: Weiyi Lu
Cc: Rob Herring, Nicolas Boichat, devicetree, linux-arm-kernel,
linux-kernel, linux-mediatek, linux-clk, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi Weiyi,
On 01/02/2021 10:31, Weiyi Lu wrote:
> On Sun, 2021-01-31 at 14:27 +0100, Matthias Brugger wrote:
>>
>> On 22/12/2020 14:40, Weiyi Lu wrote:
>>> This series is based on v5.10-rc1, MT8192 dts v6[1] and
>>> MT8192 clock v6 series[2].
>>>
>>> [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=373899
>>> [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=405295
>>>
>>
>> [1] is already mainline. You could add this patch as a new one to [2]. But
>> please try to improve the series, before sending just a new version with this
>> patch added.
>>
>> Regards,
>> Matthias
>>
> Hi Matthias,
>
> Actually I'm a little confused now. Stephen suggested me to send clock
> dts separately because dts may not go through his tree.
> So I separated it from the MT8192 clock series since clock v6.
> What do you suggest me to do next time?
>
Yes, now that you mention that, I remember...
OK, then I'd propose to resend the DTS patches once the clock patches are accepted.
Regards,
Matthias
>>> Weiyi Lu (2):
>>> arm64: dts: mediatek: Add mt8192 clock controllers
>>> arm64: dts: mediatek: Correct UART0 bus clock of MT8192
>>>
>>> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 165 ++++++++++++++++++++++-
>>> 1 file changed, 164 insertions(+), 1 deletion(-)
>>>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-02-01 10:16 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2020-12-22 13:40 [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes Weiyi Lu
2020-12-22 13:40 ` [PATCH 1/2] arm64: dts: mediatek: Add mt8192 clock controllers Weiyi Lu
2020-12-22 13:40 ` [PATCH 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192 Weiyi Lu
2021-01-31 13:29 ` Matthias Brugger
[not found] ` <4536e0a3-8e64-d2b0-df83-33705d10359a@gmail.com>
2021-02-01 9:31 ` [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes Weiyi Lu
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