From: Jerome Brunet <jbrunet@baylibre.com>
To: Anand Moon <linux.amoon@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Kevin Hilman <khilman@baylibre.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org
Subject: Re: [PATCHv1 3/3] clk: meson: g12a: set cpu clock divider flags too CLK_IS_CRITICAL
Date: Mon, 17 Feb 2020 09:02:21 +0100 [thread overview]
Message-ID: <1jmu9hzlo2.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <20200216173446.1823-4-linux.amoon@gmail.com>
On Sun 16 Feb 2020 at 18:34, Anand Moon <linux.amoon@gmail.com> wrote:
> Odroid N2 would fail to boot using microSD unless we set
> cpu freq clk divider flags to CLK_IS_CRITICAL to avoid stalling of
> cpu when booting, most likely because of PWM module linked to
Where did you see a PWM ?
> the CPU for DVFS is getting disabled in between the late_init call,
between the late_init call and what ?
> so gaiting the clock source shuts down the power to the codes.
what code ?
> Setting clk divider flags to CLK_IS_CRITICAL help resolve the issue.
>
> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Cc: Jerome Brunet <jbrunet@baylibre.com>
> Cc: Neil Armstrong <narmstrong@baylibre.com>
> Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
>
> Following Neil's suggestion, I have prepared this patch.
> https://patchwork.kernel.org/patch/11177441/#22964889
> ---
> drivers/clk/meson/g12a.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
> index d2760a021301..accae3695fe5 100644
> --- a/drivers/clk/meson/g12a.c
> +++ b/drivers/clk/meson/g12a.c
> @@ -283,6 +283,7 @@ static struct clk_fixed_factor g12a_fclk_div2_div = {
> .ops = &clk_fixed_factor_ops,
> .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
> .num_parents = 1,
> + .flags = CLK_IS_CRITICAL,
This makes no sense for because:
* This clock cannot gate and none of its parents can either. IOW, the
output of this clock is never disabled.
* I cannot guess the relation between fdiv2 and the commit description
> },
> };
>
> @@ -681,7 +682,7 @@ static struct clk_regmap g12b_cpub_clk = {
> &g12a_sys_pll.hw
> },
> .num_parents = 2,
> - .flags = CLK_SET_RATE_PARENT,
> + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
Why not. Neil what do you think of this ?
If nothing is claiming this clock and enabling it then I suppose it
could make sense.
> },
> };
next prev parent reply other threads:[~2020-02-17 8:02 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-16 17:34 [PATCHv1 0/3] Odroid N2 failes to boot using upstream kernel using microSD card Anand Moon
2020-02-16 17:34 ` [PATCHv1 1/3] arm64: dts: meson: Add missing regulator linked to VDDAO_3V3 regulator to FLASH_VDD Anand Moon
2020-02-16 17:34 ` [PATCHv1 2/3] arm64: dts: meson: Add missing regulator linked to VCCV5 regulator to VDDIO_C/TF_IO Anand Moon
2020-02-17 7:49 ` Jerome Brunet
2020-02-16 17:34 ` [PATCHv1 3/3] clk: meson: g12a: set cpu clock divider flags too CLK_IS_CRITICAL Anand Moon
2020-02-17 8:02 ` Jerome Brunet [this message]
2020-02-17 8:51 ` Anand Moon
2020-02-17 13:30 ` Anand Moon
2020-02-20 21:15 ` Martin Blumenstingl
2020-02-23 13:34 ` Anand Moon
2020-02-24 9:31 ` Jerome Brunet
2020-02-24 10:17 ` Anand Moon
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