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From: Anand Moon <linux.amoon@gmail.com>
To: Jerome Brunet <jbrunet@baylibre.com>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Neil Armstrong <narmstrong@baylibre.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Kevin Hilman <khilman@baylibre.com>,
	devicetree <devicetree@vger.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	linux-amlogic@lists.infradead.org,
	Linux Kernel <linux-kernel@vger.kernel.org>,
	"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>
Subject: Re: [PATCHv1 3/3] clk: meson: g12a: set cpu clock divider flags too CLK_IS_CRITICAL
Date: Mon, 24 Feb 2020 15:47:29 +0530	[thread overview]
Message-ID: <CANAwSgSKUEJEe_H6XnKmHZNtB549jLau=TY00jzCHAC8zb_7oA@mail.gmail.com> (raw)
In-Reply-To: <1jo8togwmi.fsf@starbuckisacylon.baylibre.com>

Hi  Jerome,

On Mon, 24 Feb 2020 at 15:01, Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>
> On Sun 23 Feb 2020 at 14:34, Anand Moon <linux.amoon@gmail.com> wrote:
>
> > Hi Martin / Jerome / Neil,
> >
> > On Fri, 21 Feb 2020 at 02:45, Martin Blumenstingl
> > <martin.blumenstingl@googlemail.com> wrote:
> >>
> >> Hi Anand,
> >>
> >> On Mon, Feb 17, 2020 at 2:30 PM Anand Moon <linux.amoon@gmail.com> wrote:
> >> [...]
> >> > > > @@ -681,7 +682,7 @@ static struct clk_regmap g12b_cpub_clk = {
> >> > > >                       &g12a_sys_pll.hw
> >> > > >               },
> >> > > >               .num_parents = 2,
> >> > > > -             .flags = CLK_SET_RATE_PARENT,
> >> > > > +             .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> >> > >
> >> > > Why not. Neil what do you think of this ?
> >> > > If nothing is claiming this clock and enabling it then I suppose it
> >> > > could make sense.
> >> > >
> >> > I would like core developers to handle this.
> >> > Sorry for the noise.
> >> can you please resend this patch with only the change to g12b_cpub_clk?
> >> I have no G12B board myself so it would be great if you could take care of this!
> >>
> >>
> >> Martin
> >
> > Thanks, yes I will try again, but I have a question.
> >
> > On eMMC module  *cpub_clk* is not getting enabled, see below is
> > clk_summay of eMMC.
>
> I'm sorry but I don't understand the link between the cpu clock of the
> second cluster and MMC.
>
> > [...]
> >           fclk_div2_div               1        1        0   999999985
> >         0     0  50000
> >              fclk_div2                2        2        0   999999985
> >         0     0  50000
> >                 ff3f0000.ethernet#m250_sel       1        1        0
> > 999999985          0     0  50000
> >                    ff3f0000.ethernet#m250_div       1        1
> > 0   249999997          0     0  50000
> >                       ff3f0000.ethernet#fixed_div2       1        1
> >     0   124999998          0     0  50000
> >                          ff3f0000.ethernet#rgmii_tx_en       1
> > 1        0   124999998          0     0  50000
> >                 ffe07000.mmc#mux       1        1        0   999999985
> >          0     0  50000
> >                    ffe07000.mmc#div       1        1        0
> > 199999997          0     0  50000
> >                 cpub_clk_dyn1_sel       0        0        0
> > 999999985          0     0  50000
> >                    cpub_clk_dyn1       0        0        0   999999985
> >          0     0  50000
> >                       cpub_clk_dyn       0        0        0
> > 999999985          0     0  50000
> >                          cpub_clk       0        0        0
> > 999999985          0     0  50000
> >                             cpub_clk_div8       0        0        0
> > 124999998          0     0  50000
> >                             cpub_clk_div7       0        0        0
> > 142857140          0     0  50000
> >                             cpub_clk_div6       0        0        0
> > 166666664          0     0  50000
> >                                cpub_clk_trace_sel       0        0
> >    0   166666664          0     0  50000
> >                                   cpub_clk_trace       0        0
> >   0   166666664          0     0  50000
> >                             cpub_clk_div5       0        0        0
> > 199999997          0     0  50000
> >                                cpub_clk_apb_sel       0        0
> >  0   199999997          0     0  50000
> >                                   cpub_clk_apb       0        0
> > 0   199999997          0     0  50000
> >                             cpub_clk_div4       0        0        0
> > 249999996          0     0  50000
> >                             cpub_clk_div3       0        0        0
> > 333333328          0     0  50000
> >                                cpub_clk_atb_sel       0        0
> >  0   333333328          0     0  50000
> >                                   cpub_clk_atb       0        0
> > 0   333333328          0     0  50000
> >                             cpub_clk_div2       0        0        0
> > 499999992          0     0  50000
> >                                cpub_clk_axi_sel       0        0
> >  0   499999992          0     0  50000
> >                                   cpub_clk_axi       0        0
> > 0   499999992          0     0  50000
> >                             cpub_clk_div16_en       0        0
> > 0   999999985          0     0  50000
> >                                cpub_clk_div16       0        0
> > 0    62499999          0     0  50000
>
> I can't read that.
>
> >
> > After enable *cpub_clk* flags with
> > .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> > this clk is enabled on microSD card see clk_summary below.
>
> Again, I don't get the relationship between cpub and sdcard (or eMMC)
>

Yes their is not relation with the cpub and sdcard and eMMC,
I understood  that cpub_clk is not getting enable which is causing
the staling at booting using sdcard.

sorry about this logs.

> > [...]
> >          fclk_div2_div               1        1        0   999999985
> >        0     0  50000
> >              fclk_div2                3        3        0   999999985
> >         0     0  50000
> >                 ff3f0000.ethernet#m250_sel       1        1        0
> > 999999985          0     0  50000
> >                    ff3f0000.ethernet#m250_div       1        1
> > 0   249999997          0     0  50000
> >                       ff3f0000.ethernet#fixed_div2       1        1
> >     0   124999998          0     0  50000
> >                          ff3f0000.ethernet#rgmii_tx_en       1
> > 1        0   124999998          0     0  50000
> >                 ffe05000.sd#mux       1        1        0   999999985
> >         0     0  50000
> >                    ffe05000.sd#div       1        1        0
> > 50000000          0     0  50000
> >                 cpub_clk_dyn1_sel       1        1        0
> > 999999985          0     0  50000
> >                    cpub_clk_dyn1       1        1        0   999999985
> >          0     0  50000
> >                       cpub_clk_dyn       1        1        0
> > 999999985          0     0  50000
> >                          cpub_clk       1        1        0
> > 999999985          0     0  50000
> >                             cpub_clk_div8       0        0        0
> > 124999998          0     0  50000
> >                             cpub_clk_div7       0        0        0
> > 142857140          0     0  50000
> >                             cpub_clk_div6       0        0        0
> > 166666664          0     0  50000
> >                                cpub_clk_trace_sel       0        0
> >    0   166666664          0     0  50000
> >                                   cpub_clk_trace       0        0
> >   0   166666664          0     0  50000
> >                             cpub_clk_div5       0        0        0
> > 199999997          0     0  50000
> >                                cpub_clk_apb_sel       0        0
> >  0   199999997          0     0  50000
> >                                   cpub_clk_apb       0        0
> > 0   199999997          0     0  50000
> >                             cpub_clk_div4       0        0        0
> > 249999996          0     0  50000
> >                             cpub_clk_div3       0        0        0
> > 333333328          0     0  50000
> >                                cpub_clk_atb_sel       0        0
> >  0   333333328          0     0  50000
> >                                   cpub_clk_atb       0        0
> > 0   333333328          0     0  50000
> >                             cpub_clk_div2       0        0        0
> > 499999992          0     0  50000
> >                                cpub_clk_axi_sel       0        0
> >  0   499999992          0     0  50000
> >                                   cpub_clk_axi       0        0
> > 0   499999992          0     0  50000
> >                             cpub_clk_div16_en       0        0
> > 0   999999985          0     0  50000
> >                                cpub_clk_div16       0        0
> > 0    62499999          0     0  50000
> >                    cpub_clk_dyn1_div       0        0        0
> > 999999985          0     0  50000
> >
> > Is this correct approach to set the flags to enable *cpub_clk*.
> > .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> >
> > What I meant is their *Dyn_enable[26]* field for enable/disable for
> > HHI_SYS_CPU_CLK_CNTL0 and HHI_SYS_CPUB_CLK_CNTL clk controller.
> > in the S922X datasheets which could help resolve this issue.
> > Any thought on this.
>
> I sorry but I'm just lost. I don't understand anything above so I can't
> comment.

I am not able to express my self clearly,
I will try to submit the patch by enable cpub_clk with following flags.

 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,

-Anand

      reply	other threads:[~2020-02-24 10:17 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-16 17:34 [PATCHv1 0/3] Odroid N2 failes to boot using upstream kernel using microSD card Anand Moon
2020-02-16 17:34 ` [PATCHv1 1/3] arm64: dts: meson: Add missing regulator linked to VDDAO_3V3 regulator to FLASH_VDD Anand Moon
2020-02-16 17:34 ` [PATCHv1 2/3] arm64: dts: meson: Add missing regulator linked to VCCV5 regulator to VDDIO_C/TF_IO Anand Moon
2020-02-17  7:49   ` Jerome Brunet
2020-02-16 17:34 ` [PATCHv1 3/3] clk: meson: g12a: set cpu clock divider flags too CLK_IS_CRITICAL Anand Moon
2020-02-17  8:02   ` Jerome Brunet
2020-02-17  8:51     ` Anand Moon
2020-02-17 13:30     ` Anand Moon
2020-02-20 21:15       ` Martin Blumenstingl
2020-02-23 13:34         ` Anand Moon
2020-02-24  9:31           ` Jerome Brunet
2020-02-24 10:17             ` Anand Moon [this message]

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