* [PATCH] clk: renesas: r8a774c0: Correct parent clock of DU
@ 2019-01-21 13:14 Geert Uytterhoeven
2019-01-21 13:15 ` Geert Uytterhoeven
2019-01-21 13:47 ` Chris Paterson
0 siblings, 2 replies; 4+ messages in thread
From: Geert Uytterhoeven @ 2019-01-21 13:14 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Fabrizio Castro, Biju Das
Cc: linux-renesas-soc, linux-clk, Geert Uytterhoeven
According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
the parent clock of the DU module clocks on RZ/G2 is S1D1.
Fixes: 906e0a4a6d1ef2d3 ("clk: renesas: cpg-mssr: Add r8a774c0 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in clk-renesas-for-v5.1.
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 28bcc8105d579611..4f3111b3113ecce8 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -175,8 +175,8 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D4),
DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D4),
DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0),
- DEF_MOD("du1", 723, R8A774C0_CLK_S2D1),
- DEF_MOD("du0", 724, R8A774C0_CLK_S2D1),
+ DEF_MOD("du1", 723, R8A774C0_CLK_S1D1),
+ DEF_MOD("du0", 724, R8A774C0_CLK_S1D1),
DEF_MOD("lvds", 727, R8A774C0_CLK_S2D1),
DEF_MOD("vin5", 806, R8A774C0_CLK_S1D2),
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] clk: renesas: r8a774c0: Correct parent clock of DU
2019-01-21 13:14 [PATCH] clk: renesas: r8a774c0: Correct parent clock of DU Geert Uytterhoeven
@ 2019-01-21 13:15 ` Geert Uytterhoeven
2019-01-23 9:56 ` Simon Horman
2019-01-21 13:47 ` Chris Paterson
1 sibling, 1 reply; 4+ messages in thread
From: Geert Uytterhoeven @ 2019-01-21 13:15 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Fabrizio Castro, Biju Das,
Linux-Renesas, linux-clk
On Mon, Jan 21, 2019 at 2:14 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
> the parent clock of the DU module clocks on RZ/G2 is S1D1.
Oops, "RZ/G2E".
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] clk: renesas: r8a774c0: Correct parent clock of DU
2019-01-21 13:15 ` Geert Uytterhoeven
@ 2019-01-23 9:56 ` Simon Horman
0 siblings, 0 replies; 4+ messages in thread
From: Simon Horman @ 2019-01-23 9:56 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
Fabrizio Castro, Biju Das, Linux-Renesas, linux-clk
On Mon, Jan 21, 2019 at 02:15:07PM +0100, Geert Uytterhoeven wrote:
> On Mon, Jan 21, 2019 at 2:14 PM Geert Uytterhoeven
> <geert+renesas@glider.be> wrote:
> > According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
> > the parent clock of the DU module clocks on RZ/G2 is S1D1.
>
> Oops, "RZ/G2E".
That aside,
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH] clk: renesas: r8a774c0: Correct parent clock of DU
2019-01-21 13:14 [PATCH] clk: renesas: r8a774c0: Correct parent clock of DU Geert Uytterhoeven
2019-01-21 13:15 ` Geert Uytterhoeven
@ 2019-01-21 13:47 ` Chris Paterson
1 sibling, 0 replies; 4+ messages in thread
From: Chris Paterson @ 2019-01-21 13:47 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
Fabrizio Castro, Biju Das
Cc: linux-renesas-soc, linux-clk
> From: linux-renesas-soc-owner@vger.kernel.org <linux-renesas-soc-
> owner@vger.kernel.org> On Behalf Of Geert Uytterhoeven
> Sent: 21 January 2019 13:14
>
> According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
> the parent clock of the DU module clocks on RZ/G2 is S1D1.
>
> Fixes: 906e0a4a6d1ef2d3 ("clk: renesas: cpg-mssr: Add r8a774c0 support")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Thank you Geert!
Kind regards, Chris
> ---
> To be queued in clk-renesas-for-v5.1.
>
> drivers/clk/renesas/r8a774c0-cpg-mssr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> index 28bcc8105d579611..4f3111b3113ecce8 100644
> --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> @@ -175,8 +175,8 @@ static const struct mssr_mod_clk
> r8a774c0_mod_clks[] __initconst = {
> DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D4),
> DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D4),
> DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0),
> - DEF_MOD("du1", 723,
> R8A774C0_CLK_S2D1),
> - DEF_MOD("du0", 724,
> R8A774C0_CLK_S2D1),
> + DEF_MOD("du1", 723,
> R8A774C0_CLK_S1D1),
> + DEF_MOD("du0", 724,
> R8A774C0_CLK_S1D1),
> DEF_MOD("lvds", 727,
> R8A774C0_CLK_S2D1),
>
> DEF_MOD("vin5", 806,
> R8A774C0_CLK_S1D2),
> --
> 2.17.1
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-01-23 9:56 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-21 13:14 [PATCH] clk: renesas: r8a774c0: Correct parent clock of DU Geert Uytterhoeven
2019-01-21 13:15 ` Geert Uytterhoeven
2019-01-23 9:56 ` Simon Horman
2019-01-21 13:47 ` Chris Paterson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).