[PATCH 1/2] clk: ingenic: Fix round_rate misbehaving with non-integer dividers

[PATCH 1/2] clk: ingenic: Fix round_rate misbehaving with non-integer dividers

[Paul Cercueil]

Take a parent rate of 180 MHz, and a requested rate of 4.285715 MHz.
This results in a theorical divider of 41.999993 which is then rounded
up to 42. The .round_rate function would then return (180 MHz / 42) as
the clock, rounded down, so 4.285714 MHz.

Calling clk_set_rate on 4.285714 MHz would round the rate again, and
give a theorical divider of 42,0000028, now rounded up to 43, and the
rate returned would be (180 MHz / 43) which is 4.186046 MHz, aka. not
what we requested.

Fix this by rounding up the divisions.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Maarten ter Huurne <maarten@treewalker.org>
Cc: <stable@vger.kernel.org>
---
 drivers/clk/ingenic/cgu.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 5ef7d9ba2195..b40160eb3372 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -426,16 +426,16 @@ ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
 	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
 	struct ingenic_cgu *cgu = ingenic_clk->cgu;
 	const struct ingenic_cgu_clk_info *clk_info;
-	long rate = *parent_rate;
+	unsigned int div = 1;
 
 	clk_info = &cgu->clock_info[ingenic_clk->idx];
 
 	if (clk_info->type & CGU_CLK_DIV)
-		rate /= ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);
+		div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);
 	else if (clk_info->type & CGU_CLK_FIXDIV)
-		rate /= clk_info->fixdiv.div;
+		div = clk_info->fixdiv.div;
 
-	return rate;
+	return DIV_ROUND_UP(*parent_rate, div);
 }
 
 static int
@@ -455,7 +455,7 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
 
 	if (clk_info->type & CGU_CLK_DIV) {
 		div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);
-		rate = parent_rate / div;
+		rate = DIV_ROUND_UP(parent_rate, div);
 
 		if (rate != req_rate)
 			return -EINVAL;
-- 
2.20.1.495.gaa96b0ce6b

[PATCH 2/2] clk: ingenic: Fix doc of ingenic_cgu_div_info

[Paul Cercueil]

The 'div' field does not represent a number of bits used to divide
(understand: right-shift) the divider, but a number itself used to
divide the divider.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Maarten ter Huurne <maarten@treewalker.org>
Cc: <stable@vger.kernel.org>
---
 drivers/clk/ingenic/cgu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
index 502bcbb61b04..e12716d8ce3c 100644
--- a/drivers/clk/ingenic/cgu.h
+++ b/drivers/clk/ingenic/cgu.h
@@ -80,7 +80,7 @@ struct ingenic_cgu_mux_info {
  * @reg: offset of the divider control register within the CGU
  * @shift: number of bits to left shift the divide value by (ie. the index of
  *         the lowest bit of the divide value within its control register)
- * @div: number of bits to divide the divider value by (i.e. if the
+ * @div: number to divide the divider value by (i.e. if the
  *	 effective divider value is the value written to the register
  *	 multiplied by some constant)
  * @bits: the size of the divide value in bits
-- 
2.20.1.495.gaa96b0ce6b

Re: [PATCH 2/2] clk: ingenic: Fix doc of ingenic_cgu_div_info

[Stephen Boyd]

Quoting Paul Cercueil (2019-01-27 18:09:21)
> The 'div' field does not represent a number of bits used to divide
> (understand: right-shift) the divider, but a number itself used to
> divide the divider.
> 
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> Signed-off-by: Maarten ter Huurne <maarten@treewalker.org>
> Cc: <stable@vger.kernel.org>
> ---

Applied to clk-next

Re: [PATCH 1/2] clk: ingenic: Fix round_rate misbehaving with non-integer dividers

[Stephen Boyd]

Quoting Paul Cercueil (2019-01-27 18:09:20)
> Take a parent rate of 180 MHz, and a requested rate of 4.285715 MHz.
> This results in a theorical divider of 41.999993 which is then rounded
> up to 42. The .round_rate function would then return (180 MHz / 42) as
> the clock, rounded down, so 4.285714 MHz.
> 
> Calling clk_set_rate on 4.285714 MHz would round the rate again, and
> give a theorical divider of 42,0000028, now rounded up to 43, and the
> rate returned would be (180 MHz / 43) which is 4.186046 MHz, aka. not
> what we requested.
> 
> Fix this by rounding up the divisions.
> 
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> Tested-by: Maarten ter Huurne <maarten@treewalker.org>
> Cc: <stable@vger.kernel.org>
> ---

Applied to clk-next