[PATCH v3 3/5] clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents

[Simon Horman <horms+renesas@verge.net.au>]

Support Z and Z2 clocks with parent frequencies greater than
UINT32_MAX Hz (~4.29GHz).

The DIV_ROUND_CLOSEST_ULL() macro accepts a 64bit numerator and 32bit
denominator. This leads to truncation of the numerator, which is the Z or
Z2 parent clock frequency in HZ, on platforms where frequency of that clock
is greater than UINT32_MAX Hz.

To resolve this problem the DIV_ROUND_CLOSEST() macro, which accepts the
prevailing types of the numerator and denominator, is used. In this case
the type of the numerator is unsigned long long (64 bit) and the type of
the denominator is unsigned long (64bit on 64bit platforms and 32bit on
32bit platforms). This allows parents whose frequency is greater than
UINT32_MAX Hz on 64bit platforms.

This appears to be sufficient as this driver is only intended for use
on 64bit systems. And in particular, the motivation for this change is
to allow a 4.8GHz clock on the R-Car Gen3 E3 (r8a77990) SoC which is
a 64bit platform.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v2: New patch
---
 drivers/clk/renesas/rcar-gen3-cpg.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 6b146c2cf6a3..236a7d9d94bd 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -120,8 +120,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned int i;
 	u32 val, kick;
 
-	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * zclk->fixed_div,
-				     parent_rate);
+	mult = DIV_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, parent_rate);
 	mult = clamp(mult, 1U, 32U);
 
 	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
-- 
2.11.0